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Basically the problem seemed to be that all directories in the path must exit, and the total path must be less than 126 char. In respect of the dongle, you can replace the IC with a faster one. I forget the part number now, but I can dig the old one out if needed. The faster version was obvious -- from memory it was a 4000 family CMOS device and you can fit the 74 equivalent. Fitting older parallel ports worked for a while, but not for ever. -- Gavin Melville gavin@cypher.co.nzArticle: 8526
hi pete, this is not too disimilar to the pci spec, where for many signals you are required to actively drive the output to a logic high before tri-stating, and then the "pullup" only has to supply leakage current. stops inputs from oscillating on the slow rise of a resistor pullup (or avoids the low resistor values) as well as limiting the power dissipation when the slowly rising input keeps both p and n-channel fets on by having a high slew rate between Vil and Vih. if the gray matter is still working correctly, the earliest i have seen this trick is on HPIB interfaces, where it would speed things up for heavily loaded busses, when the spec is violated and the number of cable-feet/instrument is kind of high. it sounds like the XL has enough drive for the isa busses, as it's compatible with 74lsxx stuff. my isa book isn't handy so the only thing to watch out for is a few special lines where fairly high drive is required; these lines are common open-collector and have a low pullup (int, cs16, anybody remember?). i think it's 16 or 20 mA so this should make it; 20 mA * 20.5 ohm = 410 mV. lastly, for ivan, be careful with the 330 ohm trick - sprinkle them on a few cards in the same system and the bus will be overloaded. -------------------------------------------------------------- rk "there's nothing like real data to screw up a great theory" - me (modified from original, slightly more colorful version) -------------------------------------------------------------- Peter Alfke <peter@xilinx.com> wrote in article <34AFAD61.9DA0B856@xilinx.com>... : Ivan wrote: : : > I'm using the Xilinx 4010XL and would like to interface it to : > the standard PC ISA bus. The IC's inputs are 5V tolerant, but can the : > outputs drive the 5V sensitive IS bus directly? : > : : I don't have the ISA spec here, but I can tell you what the XC4000XL : outputs can do: : : Actively pulling Low, the output impedance is between 14.4 and 20.5 Ohm, : but the dc current should not continuously exceed 20 mA ( metal : migration is the limiting factor). : Actively pulling High, the output source impedance is 28 to 41 Ohm, same : current warning. : : Driving more than its own Vcc is not possible, and you also cannot pull : the active High output any higher than Vcc, since a CMOS output is : resistive in both directions of current. : : The simple solution is to use "open collector" with a resistive pull-up, : which really slows you down on the way to 5V. : : But: : You can be sneaky and drive an active High level, but use the input : coming from the same pin, and make it shut off the output drive ( OE ). : Thus you get the benefit of a 30 Ohm impedance driving to 3.3 V, and the : resistor ( 330 Ohm?) only has to finish the work. If teh OE control is : a few ns slow, that actually helps in this case. : : It's a really neat trick ! Somebody else in Xilinx beat me to it, I am : green with envy. : : We have characterized this, and it works like a champ. : : Peter Alfke, Xilinx Applications : : :Article: 8527
Stuart Clubb <s_clubb@die.spammer.netcomuk.co.uk> wrote in article <34aea14b.10079414@nntp.netcruiser>... : On Sat, 03 Jan 1998 08:53:23 GMT, z80@ds.com (Peter) wrote: : <snip> : >>What the tool flow will be (Schematics anyone?). : >Depends on the above. Schematics are certainly an easier way to get : >into FPGAs in a quick and useful way than VHDL etc. : : Schematics are a little unwieldy for large devices. IMHO decent : quality VHDL wins out almost all the time now. I've seen designers : battle away at 8K gate designs and have over 100 printed sheets of : schematics. Takes them ages to get to market too. (I once saw 18 : months of engineering time go up in smoke because they missed their : market window) don't forget high quality macro generators. the ones that i've used are very tight and execute very quickly. and for many designs, a bunch of macros can be hooked together very quickly in a schematic much quicker than a full vhdl version of the design can be coded. 100 printed sheets for an 8k design - well, for starters, it must have been 'A' size! but it takes just too long to type in 8k-gates worth of stuff. an hdl (carefully avoiding ignition of a vhdl-verilog war) and macro generators are pretty good for a good deal of circuitry now, unless something very special needs to be done. i don't think there's much need to hand code ripple counters, synchronous up/down counters, shift registers, adders, comparators, decoders, multiplexors etc., etc., etc. takes too long and just typing it in is too error prone. : >>Big FPGA's become like big ASIC designs, so why not do the ASIC? : >Quite. I reckon the very big FPGAs are useful for very specialised low : >volume high cost products, but much more for ASIC prototyping. Either : >way, volumes will be low. : : Ahh, the phrase "ASIC prototyping". Guaranteed to strike fear into the : heart of every fpga manufacturer (unless they are looking for an 'in' : to the customer). and don't forget low-volume, quick-turn asic houses like chip express. they sort of fill a niche between the fpga and the asic and can spin stuff quick (measured in days). and their moderate volume stuff is measured in a week or so. also, anyone have any experience with the gatefield products? <snip> : >I know lots of people who use FPGAs, and their ways of doing things : >just don't square up with the FPGA vendor PR stuff in the press. : >People still use large volumes of 10 year old XC3020 and 3030, because : >they replace a lot of logic and are cheap. while i see more applications for the larger fpga's, i still use lots of 2,000 gate 1020's. <snip> : You might find the vendors decide to cease production of low density : parts such as 3000 series type densities. After all, if you pay (say) : $3 for a 3020, and they all reach the promised $1 for 5K gates, then : you'll probably be offered a 15K gate part as a starting point whether : you like it or not. Of course, it'll have to be 1.8V with 3.3V I/O, : and if you want a pure 5V part, you'll get screwed with an old 0.5 : micron technology and price. actel might hit an interesting spot with their new mx family at 0.45 um, which supports both 5 and 3.3 volt i/o, with full 5v swings for good noise margin and low power. and they're quoting (high volume) $7 for a 16,000 gater (8,000 gate array gates) and $4.90 for a 4,000 gater - it'll be interesting to see what the price is in batches of 25. it's a bit of a trade-off here, since we'll be stuck driving 5V CMOS levels for a while. also, personally, i get a bit nervous with the poor noise margin of the '0' for ttl levels and was glad when things moved to 5V cmos (boy, i just read this and i sound old!). just a few thoughts, -------------------------------------------------------------- rk "there's nothing like real data to screw up a great theory" - me (modified from original, slightly more colorful version) --------------------------------------------------------------Article: 8528
I'm using more than 120 flip-flop in EPM7256SQC208-15 with global clock. It looks like other problem not fan-out problem. Can you describe in detail of the problem or send the design file to me? Thanks D.H. peace wrote: > I'm using Altera's EPM7128SQC100-15 in a design . I have a > problem in my design . > > In my desing , a global clock is used and it has 30 fan-out . But > it looks like it hasn't enough drive ability as many flip-flop don't > work . Who can tell me how to resolve the problem ?Article: 8529
The ISA bus is basically a TTL bus and can therefore be driven by the XL parts in TTL mode. Unfortunately, there was no original detailed electrical spec for ISA, but IBM did specify the loading and signaling type in their documentation: Page 1-22 of IBM AT Technical Reference, #1502494, March 1984 "The following is a description of the system board's I/O channel signals. All signal lines are TTL-compatible. I/O adapters should be designed with a maximum of two low-power Shottky (LS) loads per line." (and, yes, IBM did misspelt Schottky) In the book ISA & EISA Theory and Operation by Edward Solari, ISBN 0-929392-15-9, this information is repeated on page 441. (with spellink corrected) Solari goes on to give a fairly normal table of voltages: Voltage out, at a slot: logic High >= 2.4V , Logic Low <= .5V with -4mA and +24mA respectively. Address and data lines are either unterminated, or may have 10K resistors to float busses high. Control lines are pulled high with 4.7K, OC lines are pulled high with 4.7K, 1.0K, or 300 ohms, depending on the signal. Expected Input voltage requirements for an adapter card are standard TTL: Voltage in, at a slot: Logic High >= 2.0V , Logic Low <= .8V with 40uA and -400uA respectively. XC4000XL devices in TTL mode meet all these specs, except for the logic low drive current specification. Solari suggests 24mA, Xilinx specs 12mA. Here is the calculations: 74LSxxx parts input low loading is 0.25 uL which translates to 0.25 * 1.6mA = 400uA (Fairchild TTL data book, mid 1970's vintage). IBM says no more than two such loads per slot. (they say nothing about how many loads the motherboard might be). So Iol per slot is 800uA. If the motherboard was 5 loads (quite pessimisic), and there were 6 adapter boards plugged in , then we would have (6+5) * .8 = 8.8mA, so the XL outputs at 12mA meet this spec too. Peter's recomendations in another article seem to be quite excessive, given the actual requirements of the bus. Philip Freidin. In article <34add42b.323104@news.globalserve.net> ivan@caseware.com (Ivan) writes: > > I'm using the Xilinx 4010XL and would like to interface it to >the standard PC ISA bus. The IC's inputs are 5V tolerant, but can the >outputs drive the 5V sensitive IS bus directly? > > Thanks in advance, > Ivan.Article: 8530
Hi,
I am just getting into fpga and was hopefull for some guidance.
1) The first project I need to design will replace the following
standard TTL stuff:
5) HC157
1) HC174
1) HC166
6) HC161
1) HC74
1) HC123
4) HC245
20 to 25 AND / OR gates
1) 256 X 4 ROM
and hopefully
1) 256 X 8 SRAM
2) I am looking at XILINX and QuickLogic and trying to figure if the
above TTL stuff will fit. Is there an easy way to see what will fit?
3) Low cost development software - any suggestions - there seems to
be a lot out there. Schematic entry seems to be the best to me as the
hardware is already designed for the TTL stuff.
4) I know that I have some learning to do, but I would like to get
started in the right direction before spending $$ and a lot of time
making the right move into a mfg and software vendor.
5) I would be greatful for any help!
Thanks
Mike
Article: 8531hi, I've a relatively large design in Verilog which is for 10K100. It uses approx. ~500 DFFs and a total of 2500 LCs when synthesized with Synopsys FE and runs at 13Mhz. When synthesized with Exemplar Leonardo (even with beta 4.2, normally using 4.1.5) I get approx. 3400 LCs (the number of DFFs doesn't change) and the speed is only around 8Mhz. Has anyone else observed similar results with these two products and how can I improve the results in Leonardo ? thanks muzo WDM & NT Kernel Driver Development Consulting <muzok@pacbell.net>Article: 8532
11th Annual 1998 IEEE International ASIC Conference
CALL FOR PAPERS
ULSI - MAKING IT REAL
September 13-16, 1998
Rochester, New York
Sponsored by the IEEE Rochester Section
in cooperation with the IEEE Solid State Circuits Society
http://asic.union.edu
The ASIC Conference provides a forum for sharing recent
advances in VLSI technology and design capabilities, and
their application to meeting system engineering require-
ments. The theme of this year's conference, "Making ULSI
Real", emphasizes the path from vision to reality of Ultra
Large Scale Integration. The 1998 Conference will offer a
full day of technical workshops on Sunday, the first day of
the conference. On Monday, Tuesday, and Wednesday we will
present parallel sessions of technical papers and tutorials.
In addition, ASIC'98 will acknowledge the best presented
paper with a Best Paper Award. You are invited and encour-
aged to submit original works on the following (or related)
areas of interest:
+ ASIC Applications, Architectures, Digital Signal
Processing,
+ High Level Building Blocks, Embedded Cores & Memories,
+ Mixed-Signal/Analog High Performance, Communications,
+ Synthesis, Test, & CAD Methodology, Low Power Devices,
+ Structures & Technology.
Special sessions will be devoted to
MEMS/CMOS Integration and Imaging Sensors and Systems.
**Submission of Papers**
The paper should address new developments in your field of
study. The content of the paper must present new and previ-
ously unpublished work. The paper must clearly state the
advances proposed; therefore, sufficient results (measured
or simulated) and diagrams must be presented to demonstrate
the quality and originality of the contributed work. The
paper (limit to four pages) must include a 50 word or less
summary along with the composite paper (text, figures,
tables, references, etc.). Proposals for workshops are also
invited. Deadline for submission is April 10, 1998. Please
visit our website or contact Ms. Michael Ellis at IEEE Con-
ference Services, 732.562.5362 for detailed information on
paper submissions.
Conference Chair Technical Co-Chair Technical Co-Chair
-------------------------------------------------------------------------
-- Mark Schrader, Eastman Dr. R.Sridhar, SUNY Dr. Tom Buechner Kodak
Buffalo IBM schrader@kodak.com rsridhar@eng.buffalo.edu
tom_b@vnet.ibm.com
Steering Comittee Chair Workshop Chair Publications Chair
-------------------------------------------------------------------------
-- Dr. P. R. Mukund Dr. Cherrice Traver Dr. Robert Daash Rochester
Institute of Union College Portland State Technology
traverc@doc.union.edu University prmeee@cs.rit.edu daasch@ee.pdx.edu
Please contact the Workshop Chair regarding submitting a summary
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For Exhibit/Vendor Exposition, please contact: Ms. Michael Ellis at IEEE
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Article: 8533Hi, does anyone where I can find a VHDL model for Synchronous DRAM?Article: 8534
Mike Panson wrote: > Hi, > > I am just getting into fpga and was hopefull for some guidance. > > 1) The first project I need to design will replace the following > standard TTL stuff: I suggest the Xilinx XC4000 series.I am filling in a conservative CLB-count. That's how we measure our device size. > > > 5) HC157= 5 x 2 CLBs= 10 CLBs > 1) HC174= 2 CLBs > 1) HC166=4 CLBs > 6) HC161= 6 x 3 CLBs= 18 CLBs > 1) HC74 = 1 CLB > 1) HC123 seems to be a monostable, avoid that > 4) HC245 = most likely for free inside the Xilinx chip > 20 to 25 AND / OR gates somewhere between 2 and 10 CLBs > > 1) 256 X 4 ROM = 32 CLBs for content plus 4 CLBs for address > decoding > and hopefully > 1) 256 X 8 SRAM= 64 CLBs for ctorage plus 4 CLBs for address > decoding So the total is less than 60 logic CLBs, plus 96 CLBs for ROM/RAM,for a total of 156 CLBs Your best choice is the XC4005E ( 5V ) or XC4005XL ( 3.3V). Both have 196 CLBs. If you want to add significant amounts of logic, there are bigger parts ( 4006, 4008, 4010, 4013 etc) and they come in pin-compatible packages, so you don't even have to change the pc-board. The appropriate software package is called Foundation Base, covering up to XC4010E. The price is 95 dollars as a special promotion. I hope that is really inexpensive ( not cheap!) enough. If you don't believe me, click on: http://www.xilinx.com/products/software/found/baseblst/valpromo.htm Good luck with your design. It's going to be very easy, once you convert the monostable into a digital differentiator or equivalent. Send me e-mail if you have a problem: peter@xilinx.com Peter Alfke, Xilinx Applications > > > 2) I am looking at XILINX and QuickLogic and trying to figure if the > above TTL stuff will fit. Is there an easy way to see what will fit? I doubt that Quicklogic will make you as nice an offer. > > > 3) Low cost development software - any suggestions - there seems to > be a lot out there. Schematic entry seems to be the best to me as the > > hardware is already designed for the TTL stuff. As I said, ninety-five bucks. Contact your Xilinx rep or sales office. > > > 4) I know that I have some learning to do, but I would like to get > started in the right direction before spending $$ and a lot of time > making the right move into a mfg and software vendor. Welcome to the exciting world of FPGAs.PeterArticle: 8535
Lars (larsherm@sn.no) wrote: : Hi, : does anyone where I can find a VHDL model for Synchronous DRAM? Please check www.denalisoft.com for SDRAM and other memory models. Sanjay Srivastava sanjay@denalisoft.comArticle: 8536
Lars wrote: > Hi, > does anyone where I can find a VHDL model for Synchronous DRAM? Virtual Chip sells such models. ByeArticle: 8537
Mike, Check out the low price kits from APS at : http://www.associatedpro.com/aps You will al;so get an FPGA board with the kit. The board alows you to try the actual implementation of the logic. It saves alot of time and the schematics to the board are included in the package with interface tips and C control and download boilerplates. Mike Panson wrote: > Hi, > > I am just getting into fpga and was hopefull for some guidance. > > 1) The first project I need to design will replace the following > standard TTL stuff: > > 5) HC157 > 1) HC174 > 1) HC166 > 6) HC161 > 1) HC74 > 1) HC123 > 4) HC245 > 20 to 25 AND / OR gates > > 1) 256 X 4 ROM > and hopefully > 1) 256 X 8 SRAM > > 2) I am looking at XILINX and QuickLogic and trying to figure if the > above TTL stuff will fit. Is there an easy way to see what will fit? > > 3) Low cost development software - any suggestions - there seems to > be a lot out there. Schematic entry seems to be the best to me as the > hardware is already designed for the TTL stuff. > > 4) I know that I have some learning to do, but I would like to get > started in the right direction before spending $$ and a lot of time > making the right move into a mfg and software vendor. > > 5) I would be greatful for any help! > > Thanks > > Mike -- __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ Richard Schwarz, President EDA & Engineering Tools Associated Professional Systems (APS) http://www.associatedpro.com 3003 Latrobe Court richard@associatedpro.com Abingdon, Maryland 21009 Phone: 410.569.5897 Fax:410.661.2760 __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/Article: 8538
Yes, Denali Software, http://www.denalisoft.com. Have all models in all classes. Lars (larsherm@sn.no) wrote: : Hi, : does anyone where I can find a VHDL model for Synchronous DRAM?Article: 8539
Mike Panson wrote: > Hi, > > I am just getting into fpga and was hopefull for some guidance. > > 1) The first project I need to design will replace the following > standard TTL stuff: > > 5) HC157 > 1) HC174 > 1) HC166 > 6) HC161 > 1) HC74 > 1) HC123 > 4) HC245 > 20 to 25 AND / OR gates > > 1) 256 X 4 ROM > and hopefully > 1) 256 X 8 SRAM > > 2) I am looking at XILINX and QuickLogic and trying to figure if the > above TTL stuff will fit. Is there an easy way to see what will fit? > > 3) Low cost development software - any suggestions - there seems to > be a lot out there. Schematic entry seems to be the best to me as the > hardware is already designed for the TTL stuff. > Check out also www.altera.com for free software and devices which will fit this requirement. > 4) I know that I have some learning to do, but I would like to get > started in the right direction before spending $$ and a lot of time > making the right move into a mfg and software vendor. > > 5) I would be greatful for any help! > > Thanks > > Mike Mike, Please drop me a line if you want me to help draw up a small section etc for your design etc. in an Altera Device Regards, Steven Groom Field Applications Engineer Arrow (NZ)Article: 8540
CAE MRad Pty Ltd is a world leader specialising in the development of military sensor testing and training systems for Australian and International Defence customers for airborne, air defence and naval applications. CAE MRad has a vacancy for a young engineer who has gained some experience since graduation, and who wants to put that experience towards developing leading edge products in a focused team environment. You will have experience in: high speed digital design, embedded digital signal and micro-processor implementation and real-time software in embedded environments. Your experience with Altera MAX+PLUS II Programmable Logic Development Systems and your aptitude for RF design will be well regarded. You will have a university engineering degree in electrical, electronics, computer systems or a related discipline. For more information, please contact: Mr Neville Phillis Engineering Manager, CAE MRad Pty Ltd Innovation House West, Technology Park, South Australia 5095 Phone (08) 8260 8942 Fax (08) 8260 8980 E-mail: nevillep@mrad.com.au Closing date is 16 January 1998. Only principals need apply. -- Jon Schutz Systems Engineering Manager CAE MRad Pty Ltd Ph: 61-8-82608942 Innovation House West Fax: 61-8-82608980 Technology Pk E-mail: Jon.Schutz@mrad.com.au South Australia 5095Article: 8541
Do serial EEPROMS exist for Xilinx configuration in the market to replace Xilinx OTP PROMS?Article: 8542
--------------57B771720F28A3CAD96AC1E4 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Peter Alfke wrote: > Mike Panson wrote: > > The appropriate software package is called Foundation Base, covering up > to XC4010E. > The price is 95 dollars as a special promotion. > I hope that is really inexpensive ( not cheap!) enough. > If you don't believe me, click on: > > http://www.xilinx.com/products/software/found/baseblst/valpromo.htm To your information, the special promotion price was valit till 12/31/97 -- Kind regards, Hendrie Dorland IC Centre, R&D Huizen, Netherlands hdorlan@lucent.com Room: HV204, tel: (+31-35-687)5382 --------------57B771720F28A3CAD96AC1E4 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <HTML> Peter Alfke wrote: <BLOCKQUOTE TYPE=CITE>Mike Panson wrote: <P>The appropriate software package is called Foundation Base, covering up <BR>to XC4010E. <BR>The price is 95 dollars as a special promotion. <BR>I hope that is really inexpensive ( not cheap!) enough. <BR>If you don't believe me, click on: <P><A HREF="http://www.xilinx.com/products/software/found/baseblst/valpromo.htm">http://www.xilinx.com/products/software/found/baseblst/valpromo.htm</A></BLOCKQUOTE> To your information, the special promotion price was valit till 12/31/97 <PRE>-- Kind regards, Hendrie Dorland IC Centre, R&D Huizen, Netherlands hdorlan@lucent.com Room: HV204, tel: (+31-35-687)5382</PRE> </HTML> --------------57B771720F28A3CAD96AC1E4--Article: 8543
Hi,
I wonder if anybody can help me. I am trying to synthesize a very large 24 by 1
bit look-up table. Of the 32M addresses 64231 should produce a ‘1’. I know this
table is very large and possibly synthesis is not feasible, however, I would
like to have a go at it.
Currently I have converted the table into a simple case construct (see end
message) and the plan is to synthesis this table in small chucks and connect
them up in a top level file.
I hope that by flattening this top file during synthesis an FPGA implementable
result can be achieved. Am I trying to achieve the impossible?
I used McBOOLE which compiled some of my other look-up tables (256 bytes) in a
fraction of the time (1 second) compared to ACTMAP (ASYL+, 10 minutes) and
Altera 8.1 (stopped after 20 minutes). However, McBOOLE could not handled the
large 24*1 table (return negative numbers, possible int versus long). I looked
for espresso but so far I only found the UNIX sources (same with several BDD
implementations). Before I attempt to recompile this enormous program under DOS
did anybody attempt this? Are there special Boolean optimization techniques for
large number of variables?
Thanks,
Hans.
Example file;
port (
signal abus : in std_logic_vector(23 downto 0);
signal dbus : out std_logic);
end j1j2;
architecture synthesis of j1j2 is
begin
process(abus)
begin
case abus is
when "000000010000000100000001" => dbus <='1';
when "000000010000001000000100" => dbus <='1';
……………………..
64231 addresses
……………………..
when others => dbus <='0';
end case;
end process;
Article: 8544Yes, look at Atmel's AT17CXXX where xxx is the size. regards jerry englishArticle: 8545
Hello, Various memory Verilog and VHDL models are available at Micron's Web Site. Better yet, it's FREE. Check it out at: http://www.micron.com/mti Son Huynh Lars wrote in message <34B231F4.6468@sn.no>... :Hi, :does anyone where I can find a VHDL model for Synchronous DRAM?Article: 8546
Hi gang,
I am working on improving the timekeeping of FreeBSD to get it into the
nano-second range. I have come to need a little bit of hardware
assistance and to my dismay I have found that the hardware I need does
not exist.
Knowing that the gang in this group can make any kind of hardware exist,
I hope that somebody out there can help me produce a couple of these
gadgets for my experiments.
Description:
A) 32 bit synchronous counter, input clock selectable
either from external pin or from PCI clock.
The frequency will generally be in the 5..50 MHz
range, the higher it can do the better.
This counter must be readable from the PCI interface.
B) 32 bit latch which captures the above counter at
the rising edge of an external signal.
This latch must be readable from the PCI interface.
(I wouldn't mind if there were a multiple of these
registers.)
C) Standard 32-bit PCI interface.
D) PCB with PCI connector and connections for the
external signals mentioned above. (It is alright
to use any existing PCB you may have already.)
I'm not rich, and I do FreeBSD in my sparetime, so I
cannot hire a company to do this for me, but I'm hoping
that somebody out there could help me produce a couple of
these gadgets at a price I can afford...
If you happen to know any existing hardware that does
more or less the above, that would also make me happy.
They key features are the 32 bit width and the PCI
interface.
You may be able to sell a couple of these to other people
than me, the software will be available for free and it
will make a standard PC run circles around any other
computer when it comes to timekeeping as a NTP stratum
1 server, but don't expect to sell hundred of them.
Please respond by email, I'm in the far end of the world
so news take forever to get here..
Thanks in advance,
Poul-Henning Kamp
FreeBSD core-team member
phk@FreeBSD.org
Article: 8547Yekta Ayduk wrote: > Do serial EEPROMS exist for Xilinx configuration in the market to > replace Xilinx OTP PROMS? I don't know if this helps, but Altera make a EPC1441 which is flash based, from what I gather the interface is similar for the Xilinx part - maybe this might work? Regards, Steven Groom Field Applications Engineer Arrow (NZ)Article: 8548
Hans wrote:
> Hi,
>
> I wonder if anybody can help me. I am trying to synthesize a very large 24 by 1
> bit look-up table. Of the 32M addresses 64231 should produce a ‘1’. I know this
> table is very large and possibly synthesis is not feasible, however, I would
> like to have a go at it.
I don't know about VHDL, but Altera AHDL would have a statement like...
case a[] is
when 64231 =>
cs=1;
when others =>
cs=0;
end case;
Does this help?
Regards,
Steven Groom
Field Applications Engineer
Arrow (NZ)
Article: 8549Can anyone point me to a design example for implementating a pulse width modulation (PWM) circuit in a PLD? Design handbooks, tutorials, app notes? Thank you -- Randy Bickford Expert Microsystems, Inc. Tel (916) 989-2018 7932 Country Trail Drive, Suite 1 Fax (916) 989-4277 Orangevale, Ca 95662-2120 rando@expmicrosys.com http://www.expmicrosys.com
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