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Hi G=F6ran, Thanks a lot for your support - it was realy helpful.. Best regards, Mordehay. G=F6ran Bilski wrote: > No, The only thing that might happen is that you will not reach the timing > constraints. > > G=F6ran > > <me_2003@walla.co.il> wrote in message > news:1162900739.332371.6350@m73g2000cwd.googlegroups.com... > Hi Goran, > Thanks again for your response. > when using the -ir option I managed to get my PAR right, but now I'm > worried about the results of not using the RLOC constraints. Is there a > danger that my design wont work properly now ? > Thanks again, Mordehay. > >Article: 111651
Hi my friends, We know little about Spartan and Xilinx. We are connecting our Spartan 3 starter kit board to a PC and using Xilinx ISE 8.1 to control it. We want to find a way to load our program ( instructions) into the memory of the Spartan board. Could you tell me how? We will appreciate it if you could kindly show some light on this.Article: 111652
Hi Aaron,
"Aaron Curtin" <acurtin@modspike.com> wrote in message
news:1162911143.189373.118150@h54g2000cwb.googlegroups.com...
> I then decided to create a
> float variable with its value initialized to 0.5 and displayed it. The
> result was the same leading me to believe that the problem lies
> elsewhere?
>
> float x = 0.5;
> putnum (x); // this displays 3FE00000
Where is putnum() declared? What is its argument type? Most likely the
compiler does not know that putnum takes a 32-bit float argument and is
passing the value of x by converting it to 64-bit double. Try
union
{ float f;
unsigned int i;
} x;
x.f = 0.5;
putnum(x.i);
...and see if that prints the correct value. A union is the only truly safe
way to re-interpret a bit pattern from one type to another in C.
Cheers,
-Ben-
Article: 111653Hi, I try to connect my off-chip 16 bits wide SRAM to a Nios 2 system by using a tristate bus. In the documentation of the avalon interface: For Avalon tristate slave ports, the address signal represents a byte address. This is different behavior than non-tristate slave ports, which use word addresses. For tristate slave ports, the address signal can be shared among multiple off-chip devices, and these devices might have differing data widths. If the Avalon tristate slave port data width is greater than one byte, then it is necessary to correctly map the address signals from the Avalon switch fabric to the address lines on the slave device. Table 5: Connecting External Device AO to Avalon address Data Width AO connects to 1-8 avalon_address[0] 9-16 avalon_address[1] 17-32 avalon_address[3] 33-64 avalon_address[3] 65-128 avalon_address[4] How should I connect my 16 bits wide sram address to the avalon interface? I tried the next line: avalon_address : in std_logic_vector(17 downto 0); sram_address : out std_logic_vector(16 downto 0); sram_address <= avalon_address(17 downto 1); in this case the avalon_address is 17 downto 0. This will result in a memory space of 512 kB in the sopc builder while it should be 256 kB! When I make the avalon_address 16 downto 0, I get the right memory space in sopc builder (256 kB) but I miss an address line for my chip: avalon_address : in std_logic_vector(16 downto 0); sram_address : out std_logic_vector(16 downto 0); sram_address <= '?' & avalon_address(16 downto 1); The idea was to connect it like this: avalon_address : in std_logic_vector(17 downto 1); sram_address : out std_logic_vector(16 downto 0); sram_address <= avalon_address(17 downto 1); Now I have the correct memory space, but how do I know if the mapping of my own signal avalon_address is done correctly to the real avalon tristate interface? avalon_address 17 => to real avalon tristate address(17) . . avalon_address 1 => to real avalon tristate address(1) Does anyone know if this is the right way, or would it internally connect like this: avalon_address 17 => to real avalon tristate address(16) . . avalon_address 1 => to real avalon tristate address(0) Who has experience with this? TIA, FrankArticle: 111654
hi,
I've have debugging this for the whole afternoonn today, can not get
the problem away, becoming crazy.....
I've
1. writen a VHDL-Code for Serial-Parallel-Converter on the Virtex-4
FPGA(Both Pre-SImulation and Post-Simulation pass)
2. downloaded the file to the PROM
3. then feed the CLOCK signal, RESET signal and SERIAL input signal
with the Agilent Logic Analyser onto the FPGA
4. and then feed the 16-bits PARALLEL OUTPUT signal and a OUTPUT
CLOCK(16 times slowly as input clock) back to the LA.
However, there seems to be something wrong.
The output did NOT equal the input.
What the LA send:
rst_n clk_sd i_sd
1 0 0
1 1 0
... <= 32 clk, for 16 i_sd = 0
1 0 0
1 1 0
1 0 1
1 1 1
... <= 32 clk, for 16 i_sd = 1
1 0 1
1 1 1
... repeat
Theoretically, i'll get as output: 0000 0000 0000 0000, 1111 1111 1111
1111, ...... and repeat
But actually, i got
0000 0000 0111 111,
1111 1111 1000 000,
or
1111 1111 1111 1110,
0000 0000 0000 0001,
or something like this.
I've slow down the input clock from 150MHz to 1 MHz, i make the error
even worse!
I've no idea now, help me out!
Thanks
Cheng
Here is the VHDL-Code:
-- Description: Serial-Parallel Converter
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sp_conv is
port
(
rst_n: in std_ulogic; -- async reset for the converter
i_sd: in std_ulogic; -- serial input
clk_sd: in std_ulogic; -- input clock
clk_sd_par: out std_ulogic; -- output clock
o_sd_par: out std_ulogic_vector(15 downto 0) -- parallel output
);
end sp_conv;
architecture rtl of sp_conv is
signal sd_int: std_ulogic; --input register
signal sd_par_int: std_ulogic_vector(15 downto 0); -- intern output
register
signal cnt: unsigned(3 DOWNTO 0); -- count
signal init_flag: std_ulogic; -- Mask first bit after reset
signal cnt_flag: std_ulogic;
begin
process(rst_n, clk_sd)
begin
if(rst_n = '0') then -- by reset
sd_int <= '0'; -- input register reset
sd_par_int <= (others => '0'); -- intern output register reset
o_sd_par <= (others => '0'); -- parallel output reset
clk_sd_par <= '0'; -- output clock reset
cnt <= (others => '0') ; -- count reset
init_flag <= '0';
cnt_flag <= '0';
elsif(clk_sd'event and clk_sd = '1') then -- by clk_sd's rising
edge
init_flag <= '1';
if (init_flag = '1') then -- Count only the second edge
cnt <= cnt + 1;
end if;
sd_int <= i_sd;
sd_par_int(to_integer(cnt)) <= sd_int; -- input register ==>
intern output register (bit to bit)
if(cnt = 8) then
clk_sd_par <= '1'; -- generate the rising edge of the output clock
when count=8
cnt_flag <= '1';
elsif(cnt = 0 and cnt_flag = '1') then
clk_sd_par <= '0'; -- generate the falling edge of the output
clock when count=16
o_sd_par <= sd_par_int; -- output the intern output register when
all bits arrived
end if;
end if;
end process;
end rtl;
Article: 111655hi Sandip, Read "ISE 8.2i Quick Start Tutorial", the last step is telling you how to configure a device. However, it has not mentioned, how to generate a .bit file for FPGA and a .mcs file for PROM, you can change the properties in ISE, or done it with BITGEN and PROMGEN(read Development System Reference Guide for details). have fun :) Cheng Sandip schrieb: > Hi, > > I am using ML403 board with Virtex-4. I need to generate and download a > PROM file into the PROM and then use it after I switch it OFF and then > again ON. > Can anyone please help me out in doing so?? > > Thanks and regards, > SandipArticle: 111656
Hi everybody, I have a board with a spartan-II (xc2s200-5FG456) but I'm running out of area, I wonder if it's possible to mount another FPGA on the same board (without having to redo the board layout, or with minor modifcations like swapping a GND with a Vcc): someone told me that some Spartan3 are pin compatible with my FPGA, but the Spartan3 datasheet says the opposite. Does anybody know? Thanks, PlegArticle: 111657
jetmarc@hotmail.com wrote: > Hi, > > I'm having problems hosting a ISE/EDK 8.1 SP3 project on a file server. > > The server runs Samba3 on Redhat. The workstation is WinXP and mounts > a server folder with the "drive letter" method. > > When creating a new project, I get errors like "the destination folder > is read-only" (which is not true). When I create the project on a > local disk and copy it over to the network share later, most things > work. Only the EDK submodule continue to produce errors, for example > "error deleting ./src/microblaze - folder does not exist". > > EDK starts up with a message "CMD.EXE error, the current directory > (\\server\share\folder\) may not be a UNC network path, changing to > C:\". To me it seems that this may be the root cause for the > subsequent errors. > > Note that I never used the \\server\share path, but rather worked > through a driveletter mount. The ISE/EDK tools seem to resolve the > driveletter to a fully qualified network path, and then choke on it. > > Is there a solution for this? I would really like to host the project > on the server. I wouldn't mind to install other filesharing services > (or a windows file server), if that helps. I had the same problem. I think a work around is not to use the root directory of the network drive (i.e create a directory called XilinxProjects, then create project subdirectories in there), but I could be wrong. Cheers, JonArticle: 111658
We are also unsing Precision in here but found some naming and syntax incompatibilties as well as synthesis malfunctions with the Precision's output :-( I'm not a too strong Mentorfan ... Be careful what you are doing and keep an eye on the testers output... regards Mike Treseler schrieb: > avishay wrote: > > > I'm designing with Altera FPGA with their Quartus software. My company > > also have license for Mentor Graphics' Precision synthesis tool. From a > > very brief check, it seems that Quartus' built-in synthesizer gives > > comparable results to the Precision. I wonder if there is any advantage > > in using an external synthesis tool. What does it give me more than > > Quartus has to offer? > > Since you have the licenses, consider > running your code on both to verify > vendor independence. Quartus might > save time in synthesis/place+route > since it is a single tool. > > -- Mike TreselerArticle: 111659
"uvbaz" <uvbaz@stud.uni-karlsruhe.de> wrote in message news:1162918391.444371.308790@h48g2000cwc.googlegroups.com... > hi, > I notice rst_n never resets! Think sync SlurpArticle: 111660
If you are talking about the EEPROM or any other non-volatile on-board memory, it should be detected by Impact. Just create an PROM file (.mcs) from the .bit file and load it into the memory. All of this can be done inside impact and should be detailed in the user manual for your board. ---Matthew Hicks "Jialin" <jiaojialin@gmail.com> wrote in message news:1162913626.614634.231140@m73g2000cwd.googlegroups.com... > Hi my friends, > > We know little about Spartan and Xilinx. We are connecting our > Spartan 3 starter kit board to a PC and using Xilinx ISE 8.1 to control > it. > > We want to find a way to load our program ( instructions) into the > memory of > the Spartan board. Could you tell me how? We will appreciate it if you > could kindly show some light on this. >Article: 111661
Hi all, I try to convert a file with extension *.vwf (used in Quartus) to btim or tim one. I tried to use exported (Quartus option) to vht (vhd) format files in ModelSim Actel Customer version but with no success. Could you tell me why ModelSim (Libero Design Flow) doesn't see the testbench file created in that way (there is'nt any altera libraries in the code) and propose any solution? Thanks! Best regards, KarlArticle: 111662
Mark McDougall wrote:
> I'm having problems getting a simulation running. Here's the recipe...
> Quartus output VHO file - contains VHDL & Verilog components.
> Testbench components - VHDL & Verilog components.
Maybe you need a mixed language license from Mentor.
-- Mike Treseler
Article: 111663On Mon, 06 Nov 2006 09:50:02 +0100, David Brown <david@westcontrol.removethisbit.com> wrote: > >I'm sure the second core will make a difference - while the one long >task is occupying one core, other minor tasks will run on the other >core. While these other tasks might only take a tiny proportion of the >processor time, you avoid the penalties of task switching (like losing >your cache) on the working processor. > Assuming you set the thread affinity for the long task. If you observe top on linux or task manager on windows xp, vista you will se that the %99.9 cpu consuming task is being migrated from cpu to cpu quite frequently. I am not sure why the scheduler of either OS does this.Article: 111664
> You can check the performance of your design on platforms of different > vendors. Just a quick caution on this: Make sure you run through each respective vendor's P&R tools (with multiple seeds). The performance predictions from any synthesis tool are fundamentally limited by the lack of knowledge of real placement, routing and complete timing models. Regards, Paul Leventis Altera Corp.Article: 111665
Thanks, I also found http://www.xilinx.com/publications/xcellonline/xcell_53/xc_jtag53.htm. ---Matthew Hicks "Andreas Ehliar" <ehliar@lysator.liu.se> wrote in message news:eipn4d$f9l$1@news.lysator.liu.se... > On 2006-11-06, Matthew Hicks <mdhicks2@uiuc.edu> wrote: >> I know there exists a path for the XUP board to communicate with a PC via >> the USB port because Chipscope does it and I have seen projects using >> their >> own boards but with USB as a configuration (JTAG) and communication >> option. >> The user guide doesn't give any insight on the issue and I tried >> searching >> for info on the web to no avail. Any tips or suggestions? > > You want to google for BSCAN and Spartan3 (or virtex2, you don't state > what > XUP board you are using). > > Another link with information about this subject is > http://www.s3group.com/system_ic/gnat/ > > /AndreasArticle: 111666
Basically you don't stand much chance. Power supplies are different, S3 is not 5V tolerant whereas S2 is and so on. What you may be able to do is shrink your design. There are many techniques to do this with most relying on a good understanding architectures and synthesisers. I have seen up to about 40-50 percent reduction achieved but that depends on a awful lot of things. If play with settings in tools you might with lucky and get 10-20 percent size reduction so do try if that might be enough for your needs. John Adair Enterpoint Ltd. Pleg wrote: > Hi everybody, > I have a board with a spartan-II (xc2s200-5FG456) but I'm running out of > area, I wonder if it's possible to mount another FPGA on the same board > (without having to redo the board layout, or with minor modifcations like > swapping a GND with a Vcc): someone told me that some Spartan3 are pin > compatible with my FPGA, but the Spartan3 datasheet says the opposite. > Does anybody know? > > Thanks, > > > PlegArticle: 111667
Roberto wrote: > "trigger now" button, it does not give me the status of the lines. It > enters a mode where it says"siting for core to be armed." and stays > there forever. Am I setting the trigger in a wrong way? > Usually if ChipScope doesn't respond to "trigger now" that means that the ILA core is getting no clock input. -KevinArticle: 111668
karollo@o2.pl wrote:
> I try to convert a file with extension *.vwf (used in Quartus) to btim
> or tim one. I tried to use exported (Quartus option) to vht (vhd)
> format files in ModelSim Actel Customer version but with no success.
> Could you tell me why ModelSim (Libero Design Flow) doesn't see the
> testbench file created in that way (there is'nt any altera libraries in
> the code) and propose any solution?
A simulation testbench written in vhdl
or verilog is portable across vendors.
A waveform based simulation is not.
-- Mike Treseler
Article: 111669Mike Treseler wrote: > Maybe you need a mixed language license from Mentor. Already have, been running behavioural simulation with mixed-language for yonks! Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 111670
I should probably also add, I have done successful post-PAR simulation using VHO in the past on an ancestor of this very design! I didn't have the verilog module that is seemingly causing my current problems... Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 111671
Jim Granville wrote: > There are other threads on this. Xilinx _used_ to offer some on-line > shopping, but the level of service took a dive, as the bean-counters > held sway - so it is something of a sore point.... > I don't think it is Disti pressure,(but you never know...) as most > Disti's don't want to know about samples / small qty Maint orders. > Couple that with lead free changes, shrinking shelf lives, and larger > SPQs, most Distis try to avoid carrying ANY stock at all, of a > "speculative" nature. > > Welcome to the world of short life cycle parts... > Yes, I was really shocked when I called one of the on-line warehousers of hard to get parts and he told me that although his web site lists something like 30,000 of one part available from a raft of different locations, none of them actually exist! (That wasn't actually a Xilinx part, but TI. But, if their policies are such, then they probably apply across the board.) JonArticle: 111672
% function [h,c_upd]=3DDCD_upd_max(R,N,M,H,Nit,beta,N_upd_max);
function [h,M_val,c_it,c_upd]=3DDCD_upd_max(R,N,M,H,Nit,beta,N_upd_max);
% Solving normal equations: R*h=3Dbeta
% =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
% R - N x N system matrix (real-valued);
% beta - N x 1 right-side vector;
% h - N x 1 solution vector;
% N - system size;
% M - number of bits used for representation of the solution;
% Nit - a threshold for number of iterations;
% =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
h=3Dzeros(N,1); % solution vector initialisation;
delta=3Dzeros(1,2); % plus-minus step-size parameters;
c_it=3Dzeros(1,M); % number of iterations (passes) for each bit;
c_upd=3Dzeros(1,M); % number of updates for each bit;
M_val=3DM; % real number of bits;
for m=3D1:M
d=3DH*2^(-m); % step-size parameter;
delta(1)=3Dd; delta(2)=3D-d;
for it=3D1:Nit
Flag=3D0; % indicator of successful updates;
for p=3D1:N % pass through all elements of h;
[val ad]=3Dmin([-beta(p),beta(p),-abs(R(p,p)*d/2)]);
if ad<3 % ad<3 means a successful update;
h(p)=3Dh(p)+delta(ad); % h-update;
if abs(h(p))>H
h(p)=3Dh(p)-delta(ad);
else
Flag=3D1;
c_upd(m)=3Dc_upd(m)+1; % calculation of successful
updates;
beta=3Dbeta-delta(ad)*R(p,:); % beta-update
end
end
if sum(c_upd)>N_upd_max break; end
end
if Flag=3D=3D0 c_it(m)=3Dit; break; end
if sum(c_upd)>N_upd_max c_it(m)=3Dit; break; end
end % it
if it=3D=3DNit M_val=3Dm-1; break; end
if sum(c_upd)>N_upd_max M_val=3Dm-1; c_it(m)=3Dit; break;
end
end % m
return
***************************************************************************=
=AD********
I am tried to implement the algorithm above into FPGA. My question is
if the H value effects the result in FPGA. Coz I think when the float
point changes to fixed-point, the Matrix R and Vector b will change.
And I also need change the H. But my tutor said it is for matlab, but
for FPGA, the H does not matter to the result. The important parameter
is m. Is it true? I don't have much experience on it. Any one can help
me figure it out? Thank you very much.
Article: 111673If, on the other hand, you have a picoBlaze or MicroBlaze for which you want to update the memory, the Spartan3E Starter Kit has that ready to go. Source code is available. "Matthew Hicks" <mdhicks2@uiuc.edu> wrote in message news:eiqq83$819$1@news.ks.uiuc.edu... > If you are talking about the EEPROM or any other non-volatile on-board > memory, it should be detected by Impact. Just create an PROM file (.mcs) > from the .bit file and load it into the memory. All of this can be done > inside impact and should be detailed in the user manual for your board. > > > ---Matthew Hicks > > > "Jialin" <jiaojialin@gmail.com> wrote in message > news:1162913626.614634.231140@m73g2000cwd.googlegroups.com... >> Hi my friends, >> >> We know little about Spartan and Xilinx. We are connecting our >> Spartan 3 starter kit board to a PC and using Xilinx ISE 8.1 to control >> it. >> >> We want to find a way to load our program ( instructions) into the >> memory of >> the Spartan board. Could you tell me how? We will appreciate it if you >> could kindly show some light on this. >> > >Article: 111674
>A simulation testbench written in vhdl > or verilog is portable across vendors. > A waveform based simulation is not. > > -- Mike Treseler Could you explain the difference between extension vht and vhd? Does It means that I can't use testbench exporetd from waveform to vht in Quartus. ModelSim doesn't see this file. I changed name from tbench.vht to tbench.vhd but it doesn't work. I have few waveform files and I want to try export them to another format. I could do that in Waveformer Pro (Synapticad) but it is only eval version in which I can't even save.
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