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Hey, everyone, Hope you are doing great! I just started learning about digital phase locked loop. I have a lot of things that I cannot figure out. It will be great if I can get some answers from here. In the textbook, The gain of the voltage controlled oscillator is Kvco = 2 x Pi x (fmax - fmin) / (Vmax - Vmin) The VCO output frequency, f clock, is related to the VCO input voltage by W clock = 2 x Pi x fclock = Kvco x Vinvco + W0 Where W0 is a constant. However, the variable we are feeding back is not frequency but phase ( hence the name of the circuit). The phase of the VCO clock output is related to fclock by The integration of Wclock = Kvco x Vinvco / jw Here, I do not understand that why the integration of the Wclock is equal to Kvco x Vinvco / jw. If I do Laplace transform on the integration of the Wclock, then I will get 1/ jw x Laplace transform of Kvco x Vinvco. And since these two are constant, the laplace transform will be Kvco x Vinvco / s. Hence the Laplace transform of the integration of Wclock will be Kvco x Vinvco / square of s. Here in the book, I do not think they are talking about taking a Laplace transform. And even they are taking Laplace transform, my answer will be Kvco x Vinvco / square of s. Not Kvco x Vinvco /s. Do you have any idea here, please? 2. I can understand the equation about the natual frequency and damping factor. The book also just gives me the equations about pull in range, lock time, lock range. However, there is no deduction for these equations at all. Specifically, the pull in range is Pi/2 x square root of ( 2 x damping ratio x natual frequency x Kvco x Kpd - the square of natural frequency ) Here Kpd is the gain of phase detector. The lock time is 2 x Pi / natual frequency. The lock range is Pi / 2 x (1/ R x C ) , here R and C is the resistor and capacitor value of the low pass filter. I have no idear how these equations are deducted. Thanks for reading this post and any answers are greatly appreciated. Sarah

<tryyourbestok@hotmail.com> wrote in message news:1168201717.777864.70690@38g2000cwa.googlegroups.com... > Hey, everyone, > > Hope you are doing great! > > I just started learning about digital phase locked loop. I have a lot > of things that I cannot figure out. It will be great if I can get some > answers from here. > > In the textbook, > > The gain of the voltage controlled oscillator is > > Kvco = 2 x Pi x (fmax - fmin) / (Vmax - Vmin) > > The VCO output frequency, f clock, is related to the VCO input voltage > by > > W clock = 2 x Pi x fclock = Kvco x Vinvco + W0 > > Where W0 is a constant. However, the variable we are feeding back is > not frequency but phase ( hence the name of the circuit). The phase of > the VCO clock output is related to fclock by > > > The integration of Wclock = Kvco x Vinvco / jw > > Here, I do not understand that why the integration of the Wclock is > equal to Kvco x Vinvco / jw. See http://www.holmea.demon.co.uk/Ethernet/PLLQA.htm

tryyourbestok@hotmail.com wrote: > Hey, everyone, > > Hope you are doing great! > > I just started learning about digital phase locked loop. I have a lot > of things that I cannot figure out. It will be great if I can get some > answers from here. > > In the textbook, > > The gain of the voltage controlled oscillator is > > Kvco = 2 x Pi x (fmax - fmin) / (Vmax - Vmin) > > The VCO output frequency, f clock, is related to the VCO input voltage > by > > W clock = 2 x Pi x fclock = Kvco x Vinvco + W0 > > Where W0 is a constant. However, the variable we are feeding back is > not frequency but phase ( hence the name of the circuit). The phase of > the VCO clock output is related to fclock by > > > The integration of Wclock = Kvco x Vinvco / jw > > Here, I do not understand that why the integration of the Wclock is > equal to Kvco x Vinvco / jw. > > If I do Laplace transform on the integration of the Wclock, then I > will get 1/ jw x Laplace transform of Kvco x Vinvco. And since these > two are constant, the laplace transform will be Kvco x Vinvco / s. > Hence the Laplace transform of the integration of Wclock will be Kvco x > Vinvco / square of s. Here in the book, I do not think they are talking > about taking a Laplace transform. And even they are taking Laplace > transform, my answer will be Kvco x Vinvco / square of s. Not Kvco x > Vinvco /s. > > Do you have any idea here, please? > > 2. I can understand the equation about the natual frequency and damping > factor. The book also > just gives me the equations about pull in range, lock time, lock range. > However, there is no deduction for these equations at all. > > Specifically, the pull in range is > > Pi/2 x square root of ( 2 x damping ratio x natual frequency x Kvco x > Kpd - the square of natural frequency ) > > Here Kpd is the gain of phase detector. > > The lock time is 2 x Pi / natual frequency. > > The lock range is Pi / 2 x (1/ R x C ) , here R and C is the resistor > and capacitor value of the low pass filter. > > I have no idear how these equations are deducted. > > Thanks for reading this post and any answers are greatly appreciated. > Sarah > The key secret is that frequency (when definible) is the rate of change of phase. -- Many thanks, Don Lancaster voice phone: (928)428-4073 Synergetics 3860 West First Street Box 809 Thatcher, AZ 85552 rss: http://www.tinaja.com/whtnu.xml email: don@tinaja.com Please visit my GURU's LAIR web site at http://www.tinaja.com

Have a look at our Broaddown4 board. It will do up to a LX160. Ethernet Phys would be by module that we do. Photos of that module are off our Raggedstone1 product page. John Adair Enterpoint Ltd. Frank wrote: > I've been looking all over for a board with a Xilinx V4 LX160 or 200 > FPGA > and 2 10/100 Ethernet PHYs. Closest I got was a board from Avnet that > only had 1 PHY. > > Know where to find one? Please let me know. > > Many thanks.

<tryyourbestok@hotmail.com> wrote in message news:1168201717.777864.70690@38g2000cwa.googlegroups.com... > Hey, everyone, > > Hope you are doing great! > > I have no idea how these equations are deducted. > > Thanks for reading this post and any answers are greatly appreciated. > Sarah > Hello Sarah from the University of Cincinnati..... I'm shit myself but that seems normal. You might need to ignore the mathematical analysis and wave your hands and brane about. I'm not certain about this but there is a good chance that the VCO only sort of behaves as an integrator within the loop when it is combined with the phase detector...... and the loop is stable. I think you might find the 'botched' small signal maths takes a 'short cut' and stuffs the integration in the VCO term and gives you an answer that works...... for a small signal analysis. Outside of that the overall 'loop', which has the filter in it, gives you stuff like the range (lock, pull in... large signal.... Squegging) things. It's a bit incestuous. Start out by having a think about how the 'average' output of your phase detector varies according to the difference between your reference frequency and your VCO frequency without feedback. The phase detector is really some sort of mixer. Long term, without the loop closed it's going to be all over the place. With the loop closed it might just get to the right answer..... Yes, I have been bullshitting. DNA

On Sun, 07 Jan 2007 22:55:49 GMT, "Genome" <mrspamizgood@yahoo.co.uk> wrote: > ><tryyourbestok@hotmail.com> wrote in message >news:1168201717.777864.70690@38g2000cwa.googlegroups.com... >> Hey, everyone, >> >> Hope you are doing great! >> >> I have no idea how these equations are deducted. >> >> Thanks for reading this post and any answers are greatly appreciated. >> Sarah >> > >Hello Sarah from the University of Cincinnati..... > >I'm shit myself but that seems normal. > >You might need to ignore the mathematical analysis and wave your hands and >brane about. I'm not certain about this but there is a good chance that the >VCO only sort of behaves as an integrator within the loop when it is >combined with the phase detector...... and the loop is stable. > >I think you might find the 'botched' small signal maths takes a 'short cut' >and stuffs the integration in the VCO term and gives you an answer that >works...... for a small signal analysis. > >Outside of that the overall 'loop', which has the filter in it, gives you >stuff like the range (lock, pull in... large signal.... Squegging) things. >It's a bit incestuous. > >Start out by having a think about how the 'average' output of your phase >detector varies according to the difference between your reference frequency >and your VCO frequency without feedback. The phase detector is really some >sort of mixer. > >Long term, without the loop closed it's going to be all over the place. With >the loop closed it might just get to the right answer..... > >Yes, I have been bullshitting. > >DNA > DNA's comments written out in "maths".... http://analog-innovations.com/SED/PhaseLockedLoopAnalysis.pdf If I hadn't gained a scholarship to MIT, the University of Cincinnati was one of my fall-back plans, particularly since it was only 150 miles away from home (Huntington, WV). ...Jim Thompson -- | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona Voice:(480)460-2350 | | | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | | http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.

For those asking first photo of DIL FPGA modules Craignell1/2/3 are now on our website. Modules have a very tiny packaged Spartan-3E and we have made them 5V tolerant and capable of reaching 5V CMOS levels with pullup resistors. John Adair Enterpoint Ltd.

Hi! Until now I have only worked with FPGA development boards (Altera, Xilinx). I do this only for educational purposes, not for a real project. That's why I don't need all the faetures of a recent development board like the Spartan 3e starter kit and alike. So I wondered if it is possible to just use a chaep FPGA chip like this one: http://tinyurl.com/y33nh5 and just solder some led's + buttons to the IO-pins. It is a xilinx chip, so I could use the free Webpack ISE for generating the bitstream I guess. But the problem is: How do I actually configure the FPGA? I have read a Xilinx datasheets (http://tinyurl.com/ykxojk) and got the impression that the actual configuration process isn't that difficult in slave searial mode. The problem is that I don't know much about electronics. So I wondered if I could build such a FPGA-paralell-port-programmer by myself? Are there any hidden traps? (The software side is no problem, writing and reading bits to/from parport is easy.) I know that this might sound like a dumb/unspecific question, but I didn't know where to ask. It would be cool if someone could just tell me something like "Yes, it is that easy, just do it." or "It is difficult because you need a lot of debugging eqipment etc,.". Regards, Timo

SunLei wrote: > The FFT result output, implemented in a FPGA, is a complex number with > 16-bit real part and 16-bit imaginary part. In the application, I only care > about the FFT result magnitude, Mag = sqrt(Re*Re+Im*Im).So I wonder if there > is an approximate estimation about this operation. and even more, the > decibel algorithm. I think the decibel algorithm can be easily implemented > by a looking-up-table scheme, but I still have no idea about simple complex > magnitude algorithm. I appreciate your suggestions. > > Sun Lei. > > > > If you are only interested in the result expressed in dB, then you don't need the square root: dB = 20*log(mag) = 20*log(sqrt(I^2+Q^2)) = 10*log(I^2+Q^2) If about 1/4 dB is sufficient precision, then you can use the quick and dirty log I posted to dsp-guru many years ago. To do that, left shift the sum I^2+Q^2 until you eliminate the leading zero bits, counting the bit positions shifted. Each bit shift corresponds to 6dB (3dB after taking into account the square root). Then ignore the MSB (that will always be '1' after shifting), and feed the next 4 most significant bits into a 4 input look-up table containing 10*logs of 1.0 to 1-15/16 in 1/16 increments. The output of that table gets added to the shift log to get your total value.

yttrium wrote: > i have to admit at first i was not really convinced but by writing more > and more DSP related VHDL where i need signed/unsigned values i am > learning a lot of the inefficiency of certain libraries and packages ... > By the same token, if you do a lot of DSP, you'll soon learn to appreciate the strong typing in VHDL as compared to verilog, and may even grow to despise the permissiveness (and ambiguity) of verilog. FWIW, I code my VHDL components with std_logic and std_logic_vector on the I/O in order to be consistent with existing libraries. I convert the signals to signed/unsigned inside the architecture as needed. Some of my components have a boolean generic, "is_signed" to specify the behavior as an option.

Hi all, In normal design we'd like to pipeline large comb logic to pipelined design. But I heard there is Multi-cycle Path and need more complex control logic. I have some questions according to it. 1. Is most design style don't recommend Multi-cycle Path? 2. Can I change all Multi-cycle Path to Pipelined Path? 3. Can I change all Pipelined Path to Multi-cycle Path? 4. In what circumstance shall we need Multi-cycle Path? Any recommending reading material is welcome! Best regards, Davy

Mounard Le Fougueux wrote: > I have a mature design on a spartan2300E. It has some unused pin - by > that I mean there are no references to thoses pins in either the UCF or > port map of the VHDL code - nor has there ever been. > > Here's the problem: > > Last rev of the fw, the unused pins acted as I expected - high > impedence. There fore there way never any contention with other devices > conneected to that unused pin on a backplane. If you connect an 'unused' pin to a backplane (always driven by other devices) then the safest thing to do, is declare that pin as an input - even if it means some dummy code to keep the tool flows happy. Some Sw has default 'unused to GND' / Unused to Pinkeep / Unused to Pullups' options, but certainly the tools _SHOULD_ correctly report what they finally did. I'd be miffed if a tool chain committed an unsed pin, without explaining that it had done so. -jg

John Adair wrote: > For those asking first photo of DIL FPGA modules Craignell1/2/3 are now > on our website. Modules have a very tiny packaged Spartan-3E and we > have made them 5V tolerant and capable of reaching 5V CMOS levels with > pullup resistors. > > John Adair > Enterpoint Ltd. No Link ? ( some of us are lazy..) -jg

Hi Davy, Read answers below... Davy wrote: > Hi all, > > In normal design we'd like to pipeline large comb logic to pipelined > design. But I heard there is Multi-cycle Path and need more complex > control logic. > > I have some questions according to it. > 1. Is most design style don't recommend Multi-cycle Path? In general it isn't recommended to use multi-cycle path. You end up having to manually tell the timing check part of the tools the explicit places that you are planning to violate typical synchronous design style. > 2. Can I change all Multi-cycle Path to Pipelined Path? No, most of paths but not all. > 3. Can I change all Pipelined Path to Multi-cycle Path? Yes, but why? > 4. In what circumstance shall we need Multi-cycle Path? When you have a indivisible chunk of logic, such as a hard macro that can't be pipelined further. > > Any recommending reading material is welcome! Not off hand. The moral of this story is pipeline when you can, multi-cycle when you must. > > Best regards, > Davy

Davy wrote: > I have some questions according to it. > 1. Is most design style don't recommend Multi-cycle Path? I don't design using multi-cycle paths, nor have I (so far) had to include one in a design. > 2. Can I change all Multi-cycle Path to Pipelined Path? I prefer to design single-cycle logic in the first place. I'd rather create a synchronous clock enable than keep track of a path constraint for the life of the design. > 3. Can I change all Pipelined Path to Multi-cycle Path? > 4. In what circumstance shall we need Multi-cycle Path? Multi-cycle is an odd timing spec that I happen to know. It's not something I need, it's a less than perfect (but adequate) circuit that I can either fix or tolerate by using a constraint. -- Mike Treseler

Instantiate your ILA inside the submodule you want to instrument, there is no reason why these have to be at the top level, you can have up to 15 ILA per chip. You'll have to string the control port down through the hierarchy to the ILA but at least its only one port. Alternatively, bus all the signals you want to watch into a single instrumentation bus and bring that back up through the hierarchy to your ILA instantiated atthe top level. CMOS wrote: > hi, > how do we connect internals signals(not ports) of submodules in the > top level design to trigger ports of the ila core? With core inserter, > it is possible to connect signals from many submodules to the same > trigger port, but how is this done when you use core generater and > manually setup connections of icon and ila cores? > > thank you.

Thank you. yes , iam with your algorithm. "Ray Andraka" <ray@andraka.com> ??????:hwgoh.23481$Dy2.116@newsfe20.lga... > SunLei wrote: >> The FFT result output, implemented in a FPGA, is a complex number with >> 16-bit real part and 16-bit imaginary part. In the application, I only >> care >> about the FFT result magnitude, Mag = sqrt(Re*Re+Im*Im).So I wonder if >> there >> is an approximate estimation about this operation. and even more, the >> decibel algorithm. I think the decibel algorithm can be easily >> implemented >> by a looking-up-table scheme, but I still have no idea about simple >> complex >> magnitude algorithm. I appreciate your suggestions. >> >> Sun Lei. >> >> >> >> > > If you are only interested in the result expressed in dB, then you don't > need the square root: > > dB = 20*log(mag) = 20*log(sqrt(I^2+Q^2)) = 10*log(I^2+Q^2) > > If about 1/4 dB is sufficient precision, then you can use the quick and > dirty log I posted to dsp-guru many years ago. To do that, left shift > the sum I^2+Q^2 until you eliminate the leading zero bits, counting the > bit positions shifted. Each bit shift corresponds to 6dB (3dB after > taking into account the square root). Then ignore the MSB (that will > always be '1' after shifting), and feed the next 4 most significant bits > into a 4 input look-up table containing 10*logs of 1.0 to 1-15/16 in 1/16 > increments. The output of that table gets added to the shift log to get > your total value.

If you're just using the magnitude to compare to some constant threshold or something like that, then you can just square the number you are comparing to and avoid the sqrt in logic. SunLei wrote: > The FFT result output, implemented in a FPGA, is a complex number with > 16-bit real part and 16-bit imaginary part. In the application, I only care > about the FFT result magnitude, Mag = sqrt(Re*Re+Im*Im).So I wonder if there > is an approximate estimation about this operation. and even more, the > decibel algorithm. I think the decibel algorithm can be easily implemented > by a looking-up-table scheme, but I still have no idea about simple complex > magnitude algorithm. I appreciate your suggestions. > > Sun Lei.

It sounds like that pin isn't actually a no-connect, but is used since you are expecting a particular behavoiour. As one poster mentioned (and increased my knowledge) the tools will do whatever they want with a pin that it figures are unconnected. If you have a specific behaviour you need, you need to tell it so. Sounds like you lucked out in a manner of sorts that it drove the pin to the same logic state of the other driver on that net in previous builds. Mounard Le Fougueux wrote: > I have a mature design on a spartan2300E. It has some unused pin - by > that I mean there are no references to thoses pins in either the UCF or > port map of the VHDL code - nor has there ever been. > > Here's the problem: > > Last rev of the fw, the unused pins acted as I expected - high > impedence. There fore there way never any contention with other devices > conneected to that unused pin on a backplane. > > So far so good. > > I then need to make a small change to the VHDL code that had NO IMPACT > on either the ports or the UCF. The PAR report has the pin as "UNUSED". > I had to do an overnight MPPR (Mutipass place and route) to meet timing > constraints (as I normally had to on all previous revs). > > However with this new rev, the FPGA is clearly driving the pin to 3.3V > through a low imppendance, and in fact is contending with anotehr device > which is driving the same line to 0V resulting in a net ~1V contended > signal result. This happen on every board that i've tried this new rev > on - therefore it is not a board issue but a FPGA configuration issue. > > Shouldn't an unused FPGA pin default to some high impedence state? My > solution to the problem is to explicitely USE the pins as inputs. > > However what would be the explaination for an unused input looking like > a driven 3.3V output????? > > Thanks

Use your APB clock as the clock for your slower circuit, it will use slightly more power but your static timing problems will handled by the tools. Next, use a "data ready" status bit in your slave so that the master knows when its should expect to be able to read valid data. APB wasn't meant to hold for slaves, the ARM has to deal with this by using some kind of data ready signal. If the software guy gives your a hard time offer to write the I/O routine for him. marco wrote: > Hello. > > I have a peripheral with an AMBA APB interface. > The issue that I am facing is that of clock domain crossing. > The processing logic in the peripheral is required to operate at a > relatively slow clock frequency, but the clock frequency of the APB > interface can be 4 to 5 times that of the slow clock domain. > I have been considering the two clock domains as asynchronous with > respect to each other, even though the faster clock is generated from > the slow clock by means of a PLL; therefore, the phase relationship > between the two clock should be constant. > > My problems lies in the fact that APB has no signal to hold the bus in > the case where the data from a write cycle to the slow clock domain has > not yet been registered by the slow clock when a second write cycle > starts to happen. > > I am considering to options: > 1) Have the Configuration Registers clocked with the fast clock signal > and only have event signals generated by a write or a read cross the > clock domain boundary. > > 2) Buffer data with a FIFO and synchronize the control signals to the > slow clock domain. > > Any suggestions would be appreciated. > Thank you in advance. > Best Regards, > Marco.

tryyourbestok@hotmail.com wrote: > Hey, everyone, > > Hope you are doing great! > > I just started learning about digital phase locked loop. I have a lot > of things that I cannot figure out. It will be great if I can get some > answers from here. > > In the textbook, What textbook? > > The gain of the voltage controlled oscillator is > > Kvco = 2 x Pi x (fmax - fmin) / (Vmax - Vmin) > That looks right, although it's not very 'digital'. > The VCO output frequency, f clock, is related to the VCO input voltage > by > > W clock = 2 x Pi x fclock = Kvco x Vinvco + W0 > > Where W0 is a constant. Good so far. > However, the variable we are feeding back is > not frequency but phase ( hence the name of the circuit). The phase of > the VCO clock output is related to fclock by > > > The integration of Wclock = Kvco x Vinvco / jw > > Here, I do not understand that why the integration of the Wclock is > equal to Kvco x Vinvco / jw. It isn't. See below. > > If I do Laplace transform on the integration of the Wclock, then I > will get 1/ jw x Laplace transform of Kvco x Vinvco. And since these > two are constant, the laplace transform will be Kvco x Vinvco / s. > Hence the Laplace transform of the integration of Wclock will be Kvco x > Vinvco / square of s. Here in the book, I do not think they are talking > about taking a Laplace transform. And even they are taking Laplace > transform, my answer will be Kvco x Vinvco / square of s. Not Kvco x > Vinvco /s. > > Do you have any idea here, please? I have an idea that you needed to pay more attention in your signals class, and that you're confusing signals with systems. Vinvco is a signal which is being acted on by an integrator. You don't _know_ Vinvco's Laplace transform up front, you only know that a time-domain integrator acts to to multiply that Laplace transform by 1/s in the frequency domain. > > 2. I can understand the equation about the natual frequency and damping > factor. The book also > just gives me the equations about pull in range, lock time, lock range. > However, there is no deduction for these equations at all. > > Specifically, the pull in range is > > Pi/2 x square root of ( 2 x damping ratio x natual frequency x Kvco x > Kpd - the square of natural frequency ) > > Here Kpd is the gain of phase detector. > > The lock time is 2 x Pi / natual frequency. > > The lock range is Pi / 2 x (1/ R x C ) , here R and C is the resistor > and capacitor value of the low pass filter. > > I have no idear how these equations are deducted. > > Thanks for reading this post and any answers are greatly appreciated. > Sarah > "Phase Locked Loop Circuit Design" by Wolaver gives a very good discussion of the lock-in process, including approximate equations for a number of phase detectors (and yes, lock in is _heavily_ influenced by the phase detector). By the way: where does the 'digital' come in? All I see is traditional PLL circuits stuff here. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Posting from Google? See http://cfaj.freeshell.org/google/ "Applied Control Theory for Embedded Systems" came out in April. See details at http://www.wescottdesign.com/actfes/actfes.html

On Sun, 7 Jan 2007 20:00:54 +0800, "SunLei" <iamsunlei@gmail.com> wrote: >The FFT result output, implemented in a FPGA, is a complex number with >16-bit real part and 16-bit imaginary part. In the application, I only care >about the FFT result magnitude, Mag = sqrt(Re*Re+Im*Im).So I wonder if there >is an approximate estimation about this operation. and even more, the >decibel algorithm. I think the decibel algorithm can be easily implemented >by a looking-up-table scheme, but I still have no idea about simple complex >magnitude algorithm. I appreciate your suggestions. > >Sun Lei. I don't know what precision you need, so the following may be totally unsuitable. But it's worth mentioning, if only as a history lesson. Back in the 70's, when life was cheap and digital hardware was expensive, I was designing parts of radar signal processors. Most of these things had an FFT in the front end, and at some point we had to produce a magnitude from I and Q. In those days a 12-by-16 multiplier took an entire circuit board of AMD 25S05 2-by-4 multipliers, which seemed kind of excessive for such a function. We got pretty good results by comparing the magnitudes of I and Q, then adding the larger plus half the smaller. The average result error is around 8.6 percent. There are variations on this theme that use different coefficients, i.e. alpha*|larger| + beta*|smaller|, and produce much lower average and peak errors. You can read more about this at: http://dspguru.com/comp.dsp/tricks/alg/mag_est.htm If you're using one of those new-fangled FPGAs with a zillion multipliers on it, this isn't the solution for you. Still, it's interesting how much performance designers used to squeeze out of not all that much logic. And coffee was only a quarter. And the music was better. I could go on. Bob Perlman Cambrian Design Works http://www.cambriandesign.com

Hi, in C programming,it's easy to get a negative value of any variables, as minus -xn; in FPGA, suppose it's 16bit 2's complement number format, how to compute a negative value of a given number 'xn'? I mean, there must be a solution to get the result easily, not "reverse every 16-bits first,and add 1" to get the result. I am confused about this, there must be something wrong with my understandings. Sun lei.

On Mon, 8 Jan 2007 14:54:23 +0800, "SunLei" <iamsunlei@gmail.com> wrote: >Hi, > > in C programming,it's easy to get a negative value of any variables, as >minus -xn; in FPGA, suppose it's 16bit 2's complement number format, how to >compute a negative value of a given number 'xn'? I mean, there must be a >solution to get the result easily, not "reverse every 16-bits first,and add >1" to get the result. > I am confused about this, there must be something wrong with my >understandings. > >Sun lei. Well, that's what you have to do if you want to form the 2's complement of a number. Depending on the application, you may be able to get away with less. For example, if you're computing A minus B, you invert the bits in B, put A and B into an adder, and inject a 1 into the adder carry-in to get the increment--no need for an extra adder. Or you could always write c = a - b and let Verilog do the work. There's more on binary arithmetic here: http://www.cambriandesign.com/2006/07/twos-complement-arithmetic.html Bob Perlman Cambrian Design Works http://www.cambriandesign.com

Well, I have a similar situation. I have only worked with development platform from Xilinx, like Spartan 3E Starter kit, and now I have to work with a Xilinx FPGA which is integrated in a Sundance Board. Of course the fpga is the same but could I program it with ISE and XPS?. I think that you can use this tools for creating the bitstream, but you can not use any Xilinx tool to download this configuration. You must use another tool from the company or integrate this with some program. But in your case, I think that you need quite a lot electronic knowledge to develop your own board. You need some interface to program the fpga, some vco to create a reference clock, some voltage regulator, etc... My opinion is that what you try to do is a good project but I think that you are re-inventing the wheel. I hope this could help you Best Regards Pablo

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