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Messages from 125850

Article: 125850
Subject: Re: not totally repulsive
From: a7yvm109gf5d1@netzero.com
Date: Tue, 06 Nov 2007 13:45:28 -0800
Links: << >>  << T >>  << A >>
On Nov 6, 12:59 pm, Andy <jonesa...@comcast.net> wrote:
>
> Prior to that, how many existing boards do you need to use up, and how
> many customers can you afford to loose when they do not work

About as many as he can afford to tighten, I suppose.


Article: 125851
Subject: Re: not totally repulsive
From: Rich Grise <rich@example.net>
Date: Tue, 06 Nov 2007 23:11:11 GMT
Links: << >>  << T >>  << A >>
On Tue, 06 Nov 2007 13:01:51 -0800, BobW wrote:
...
> turbofans. I'll take the extra supplies as the lesser-of-two evils.

If Satan and Lucifer showed up at the inn, and the proprietor rented
them each a room, would he be the lessor of two evils? ;-)

Cheers!
Rich


Article: 125852
Subject: Re: not totally repulsive
From: "Symon" <symon_brewer@hotmail.com>
Date: Tue, 6 Nov 2007 15:22:15 -0800
Links: << >>  << T >>  << A >>
"Rich Grise" <rich@example.net> wrote in message 
news:jw6Yi.4461$3j7.554@trnddc02...
> On Tue, 06 Nov 2007 13:01:51 -0800, BobW wrote:
> ...
>> turbofans. I'll take the extra supplies as the lesser-of-two evils.
>
> If Satan and Lucifer showed up at the inn, and the proprietor rented
> them each a room, would he be the lessor of two evils? ;-)
>
> Cheers!
> Rich
>
Rich, maybe he'd be the landlord of the flies?

I'll get my coat...

http://en.wikipedia.org/wiki/Beelzebub#Religious_meaning 



Article: 125853
Subject: Re: not totally repulsive
From: John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com>
Date: Tue, 06 Nov 2007 16:29:12 -0800
Links: << >>  << T >>  << A >>
On Tue, 06 Nov 2007 23:11:11 GMT, Rich Grise <rich@example.net> wrote:

>On Tue, 06 Nov 2007 13:01:51 -0800, BobW wrote:
>...
>> turbofans. I'll take the extra supplies as the lesser-of-two evils.
>
>If Satan and Lucifer showed up at the inn, and the proprietor rented
>them each a room, would he be the lessor of two evils? ;-)
>
>Cheers!
>Rich


Or, as Captain Jack Aubrey said, the proper British sailor always
chooses the lesser of two weevils.

John


Article: 125854
Subject: Re: not totally repulsive
From: John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com>
Date: Tue, 06 Nov 2007 17:24:50 -0800
Links: << >>  << T >>  << A >>
On Tue, 06 Nov 2007 13:45:28 -0800, a7yvm109gf5d1@netzero.com wrote:

>On Nov 6, 12:59 pm, Andy <jonesa...@comcast.net> wrote:
>>
>> Prior to that, how many existing boards do you need to use up, and how
>> many customers can you afford to loose when they do not work
>
>About as many as he can afford to tighten, I suppose.

The chances of this not working are nil; I'd be more worried about
meteor damage in shipping. But in fact my customers are great: when we
do have a problem, we tell them the truth, we work with them to fix
it, we ship them replacement products, whatever it takes. They know
that complicated things sometimes go wrong. What they appreciate is an
honest, energetic fix.

John


Article: 125855
Subject: Time Delay in FPGA
From: raullim7@hotmail.com
Date: Tue, 06 Nov 2007 21:46:02 -0800
Links: << >>  << T >>  << A >>
hi, i have two processes in my vhdl code for my FPGA. the two
processes each will generate a signal with the second one lagging
around 5ns. problem is, i am told that this 5ns delay might not be
from my coding but from the FPGA processing delay.. may i know how do
i check for this processing delay? thanks


Article: 125856
Subject: Re: Static PLL
From: rouzbeh.h@actel.com
Date: Tue, 06 Nov 2007 23:48:55 -0800
Links: << >>  << T >>  << A >>
On 5 Nov, 22:00, Vince <claesvinc...@gmail.com> wrote:
> On 5 nov, 16:13, rouzbe...@actel.com wrote:
>
>
>
> > Hi Vince,
>
> > There is an example for the ProASIC3 board onActelwebpage with
> > complete design files and documentation.
> > But this design does not use the PLL.http://www.actel.com/products/hardware/devkits_boards/proasic3_starte...
>
> > Check that the POWERDOWN input signal for the PLL is connected
> > correctly.
> > By default this input is Active low and should therefore be connected
> > to '1'.
> > When generating the PLL macro you can see/change this configuration.
>
> > If this is not the problem let me know and I can send you an example.
>
> > BR
> > Rouzbeh
>
> Hi Rouzbeh,
>
> I just have problems with the PLL macro, I have developed some
> examples on this board already using CoreABC, UART, VHDL Project etc.
> so I know how to work with the board. But always when I use the STATIC
> PLL Macro it gives me problems... I can't get it running correctly.
> Can you send me an example (where I get a 10MHz and 40MHz clock out of
> the static pll macro? (I can't find a static pll example on theACTEL
> website)
>
> Thanks for your help, kind regards.
>
> Vince

Hi Vince,

Please also make sure that you have connected VCC/GND to the PLL/s.

"Instructions for PLL Activation on ProASIC3 Starter Kit Board
In order to use the PLLs on the ProASIC3 starter kit board, power must
be applied to their
respective analog supply rails. For the west side PLL, known as PLF,
the VCCPLF line must be
connected to VCC, which is held at 1.5 V. The same is true for VCCPLC
of the PLL on the east side,
known as PLC. In addition, the VCOMPLF and VCOMPLC lines must be
connected to ground. We
do not connect these voltages by default on the board for three
reasons:
1. The PLC analog voltage rails are not available on A3P devices, only
on A3PE in the PQ208
package. Only the west side PLL, namely PLF, is available on A3P
devices in PQ208. In A3P
devices, the pins are used as general I/Os. The same board is used for
A3PE and A3P devices.
2. We want to demonstrate the lowest possible power consumption for
the part. Perpetually
powering the PLL lines would not achieve that.
3. It is easy to connect the appropriate pins together when desired.
That is why we make the pins
available on the headers.
A variety of valid connections are possible. Two examples are as
follows:
1. For PLF, connect pin 27 (VCCPLF) to pin 36 (VCC), and pin 25
(VCOMPLF) to pin 17 (GND).
2. For PLC, (A3PE only) connect pin 131 (VCCPLC) to pin 142 (VCC), and
pin 133 (VCOMPLC)
to pin 141 (GND).
To facilitate end users, we will be supplying jumper wires with
selected production versions of the kit
to allow end users to quickly connect and disconnect these voltage
supply rails. If a user has lost the
jumper wires or has a production kit without jumper wires, it is a
simple matter of soldering short
insulated connecting wire to the appropriate header pins on the J14A
and J14C headers."

Thanks
Rouzbeh


Article: 125857
Subject: FPGA Clock signal
From: raullim7@hotmail.com
Date: Wed, 07 Nov 2007 00:32:56 -0800
Links: << >>  << T >>  << A >>
i would like to ask how can i capture the FPGA master clock signal in
the oscilloscope? Bcos in the data sheet, it indicates that the master
clock is located at pin N9 which is not accessible externally. please
help. thanks a million


Article: 125858
Subject: Re: not totally repulsive
From: John Devereux <jdREMOVE@THISdevereux.me.uk>
Date: Wed, 07 Nov 2007 09:34:28 +0000
Links: << >>  << T >>  << A >>
John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com> writes:

> On Tue, 06 Nov 2007 13:45:28 -0800, a7yvm109gf5d1@netzero.com wrote:
>
>>On Nov 6, 12:59 pm, Andy <jonesa...@comcast.net> wrote:
>>>
>>> Prior to that, how many existing boards do you need to use up, and how
>>> many customers can you afford to loose when they do not work
>>
>>About as many as he can afford to tighten, I suppose.
>
> The chances of this not working are nil; I'd be more worried about
> meteor damage in shipping.

In fact I would think it is more likely that the "proper" LDO solution
will e.g. start oscillating, for some reason.

-- 

John Devereux

Article: 125859
Subject: Re: not totally repulsive
From: Spehro Pefhany <speffSNIP@interlogDOTyou.knowwhat>
Date: Wed, 07 Nov 2007 05:25:37 -0500
Links: << >>  << T >>  << A >>
On Wed, 07 Nov 2007 09:34:28 +0000, the renowned John Devereux
<jdREMOVE@THISdevereux.me.uk> wrote:

>John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com> writes:
>
>> On Tue, 06 Nov 2007 13:45:28 -0800, a7yvm109gf5d1@netzero.com wrote:
>>
>>>On Nov 6, 12:59 pm, Andy <jonesa...@comcast.net> wrote:
>>>>
>>>> Prior to that, how many existing boards do you need to use up, and how
>>>> many customers can you afford to loose when they do not work
>>>
>>>About as many as he can afford to tighten, I suppose.
>>
>> The chances of this not working are nil; I'd be more worried about
>> meteor damage in shipping.
>
>In fact I would think it is more likely that the "proper" LDO solution
>will e.g. start oscillating, for some reason.

For example, if it prefers black capacitors over orange ones. 


Best regards, 
Spehro Pefhany
-- 
"it's the network..."                          "The Journey is the reward"
speff@interlog.com             Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog  Info for designers:  http://www.speff.com

Article: 125860
Subject: Re: Time Delay in FPGA
From: roger <roger.jons@gmail.com>
Date: Wed, 07 Nov 2007 11:18:32 -0000
Links: << >>  << T >>  << A >>
Hi,

Is it synchronous or asynchronous processes? If they are synchronous
you can set up OFFSET OUT constraints which describes the internal
delay in the FPGA from the last clocked element in your design to the
output pin. Review the static timing report after PAR and you will get
the actual internal output delay. If this doesn't work for you please
provide some more information.

/Roger

On Nov 7, 6:46 am, raull...@hotmail.com wrote:
> hi, i have two processes in my vhdl code for my FPGA. the two
> processes each will generate a signal with the second one lagging
> around 5ns. problem is, i am told that this 5ns delay might not be
> from my coding but from the FPGA processing delay.. may i know how do
> i check for this processing delay? thanks



Article: 125861
Subject: Re: FPGA Clock signal
From: roger <roger.jons@gmail.com>
Date: Wed, 07 Nov 2007 11:22:29 -0000
Links: << >>  << T >>  << A >>
On Nov 7, 9:32 am, raull...@hotmail.com wrote:
> i would like to ask how can i capture the FPGA master clock signal in
> the oscilloscope? Bcos in the data sheet, it indicates that the master
> clock is located at pin N9 which is not accessible externally. please
> help. thanks a million

Hi,

Either you have to measure at the clock oscillator or route the clock
input out on a pin that is externally accessible. If you route through
you will get internal IO buffer delays added to your clock signal.

/Roger


Article: 125862
Subject: Re: ERROR:MDT - transparent bus interface connector
From: xenix <lastval@gmail.com>
Date: Wed, 07 Nov 2007 11:35:18 -0000
Links: << >>  << T >>  << A >>
thanx Mike for you answer but i didn't understand it well. can you
explain it more? thanx again:)

regards


Article: 125863
Subject: Re: Linux capable free/GPL SOFT CPU for XC3S500E?
From: ghelbig@lycos.com
Date: 7 Nov 2007 04:54:57 -0800
Links: << >>  << T >>  << A >>
On Nov 5, 2:11 pm, Wojciech Zabolotny <w...@ipebio15.ise.pw.edu.pl>
wrote:
> Hi All,
>
> I'm looking for a possibility to run Linux (may be a ucLinux) on a
> XC3S500E containing CPU and some custom peripherials.
> The hardware platform should be a Spartan3E Starter Kit (rev. D),
> or something like this.
>
> I have found the almost ready to use solution here:http://muranaka.info/pukiwiki/index.php?MicroBlaze%20uClinux%20and%20...
> but it is MicroBlaze based, which is not acceptable for me due to
> licensing terms (which are even worse for the Ethernet MAC controller).
> Has anybody tried to use the aeMB clone with the free OpenCores Ethernet
> MAC controller with the MicroBlaze ucLinux?
>
> The OpenRisc and LEON3 seem to be too big for XC3S500E (or at least I
> was not able to trim them sufficiently for this FPGA).
>
> The most preferable solution seem to be a CPU which has a standard
> instruction set (e.g. Plasma, which is MIPS I compatible), because in
> this case the toolchain is well supported.
>
> However I could not find any information if it is possible to run Linux
> on the Plasma (or mips789) SOFT CPU.
> Has anybody any experience in that subject?
>
> There is an ideal solution announced on the OpenCores:http://www.opencores.org/projects.cgi/web/m1_core/overview
> But it is only an idea (Development status :: alpha)
> --
> TIA & Regards,
> Wojtek Zabolotny

Linux will run on a soft CPU, including ones that fit into the
XC3S500.  There are uClinux ports for both the MicroBlaze and NIOS.

A point to mention is that uClinux runs without a memory manager.
There just aren't enough gates to fit one in an FPGA.

If you can't find an open-source port to MicroBlaze or NIOS, look for
an ARM7 port.  An ARM7 is an ARM9 with the memory manager removed.

Hope that helps,
G.


Article: 125864
Subject: Re: FPGA Clock signal
From: John_H <newsgroup@johnhandwork.com>
Date: Wed, 07 Nov 2007 14:02:30 GMT
Links: << >>  << T >>  << A >>
raullim7@hotmail.com wrote:
> i would like to ask how can i capture the FPGA master clock signal in
> the oscilloscope? Bcos in the data sheet, it indicates that the master
> clock is located at pin N9 which is not accessible externally. please
> help. thanks a million

Are you *sure* this signal is not externally accessible?  Typically the 
BGA package has a matrix of pads and vias.  The via for the clock signal 
should be exposed on the back of the board, ready for a steady hand to 
probe the clock right there "at" the package ball.

Article: 125865
Subject: [Linker script : EDK6.3 -> EDK 8.2] Parse error
From: Pasacco <pasacco@gmail.com>
Date: Wed, 07 Nov 2007 06:51:26 -0800
Links: << >>  << T >>  << A >>
Dear

I used to EDK 6.3 for multiprocessor system implementation.
The system worked fine.
But, when I upgraded to EDK 8.2, "parse error" occurs in the following
linker script.

------------------------------------------------------------------------
.init : { KEEP(*(.init)) } >
.fini : { KEEP(*(.fini)) } >
------------------------------------------------------------------------

Does anyone have this experience? If yes, let me know how to fix this
problem.

Thank you in advance.

Entire linker script is below.
----------------------------------------------------------------------------------------------------------------------
/* Linker Script automatically rev'ed up using XPS 8.2 */
/* Define default stack and heap sizes */
_START_ADDR = 0xFFFF8000; /*DEFINED(_START_ADDR) ? _START_ADDR :
0xFFFF0000;*/
_STACK_SIZE = 60k; /*DEFINED(_STACK_SIZE) ? _STACK_SIZE : 4k;*/
_HEAP_SIZE  = 60k; /*DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 4k;*/

/* Define boot.o to be the first file for linking. This statement is
mandatory. */
STARTUP(boot.o)

/* Specify the default entry point to the program */
ENTRY(_boot)

/* Define the Memory layout, specifying the start address and size of
the different memory locations */
MEMORY
{
  dRAM : ORIGIN = 0x040E0000, LENGTH = 0x20000    /*(128K)*/
  pRAM : ORIGIN = 0xFFFF8000, LENGTH = 0x8000-4  /*32K-4*/
  boot : ORIGIN = 0xFFFFFFFC, LENGTH = 4
}

/* Define the sections and where they are mapped in memory */

SECTIONS
{
   . = _START_ADDR;

   /*  .vectors section must be aligned on a 64k boundary
    * Hence should be the first section definition as bram start
location
    * is 64k aligned  */
    .vectors : /*BLOCK (64k):*/
    {
       *(.vectors)
    } > pRAM


   .boot0 : { *(.boot0)} > pRAM
   .text  : { *(.text)
    *(.text.*)
    *(.gnu.linkonce.t.*)
  }  > pRAM

/**********************************************/
/* Parse error */
/**********************************************/
.init : { KEEP(*(.init)) } >

.fini : { KEEP(*(.fini)) } >

   .boot  : { *(.boot) } > boot
   .data  :
   {
      *(.data)
          *(.data.*)
          *(.gnu.linkonce.d.*)
          CONSTRUCTORS
      *(.got2)
      *(.rodata)
      *(.fixup)
    *(.rodata.*)
    *(.gnu.linkonce.r.*)
   } > pRAM


.dtors : {
   __DTOR_LIST__ = .;
   ___DTORS_LIST___ = .;
   KEEP (*crtbegin.o(.dtors))
   KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
   KEEP (*(SORT(.dtors.*)))
   KEEP (*(.dtors))
   __DTOR_END__ = .;
   ___DTORS_END___ = .;
} > pRAM

.eh_frame : { *(.eh_frame) } > pRAM

.jcr : { *(.jcr) } > pRAM

.gcc_except_table : { *(.gcc_except_table) } > pRAM

.got : { *(.got) } > pRAM

.tdata : {
   *(.tdata)
   *(.gnu.linkonce.td.*)
} > pRAM

.tbss : {
   *(.tbss)
   *(.gnu.linkonce.tb.*)
} > pRAM

/*  .data1   : { *(.data1) } > ram
  .got1                : { *(.got1)   }  > ram

  .got2                : { *(.got2)   }  > ram

  .got1                  : { *(.got1)   }  > ram

  .dynamic          : { *(.dynamic) } > ram
*/

  .ctors   :
  {
/*    __CTOR_LIST__ = .;
    LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
    *(.ctors)
    LONG(0)
    __CTOR_END__ = .;*/

KEEP (*crtbegin.o(.ctors))
    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
    KEEP (*(SORT(.ctors.*)))
    KEEP (*(.ctors))
  } > pRAM
  __CTOR_LIST__ = ADDR(.ctors);
  __CTOR_END__ = ADDR(.ctors) + SIZEOF(.ctors);


   /* small data area (read/write): keep together! */
   .sdata : { *(.sdata)
   *(.gnu.linkonce.s.*)  }  > pRAM

   .sbss :
   {
     . = ALIGN(4);
     *(.sbss)
   *(.gnu.linkonce.sb.*)
     . = ALIGN(4);
   } > pRAM

   __sbss_start = ADDR(.sbss);
   __sbss_end = ADDR(.sbss) + SIZEOF(.sbss);

   /* small data area 2 (read only) */
  .sdata2 : { *(.sdata2)
   *(.gnu.linkonce.s2.*)  }  > pRAM

  __SDATA2_START__ = ADDR(.sdata2);
  __SDATA2_END__ = ADDR(.sdata2) + SIZEOF(.sdata2);

  .sbss2 : { *(.sbss2)
   *(.gnu.linkonce.sb2.*)
  }  > pRAM

  __SBSS2_START__ = ADDR(.sbss2);
  __SBSS2_END__ = ADDR(.sbss2) + SIZEOF(.sbss2);

  .bss :
  {
      . = ALIGN(4);
      *(.bss)
   *(.gnu.linkonce.b.*)
      *(COMMON)
      . = ALIGN(4);
      __bss_end = .;

      /* add stack and align to 16 byte boundary */
  _stack_end = .;
      . = . + _STACK_SIZE;
      . = ALIGN(16);
      __stack = .;

      /* add heap and align to 16 byte boundary */
          _heap_start = .;
      . = . + _HEAP_SIZE;
      . = ALIGN (16);
      _heap_end = .;
  } > dRAM

  __bss_start = ADDR(.bss);

}

ODY></HTML>


Article: 125866
Subject: did i miss edk 9.2
From: "u_stadler@yahoo.de" <u_stadler@yahoo.de>
Date: Wed, 07 Nov 2007 06:51:37 -0800
Links: << >>  << T >>  << A >>
hi

just i quick question: did i miss edk 9.2?
there are some service packs for edk 9.2 on the xilinx web site but i
can't find edk 9.2 itself on the webpage...
it still says edk 9.1. i'm i missing something?

thanks


Article: 125867
Subject: Re: did i miss edk 9.2
From: "MM" <mbmsv@yahoo.com>
Date: Wed, 7 Nov 2007 14:16:32 -0500
Links: << >>  << T >>  << A >>
<u_stadler@yahoo.de> wrote in message 
news:1194447097.787871.138930@d55g2000hsg.googlegroups.com...
> hi
>
> just i quick question: did i miss edk 9.2?
> there are some service packs for edk 9.2 on the xilinx web site but i
> can't find edk 9.2 itself on the webpage...
> it still says edk 9.1. i'm i missing something?
>

It's been out for a few days now. I even received my copy in mail... 
However, I haven't checked the web site...


/Mikhail







Article: 125868
Subject: Re: did i miss edk 9.2
From: Alain <no_spa2005@yahoo.fr>
Date: Wed, 07 Nov 2007 12:16:46 -0800
Links: << >>  << T >>  << A >>
go to :

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp

then look at :

EDK (Platform Studio)
Integrated development environment containing tools to facilitate the
creation of your embedded platform
Current:
9.2i - Nov 2007
Learn more  |  Download


Article: 125869
Subject: Custom processor developement issues
From: argee <nope@nope.com>
Date: Wed, 07 Nov 2007 21:35:30 +0100
Links: << >>  << T >>  << A >>
Hi all,

I'm trying to find a simple way to check the functional correctness of a 
custom processor/coprocessor/thingy on an FPGA (I'm kindo new at this). 
The core itself is generated automatically (and as such should behave as 
planned), so I only need to check if the algorithm that the processor is 
supposed to run is working correctly. The processor operates on the data 
in it's data memory and I'm looking for a simple way to check that 
memory's contents, both during simulation and from the FPGA. Available 
tools include Xilinx ISE Webpack + ModelSim XE and Altium Designer + 
Nanoboard NB1 (Spartan2). During simulation I wasn't able to access the 
memory's internal content (the VHDL variable) from ModelSim so I tried 
to verify the design by observing processor/memory comunication which is 
tedious and error-prone process (so is using a soft logical analyzer 
after implementation). Btw. the implementation uses memories generated 
with CoreGenerator if it makes any difference.
So, is there a simple way to run the program on the FPGA and (after the 
processor HALTs) read the results on my PC?

TIA

Regards,
RG

Article: 125870
Subject: Re: Linux capable free/GPL SOFT CPU for XC3S500E?
From: Wojciech Zabolotny <wzabolot@elektron.elka.pw.edu.pl>
Date: Wed, 7 Nov 2007 22:20:18 +0100
Links: << >>  << T >>  << A >>


On Wed, 7 Nov 2007, ghelbig@lycos.com wrote:

> Linux will run on a soft CPU, including ones that fit into the
> XC3S500.  There are uClinux ports for both the MicroBlaze and NIOS.
>

Yes, I know, however I'm looking for an open solution, which I could both 
give away to students, and to use in some research applications.
So the problem is that the cores should be open source and with 
permissive (preferrably free or even GPL) license.

> A point to mention is that uClinux runs without a memory manager.
> There just aren't enough gates to fit one in an FPGA.
>
> If you can't find an open-source port to MicroBlaze or NIOS, look for
> an ARM7 port.  An ARM7 is an ARM9 with the memory manager removed.
>

Well, however the only freely available synthesizable ARM7 implementation 
is the nnARM, which after its disappearance from OpenCores in 2001 is 
still available in many mirrors (just google for sARM_tb.zip ;-) ), but 
AFAIK it is not safe to use due to legal issues (and is not complete as well).
-- 
Thanks and regards,
Wojtek


Article: 125871
Subject: Re: Custom processor developement issues
From: Andrew FPGA <andrew.newsgroup@gmail.com>
Date: Wed, 07 Nov 2007 13:29:02 -0800
Links: << >>  << T >>  << A >>
I can't give an exact solution to your problem, but I will briefly
describe the strategy I took in verifying a soft core processor I
modified.

I modified the existing xilnx 8 bit picoblaze soft cpu by adding
several custom instructions including a multiply and turning it into a
pesudo 16 bit processor. I wrote a self-checking testbench in VHDL to
verify a range of processor instructions.
The testbench would:

1) Apply an instruction to the instruction bus ( I had the processor
instantiated in a testbench so that the testbench would feed
instructions).

2) Use modelsim "signal spy" to make key signals inside the cpu
available to my testbench. The most important signals being the data
written to the destination register.

3) Testbench checks the destination register contents and prints an
error if incorrect result.

4) Can make higher level tests my concatenating series of
instructions.

My personal view is that the only time one should be forced into
functional verification on real FPGA hardware is if the simulation is
impractical because
a) the time duration of the simulation takes too long
b) the input required is too complex or can only be generated/accessed
in real hardware.

You can also write non-synthesizable code into your cpu core, that
decodes registers, buses etc and displays text strings in nice
readable format. This helps debugging. Ken Chapman uses this technique
in the picoblaze softcore processor.

Cheers
Andrew


Article: 125872
Subject: Non-volatile FPGA in a small package
From: rickman <gnuarm@gmail.com>
Date: Wed, 07 Nov 2007 13:46:56 -0800
Links: << >>  << T >>  << A >>
I am looking for my usual FPGA in a small package.  This is a contract
design and the customer has a preference to avoid BGAs.  The only
leaded part that will fit the board is a 100 pin TQFP.  I found a
couple of MAX II devices in this package and Lattice has some MACHXO
parts as well as one XP part.  Of the three, I like the XP better as
it has 3000 LUTs to work with as well as PLLs.

Lattice also has an XP2 line which should be lower cost/higher density
as well as lower power.  But they don't seem to be available yet.  I
don't see stock on any parts and it looks like they are not supporting
the TQ100 package.

I also wanted to consider the Xilinx XC3S-AN parts.  The combinations
of device and package are very limited with a one to one
relationship.  Each part comes in a different package and *only* that
package.  So there is no chance to upgrade to a different density part
once you design the board.  Of course, I don't think this is a real
issues for this app, since any of the FPGA types are well large
enough.  But I also can't find any pricing.  The other parts are all
in the $10 - $15 range.  I have no idea if the XC3S-AN is in that same
range.

So does anyone know if the Lattice XP2 and the Xilinx XC3S-AN parts
are ready for prime time?  Should I skip these parts and go with one
of the other choices?  BTW, the customer has experience with the
Altera parts and can already program them in system.  So that is a
definite plus for the MAX II.  But it is otherwise at the back of the
field with the least available LUTs and no PLL.  So I really want to
use a different part.


Article: 125873
Subject: Re: Non-volatile FPGA in a small package
From: "Symon" <symon_brewer@hotmail.com>
Date: Wed, 7 Nov 2007 14:11:22 -0800
Links: << >>  << T >>  << A >>
Hi Rick,
Dunno if this helps, saw it in EDN yesterday.
http://www.edn.com/article/CA6495296.html?nid=3351&rid=588729451

"High noon for FPGAs: Low-cost-versus- high-end showdown
Greenhorns in the high-end-FPGA market, Lattice and Actel are shooting it 
out against old hands Xilinx and Altera in the battle for low-cost devices."
HTH., Syms. 



Article: 125874
Subject: Re: Custom processor developement issues
From: argee <nope@nope.com>
Date: Wed, 07 Nov 2007 23:58:37 +0100
Links: << >>  << T >>  << A >>
Andrew FPGA wrote:

> I modified the existing xilnx 8 bit picoblaze soft cpu by adding
> several custom instructions including a multiply and turning it into a
> pesudo 16 bit processor. I wrote a self-checking testbench in VHDL to
> verify a range of processor instructions.

This doesn't directly apply to this particular problem I'm trying to 
solve but it sure is a great help for my upcoming hobby projects dealing 
with general-purpose cpus (hopefully the next one will have more than 4 
instructions ;).

These processors I'm dealing with are automatically generated 
instruction-less microcode-driven thingies (I'm exploring architectural 
optimizations), so I hope I'm not going to have to debug their internal 
workings. Just want to read the results (and measure performance) for 
now and it's a bit frustrating not even being able to do that. *must 
learn more*

 > 2) Use modelsim "signal spy" to make key signals inside the cpu
 > available to my testbench. The most important signals being the data
 > written to the destination register.

I will definitely check this out. This "signal spy" seems essential for 
verification. Never heard of it before, though. :/

> My personal view is that the only time one should be forced into
> functional verification on real FPGA hardware is if the simulation is
> impractical because
> a) the time duration of the simulation takes too long

Hmmm... So it was wrong of me to assume that some kind of functional 
verification in FPGAs is common. I thought there was some simple way to 
i.e. read the contents of registers and memories etc. Must be all this 
LiveDesign propaganda getting to me...

> You can also write non-synthesizable code into your cpu core, that
> decodes registers, buses etc and displays text strings in nice
> readable format. This helps debugging. Ken Chapman uses this technique
> in the picoblaze softcore processor.

I was thinking about something like that but dismissed it having had 
little experience with manually creating testbenches and testing it in 
an FPGA seemed way more cool. I think I'll try digging into a manual and 
writing a proper testbench that displays the memory content upon 
receiving the HALT signal. And assume that the synthesizable HDL + 
CoreGen memories combination is functionally equal to the behavioral 
model. ;)

Anyways, thanx a bunch! These ideas will be a great help!

Regards,
RG



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