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Messages from 133500

Article: 133500
Subject: Re: Nintendo DS Screenshots / Video Capture
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Wed, 02 Jul 2008 11:09:28 +1200
Links: << >>  << T >>  << A >>
adwordsmcc@r720.co.uk wrote:
> Hi All,
> 
> I'm starting to look at building something that will allow me to take
> screenshots and do video capture of both of the Nintendo DS screens.

It's not a fpga solution, but I think there are a number of
PC emulators, of these game consoles.
Using a PC emulator, would give a simple way to capture screens.

If you do want a HW path, you will need access to an oscilloscope,
to check the details, but a FPGA+Memory would certainly
have the horsepower to do this.

-jg


Article: 133501
Subject: Re: Nintendo DS Screenshots / Video Capture
From: Paul Urbanus <urbpublic@hotmail.com>
Date: Tue, 01 Jul 2008 19:00:54 -0500
Links: << >>  << T >>  << A >>
adwordsmcc@r720.co.uk wrote:
> Hi All,
> 
> I'm starting to look at building something that will allow me to take
> screenshots and do video capture of both of the Nintendo DS screens.
> 
> Amazingly there is actually nothing available that you can buy to do
> this (publically anyway), so why not build it!
> 
> I knew I was onto something when I found this...
> http://home.comcast.net/~olimar/DS/jumbotron/ That was enough to prove
> to me that if the creator of that is able to grab a screenie so am I
> (in theory )! Unfortunaltly the creator is either not picking up mails
> from that address or is being hammered with similar questions and is
> not responding which leaves a noob like me a bit lost....
> 
> Anyway, undetered I'd like to capture a screenshot from one screen and
> squirt it through an RS232 connection where I can have a simple home
> made .NET app listening (I'm a .NET developer in the day ) to create a
> simple *.bmp or similar.
> 
> I've been eyeing up the Diligent Spartan 3E Starter Board to help out
> with the project as it has a few handy bits already onboard (namely
> RS232, VGA (3 bit only I think?) for some simple downsampled ouput and
> some memory to buffer a frame should I need to).

If you look at the project page, you'll see that the Neal used a Spartan 
3 Starter Kit, available from Xilinx for $149 (same price as the Spartan 
3E Starter Kit). Or, you can buy the Spartan 3 Starter Kit direct from 
the manufacturer for $99 - for some reason Xilinx raised their price, 
which used to be $99. I suspect they are trying to move folks to the 
newer 3E parts.

For a newbie such as yourself (or even an oldie like me) and a project 
such as this, I highly recommend the S3 kit over the S3E kit, for a 
number of reasons.

1. The expansion connectors on the S3 are standard 0.1 inch pitch 
headers, while the S3E board uses a Hirose fine pitch connector for most 
of the FPGA I/O. There are some 6-pin 0.1 inch connectors on the 3E 
board, but the total number of I/O available on these connectors is a 
small fraction of the FPGA I/O. It is much easier for a hobbyist (or 
even a professional) to connect stuff to the 0.1 inch headers.

2. The RAM on the S3 board is SRAM, while the S3E board only has DDR2 
SDRAM. It is orders of magnitude easier to implement a frame buffer 
(which you will need for your project) in SRAM than DDR2 DRAM. The DDR2 
requires a controller, while the POSR (Plain Old Static RAM) just 
requires you to hook up the address and data lines.

3. The LED display one the S3 board is very easy to use, while the LCD 
on the S3E requires more circuitry to initialize and send data to the 
display. The only thing you need for the LED display is some matrix 
scanning code, which is provided by Xilinx in their demo code (which is 
written in VHDL, not verilog). The LED display is very handy for debugging.

4. The S3 board has 8 slide switches and 4 pushbutton switches for 
general use, while the S3E board primarily uses a rotary encoder which 
needs to be decoded. Switches are also great for debugging and changing 
operating modes easily.


Here's the link to Digilent page for the S3 kit.
http://www.digilentinc.com/Products/Detail.cfm?Prod=S3BOARD&Nav1=Products&Nav2=Programmable


> 
> I've isolated the RGB (6 bit each) solder points and found the VSYNC
> and DCLK (data sampling clock?) solder points as well. According to
> the page I've found I can simply count the clocks (263 exactly) to
> find the HSYNC.
> 
> For reference heres a link to the specs of an LCD that is appently
> very close to the Nintendo DS ones... http://www.sharpsma.com/Page.aspx/americas/en/part/LQ030B7DD01/
> 
> However, I am a total noob (both FPGA + General electronics) and I
> have some basic questions before proceeding if anybody can help
> (crosses fingers!  )
> 
> 1. I'm guessing I just buy the 100 pin breadboard module for the
> Diligent Spartan 3E Starter Board

For the S3 board, all you need for connectivity are breakaway male 
header strips, which are quite inexpensive and readily available. These 
will plug directly into the S3 I/O connectors. TIP: Buy header strips 
where the pins are extra long, which will making probing the signals easier.

  and pop the RGB + DCLK + VSYNC
> straight into it? Do I need to check the voltage first or anything to
> make sure its safe? Will I need to put a ground pin in as theres a GRD
> solder point on the Nintendo DS PCB?

I suspect the signal levels at the DS are 2.5V or 3.3V. Since you are 
only receiving signals at the FPGA, you can set the input standard to 
LVTTL and you should be fine.

You definitely need GNDs, and preferably more than one.

> 
> 2. When 'counting clocks' for the HSYNC I'm assuming the author of the
> page already mentioned was talking about counting the clocks of the
> DCLK, agree? How would I go about that in Verilog?

I'm not a verilog person, but here's the basic functional flow.

1. Implement a counter with a count length of 263 (counts from 0 to 
262). This will be used to determine the horizontal position of the pixels.
2. Detect either the rising or falling edge of VSYNC - pick one and only 
one edge.
3. Use the detected VSYNC edge to load your horizontal counter with a 
specific value, initially to zero. If your image is shifted horizontally 
after you grab a frame, then adjust this preload value to get the image 
properly horizontally positioned.
4. Implement a second counter which keeps track of the line number of 
the screen image. Clear this counter with the detected VSYNC edge 
generate in step 2.
5. Increment the vertical counter from step 4 whenever the horizontal 
counter value is 262 (max count).

> 
> 3. To build up the frame of data do I just sample the RBG pins every
> clock cycle?

After you sample the data, you have to do something with it. In this 
case, you need to write it to the S3 SRAM. The SRAM is 32 bits wide, and 
the LCD data is 18 bits (based upon the Sharp data sheet provided on 
Neal's project page). So, one pixel will fit, with room to spare, in a 
single 32 bit SRAM word.

The next question is, to which address in SRAM should it be written? Now 
is where we will use our horizontal and vertical counters.

The easiest thing to do is to concatenate the counters to form the SRAM 
address. This will waste a lot of the memory, because the horizontal 
counter has a max value of 262.

Why? Because you must use 9 bits of address to count up to 262, and the 
space between counts 263 through 511 will be unused. But, who cares - 
you have plenty of RAM so don't worry about it. But, your software will 
have to know where to find the 256 pixels (out of the 512 allocated 
memory words) for each line of the image. You can make this easier by 
selecting the preload value in step 3 so that the 256 pixels of the 
image are in the first or last 256 of the 512 locations.

If you want to simplify the code (not by much, though) in step 3, you 
can clear the counter instead of preloading it. Then, your software can 
read the SRAM and unwind the data. This is a classic tradeoff of whether 
  a part of the functionality should be implemented in software or 
hardware. In this case, the hardware cost is minimal. But, in 1980, 
there was difference in price - in dollars and pin count - between a TTL 
counter chip with clear only, and a TTL counter chip with preload.

By convention, the horizontal counter is usually connected to the lower 
order address bits, although it is not required. Maintaining this 
convention, the SRAM address bits would be connected to the counters as 
follows.

A A A A A A A A A A A A A A A A A   SRAM
1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
| | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | |
V V V V V V V V H H H H H H H H H   COUNTERS
7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0

This should allow you to capture the screen data. So, you'll need to add 
some way (using a PB switch, maybe) to trigger the screen capture. Or, 
you could detect activity on the serial port to trigger the capture.

After the capture is finished, you'll need to dump the data out of the 
S3 board to your PC. The serial port is probably the easiest way to do 
this. You can leave all of your counters that you used in your capture 
process connected. Just switch the clock and VSYNC counter inputs from 
the DS signals to an internal set that first generates a psuedo VSYNC, 
then generates a clock after each pixel has been transferred over the 
serial port. Note that since each pixel is only 6 bits, you can send a 
pixel to the PC using 3 consecutive bytes.


  The author of the page already mentioned points out that
> the bottom screen is read on the rising clock edge and the top on the
> falling, how do I go about sampling on each edge?
> 
> If theres ANY other advice you have PLEASE do mention it.  Good book
> etc are always welcome...

I hope I didn't spoil you project by giving too much info.

> 
> Pete

Urbite

Article: 133502
Subject: Re: How do I program an fpga once it has been designed and layout is complete
From: "Symon" <symon_brewer@hotmail.com>
Date: Wed, 2 Jul 2008 01:09:03 +0100
Links: << >>  << T >>  << A >>
<phxagent@gmail.com> wrote in message 
news:0232ce5e-f1e0-4c0e-b11b-0d850c622ce6@d19g2000prm.googlegroups.com...
>
> I have the resources to write VHDL/Verilog, netlist it and do the
> layout(incl. routing), but how do I program this fpga?
>

Very carefully!

Go and do some reading. My advice is to start with the website of the FPGA 
vendor you've chosen. Alternatively, as you seem to work for Intel, get them 
to send you on an expensive course.

HTH, Syms.

p.s. http://catb.org/~esr/faqs/smart-questions.html 



Article: 133503
Subject: Re: How do I program an fpga once it has been designed and layout is complete
From: hal-usenet@ip-64-139-1-69.sjc.megapath.net (Hal Murray)
Date: Tue, 01 Jul 2008 19:20:29 -0500
Links: << >>  << T >>  << A >>

>I have the resources to write VHDL/Verilog, netlist it and do the
>layout(incl. routing), but how do I program this fpga? I guess this is
>something I am not too clear about. Thanks folks

Look in the data sheet.  There will be a section on that area, maybe
called Configuration.

The compiler will give you a pile of bits.  Typically, you feed them
serially to the FPGA with clock and data pins.  You can bit bang it from
a small CPU. In a different mode, the FPGA  can probably wiggle the
clock to load itself from a serial ROM.  (Then you have to program the ROM.)

You can usually load them via JTAG.

The vendor probably provides a tool to do it.

It's probably simplest to get one of the low cost starter kits
and follow the directions for one of their demos.  Or just
read their documention to see how it's done.

-- 
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 133504
Subject: Re: Nintendo DS Screenshots / Video Capture
From: Mark McDougall <markm@vl.com.au>
Date: Wed, 02 Jul 2008 11:23:26 +1000
Links: << >>  << T >>  << A >>
Jim Granville wrote:

> It's not a fpga solution, but I think there are a number of
> PC emulators, of these game consoles.
> Using a PC emulator, would give a simple way to capture screens.

Nintendo DS emulation is still in relative infancy, with only a handful of 
commercial games running - and rather poorly at that. You also need to 
acquire additional "grey" hardware to dump the roms or source some pirate 
copies... :(

Regards,

-- 
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

Article: 133505
Subject: Re: Standard forms for Karnaugh maps?
From: Eric Smith <eric@brouhaha.com>
Date: Tue, 01 Jul 2008 19:00:29 -0700
Links: << >>  << T >>  << A >>
Evan Lavelle wrote:
> There's a common misconception that K-maps are/were only used for
> minimisation, so they're now irrelevant. Actually, K-maps are probably
> the most fundamental tool for the design, specification, and analysis
> of combinatorial logic.

That may have been true at one time, but it's not true any longer.
Aside from my own experience, I know quite a few digital designers,
and most have not used a K-map since school.

> They're also independent of the
> implementation, which makes them ideally suited for verification of
> the same circuits. They're about 'what', not 'how'. An HDL
> description, on the other hand, is exactly the opposite - 'how', not
> 'what'.

That entirely depends on how you write the HDL.  It's possible and
not even all that uncommon to write behavioral HDL that specifies
what is desired, and let the synthesizer decide how to implement it.

In VHDL one way to do that is to use conditional assignment statements,
e.g.,

     Q <=      '1' when A = '0' and B = '0' and C = '0'
          else '0' when A = '0' and B = '0' and C = '1'
          else '1' when A = '0' and B = '1' and C = '0'
          else '0' when A = '0' and B = '1' and C = '1'
          else '1' when A = '1' and B = '0' and C = '0'
          else '0' when A = '1' and B = '0' and C = '1'
          else '0' when A = '1' and B = '1' and C = '0'
          else '1';

That specifies the desired behavior of a combinatorial circuit with
three inputs and one output, but nowhere does it explicitly direct the
synthesizer to implement it in any particular way.  The synthesizer could
use a sum-of-products and generate four three-input AND gates and a
four-input OR gate, or it might generate a two-input NAND and a two-input
XOR, or an eight-input mulitplexer.

Even though I knew the desired behavior of the circuit, I didn't have
any need to write a K-map, nor would doing so have benefitted me in
any way.  While this is a trivial example, the same is true of more
complex combinatorial logic.  For combinatorial circuits with four
or fewer inputs, I could easily write out a K-map, but I wouldn't
gain anything.  For five or more inputs, writing a K-map by hand
becomes very tedious and error-prone, and a good synthesizer can minimize
the logic just as well as I can anyhow.

Article: 133506
Subject: Re: How do I program an fpga once it has been designed and layout is
From: phxagent@gmail.com
Date: Tue, 1 Jul 2008 19:01:28 -0700 (PDT)
Links: << >>  << T >>  << A >>
Thanks for the responses, but I think I need to be more clear on my
question. First off, this is for a class project for my advanced
degree, so my employer has nothing to do with it.

When I mean design an FPGA, I literally mean designing it. Not
programming a vendor's FPGA.

So going back to my original question, if I did design an FPGA with
LUTs and SRAM, how can I program this FPGA to do a particular
function? Do I write the software? If so, is that an easy thing to do?

Are there any tools available that would let me program any FPGA? I
looked at DAGGER, but seems like it needs an input file from the VPACK
tool. thanks again.

Article: 133507
Subject: Re: How do I program an fpga once it has been designed and layout
From: Jeff Cunningham <jcc@sover.net>
Date: Wed, 02 Jul 2008 00:15:12 -0400
Links: << >>  << T >>  << A >>
phxagent@gmail.com wrote:
> Thanks for the responses, but I think I need to be more clear on my
> question. First off, this is for a class project for my advanced
> degree, so my employer has nothing to do with it.
> 
> When I mean design an FPGA, I literally mean designing it. Not
> programming a vendor's FPGA.
> 
> So going back to my original question, if I did design an FPGA with
> LUTs and SRAM, how can I program this FPGA to do a particular
> function? Do I write the software? If so, is that an easy thing to do?
> 
> Are there any tools available that would let me program any FPGA? I
> looked at DAGGER, but seems like it needs an input file from the VPACK
> tool. thanks again.

I think you still need to explain yourself more. Are you creating a 
design of your own custom FPGA (that other people could theoretically 
program) for a class project? Are you planning to actually fab a chip 
through some university program like MOSIS? That seems like an pretty 
ambitious class project.

When you say software to program the FPGA are you talking about 
something to download the bitstream? Or are you talking about the 
complete HDL synthesis and place and route tool chain?

-Jeff

Article: 133508
Subject: Re: How do I program an fpga once it has been designed and layout is complete
From: Muzaffer Kal <kal@dspia.com>
Date: Tue, 01 Jul 2008 21:24:37 -0700
Links: << >>  << T >>  << A >>
On Tue, 1 Jul 2008 19:01:28 -0700 (PDT), phxagent@gmail.com wrote:

>Thanks for the responses, but I think I need to be more clear on my
>question. First off, this is for a class project for my advanced
>degree, so my employer has nothing to do with it.
>
>When I mean design an FPGA, I literally mean designing it. Not
>programming a vendor's FPGA.
>
>So going back to my original question, if I did design an FPGA with
>LUTs and SRAM, how can I program this FPGA to do a particular
>function? Do I write the software? If so, is that an easy thing to do?
>
>Are there any tools available that would let me program any FPGA? I
>looked at DAGGER, but seems like it needs an input file from the VPACK
>tool. thanks again.

You have to also design the programming architecture into your FPGA.
FPGAs are basically SRAM (LUTs are SRAM too), configurable DFF cells
and a whole lot of wires with switches on each end. The SRAM blocks
and DFFs (assuming you don't have any other hard macros ala
multipliers etc) have their inputs and outputs connected to some
switches which are connected to the wires too. So you connect all the
control inputs of the switches to some regular DFFs which are
connected in a scan chain type connection themselves and when you
generate the programming file, you shift it in upon which you
configure all the switches and the configuration options of your DFFs.
If you also want to initialize your SRAM blocks you can design
configuration time memory controllers which write the shifted value
into them to the SRAM. 

If you're doing any non-trivial FPGA design, I think you'll find that
generating the actual programming file itself from your logic design
specification is one of the most time consuming tasks.

Article: 133509
Subject: Re: How do I program an fpga once it has been designed and layout is
From: mng <michael.jh.ng@gmail.com>
Date: Tue, 1 Jul 2008 21:28:59 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 1, 7:01=A0pm, phxag...@gmail.com wrote:
> Thanks for the responses, but I think I need to be more clear on my
> question. First off, this is for a class project for my advanced
> degree, so my employer has nothing to do with it.
>
> When I mean design an FPGA, I literally mean designing it. Not
> programming a vendor's FPGA.

This sounds rather involved for a class project. And more of an
exercise in CAD tools than anything else.

> So going back to my original question, if I did design an FPGA with
> LUTs and SRAM, how can I program this FPGA to do a particular
> function? Do I write the software? If so, is that an easy thing to do?

I'm not sure what you're getting at here. What do you mean by
"program", exactly? Putting the bitfile into the FPGA? Generating the
bitfile from a placed/routed design?

> Are there any tools available that would let me program any FPGA? I
> looked at DAGGER, but seems like it needs an input file from the VPACK
> tool. thanks again.

You might be able to modify DAGGER to do what you want. But this might
be a good time to take a step back and figure out 1) what exactly you
want to achieve with your project, 2) what requisite knowledge you
have yet to acquire, 3) whether it's doable in the timeframe
specified.

Cheers,
Mike

Article: 133510
Subject: Re: How do I program an fpga once it has been designed and layout is
From: Peter Alfke <alfke@sbcglobal.net>
Date: Tue, 1 Jul 2008 21:48:06 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 1, 9:28=A0pm, mng <michael.jh...@gmail.com> wrote:
> On Jul 1, 7:01=A0pm, phxag...@gmail.com wrote:
>
> > Thanks for the responses, but I think I need to be more clear on my
> > question. First off, this is for a class project for my advanced
> > degree, so my employer has nothing to do with it.
>
> > When I mean design an FPGA, I literally mean designing it. Not
> > programming a vendor's FPGA.
>
> This sounds rather involved for a class project. And more of an
> exercise in CAD tools than anything else.
>
> > So going back to my original question, if I did design an FPGA with
> > LUTs and SRAM, how can I program this FPGA to do a particular
> > function? Do I write the software? If so, is that an easy thing to do?
>
> I'm not sure what you're getting at here. What do you mean by
> "program", exactly? Putting the bitfile into the FPGA? Generating the
> bitfile from a placed/routed design?
>
> > Are there any tools available that would let me program any FPGA? I
> > looked at DAGGER, but seems like it needs an input file from the VPACK
> > tool. thanks again.
>
> You might be able to modify DAGGER to do what you want. But this might
> be a good time to take a step back and figure out 1) what exactly you
> want to achieve with your project, 2) what requisite knowledge you
> have yet to acquire, 3) whether it's doable in the timeframe
> specified.
>
> Cheers,
> Mike

I think we all wonder what you want to achieve with your project.
You could re-invent and re-implement what Xilinx did 25 years ago, but
what would that do for you, or for anybody?
It's hard to help you when you leave so many things un-explained.
Peter Alfke

Article: 133511
Subject: VHDL code for RCOM message
From: jsreenivas.naidu@gmail.com
Date: Tue, 1 Jul 2008 21:58:36 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi,

I am presently writing Testcases and Test benches for my Communication
control modules which are used in Boeing spoilers.

I need the code for checking (validate and verify) a Message format of
my RCOM (remote electronic unit Communication). The message format is


           < StartBit> <Header Word><1-29 data word><checker word(odd
vertical parity)>

Here each word is 32-bit in data word
Header word is 5-bit

It would be a great helpful if any one gives clear steps for verify
this format

Thanks,
Sreeniv.


Article: 133512
Subject: Re: How do I program an fpga once it has been designed and layout
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Wed, 02 Jul 2008 17:24:18 +1200
Links: << >>  << T >>  << A >>
phxagent@gmail.com wrote:
> Thanks for the responses, but I think I need to be more clear on my
> question. First off, this is for a class project for my advanced
> degree, so my employer has nothing to do with it.
> 
> When I mean design an FPGA, I literally mean designing it. Not
> programming a vendor's FPGA.
> 
> So going back to my original question, if I did design an FPGA with
> LUTs and SRAM, how can I program this FPGA to do a particular
> function? 

You set the config bits, typically serially loaded.

> Do I write the software? 

Yes

> If so, is that an easy thing to do?

No.

> 
> Are there any tools available that would let me program any FPGA? I
> looked at DAGGER, but seems like it needs an input file from the VPACK
> tool. thanks again.

What does your Professor want ?

How many hours are allocated to this ?

Does he want working silicon (!), or a simulated result ?

How will your FPGA vary fom the 'mainstream' ones, and what
aspect of that difference do you need to demonstrate ?

How large does this need to be ?


-jg




Article: 133513
Subject: real time FIR implementation in FPGA
From: raj <rajesh.obli@gmail.com>
Date: Tue, 1 Jul 2008 22:42:32 -0700 (PDT)
Links: << >>  << T >>  << A >>
hai,

I have stored my filter coefficients in FPGA.I have not stored my
input samples  it will directly given to the FPGA pin.My FPGA logic
will wait for new input samples,accepts it,process it and then wait
for the new sample..

from the above my filter is not operating at real time..what is the
necessary change to operate at real time?how can i handle real time
signal samples?do my fpga need to have software support?basically i am
confused with real time signal input to fpga...

suppose i have a sine samples how it should inputted to fpga?

those who already implemented FIR clarify this got tired hitting
google to get answers..

regards,
raj

Article: 133514
Subject: Re: How do I program an fpga once it has been designed and layout is complete
From: Ben Jackson <ben@ben.com>
Date: Wed, 02 Jul 2008 05:42:46 GMT
Links: << >>  << T >>  << A >>
On 2008-07-02, phxagent@gmail.com <phxagent@gmail.com> wrote:
>
> So going back to my original question, if I did design an FPGA with
> LUTs and SRAM, how can I program this FPGA to do a particular
> function? Do I write the software? If so, is that an easy thing to do?

For proof-of-concept you should be able to generate a bitstream that hooks
a few gates to a flop from inputs to outputs.  Since you designed the FPGA,
you'd know how to do that.

If you want to generate that from a high-level description there will be
significant software involved.  You may be able to take a frontend like
Icarus Verilog and write a new backend for your project, but it will take
considerable software expertise.

-- 
Ben Jackson AD7GD
<ben@ben.com>
http://www.ben.com/

Article: 133515
Subject: Re: VHDL code for RCOM message
From: Mike Treseler <mtreseler@gmail.com>
Date: Tue, 01 Jul 2008 22:51:48 -0700
Links: << >>  << T >>  << A >>
jsreenivas.naidu@gmail.com wrote:

> I am presently writing Testcases and Test benches for my Communication
> control modules which are used in Boeing spoilers.

Oh my.

> I need the code for checking (validate and verify) a Message format of
> my RCOM (remote electronic unit Communication). The message format is
> 
> 
>  < StartBit> <Header Word><1-29 data word><checker word(odd vertical parity)>

I'm not sure how to find the end of packet,
but once I figured that out, I would shift
a packet in and verify the parity to start with.


> It would be a great helpful if any one gives clear steps for verify
> this format

Hope you work it out.
Until then, I'll be on airbus ;)

      -- Mike Treseler

Article: 133516
Subject: Re: How do I program an fpga once it has been designed and layout is
From: phxagent@gmail.com
Date: Tue, 1 Jul 2008 23:31:40 -0700 (PDT)
Links: << >>  << T >>  << A >>
Thank you all for your inputs on this subject. You are right, I would
first want to evaluate what I am signing-up for and thats exactly what
I am doing in this group :) It would definitely not go all the way
into fabrication, but a proof of concept would be good enough. The
idea is to create a novel tile architecture that does not exist
today.

Question for Mike. I thought Dagger was a web-based tool. Can I really
modify it?

Article: 133517
Subject: Re: VHDL code for RCOM message
From: Frank Buss <fb@frank-buss.de>
Date: Wed, 2 Jul 2008 08:46:43 +0200
Links: << >>  << T >>  << A >>
jsreenivas.naidu@gmail.com wrote:

> I am presently writing Testcases and Test benches for my Communication
> control modules which are used in Boeing spoilers.

I wonder how fast it needs to be for a spoiler. Do you really use a FPGA
for controlling the spoiler or is it just in the test equipment? FPGAs are
very complex, synthesizer software and hardware. It is easy to write VHDL
programs, which e.g. enter illegal statemachine states, if input signals
are not aligned to clock. Unless you write big and time consuming
testcases, maybe you won't detect such bugs.

I would use a microcontroller for both, then it is only some lines of C
code (or maybe SparkADA, which is better for mathematical proving programs
for critical systems).

-- 
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

Article: 133518
Subject: Re: real time FIR implementation in FPGA
From: Frank Buss <fb@frank-buss.de>
Date: Wed, 2 Jul 2008 09:05:38 +0200
Links: << >>  << T >>  << A >>
raj wrote:

> I have stored my filter coefficients in FPGA.I have not stored my
> input samples  it will directly given to the FPGA pin.My FPGA logic
> will wait for new input samples,accepts it,process it and then wait
> for the new sample..
> 
> from the above my filter is not operating at real time..

First you should take a look at the definition of "real-time" :

http://en.wikipedia.org/wiki/Real-time

So if you design a hard real-time system, the main requirement is that your
FPGA outputs some signal after some maximum time, after some input arrives.
E.g. if you feed a signal every second and you specify, that the output
must be available after one second and if your FPGA does this, it is
operating at real-time.

> suppose i have a sine samples how it should inputted to fpga?

If you have already samples (e.g. a 16 bit parallel signal), just feed it
to the FPGA. Maybe the sampling clock would be a good idea, too.

-- 
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

Article: 133519
Subject: Re: real time FIR implementation in FPGA
From: raj <rajesh.obli@gmail.com>
Date: Wed, 2 Jul 2008 00:41:34 -0700 (PDT)
Links: << >>  << T >>  << A >>
hai,

if you feed a signal every second and you specify, that the output
must be available after one second and if your FPGA does this, it is
operating at real-time

I don't know how to feed the samples to FPGA input pin as the samples
are coming from outside the chip?what is the logic behind this?

For testing purpose i used a text file and dump my samples into it and
given to the input of FPGA..the same task how can i do it in the board
which has this FPGA?pls clarify the same

regards,
raj





On Jul 2, 12:05=A0pm, Frank Buss <f...@frank-buss.de> wrote:
> raj wrote:
> > I have stored my filter coefficients in FPGA.I have not stored my
> > input samples =A0it will directly given to the FPGA pin.My FPGA logic
> > will wait for new input samples,accepts it,process it and then wait
> > for the new sample..
>
> > from the above my filter is not operating at real time..
>
> First you should take a look at the definition of "real-time" :
>
> http://en.wikipedia.org/wiki/Real-time
>
> So if you design a hard real-time system, the main requirement is that you=
r
> FPGA outputs some signal after some maximum time, after some input arrives=
.
> E.g. if you feed a signal every second and you specify, that the output
> must be available after one second and if your FPGA does this, it is
> operating at real-time.
>
> > suppose i have a sine samples how it should inputted to fpga?
>
> If you have already samples (e.g. a 16 bit parallel signal), just feed it
> to the FPGA. Maybe the sampling clock would be a good idea, too.
>
> --
> Frank Buss, f...@frank-buss.dehttp://www.frank-buss.de,http://www.it4-syst=
ems.de


Article: 133520
Subject: Timing Analyzer report for IOBs -- 1GSPS DAC interface
From: PatC <pato@REMOVETHISpatocarr.com>
Date: Wed, 02 Jul 2008 00:43:52 -0700
Links: << >>  << T >>  << A >>
Hi,

I'm designing a 1GSPS DAC interface that sends a 500MHz clock and 16bit 
DDR parallel data in Virtex-5 xc5vlx95t-1ff1136 device.

The 500MHz input clock is driven to a BUFIO that connects to the CLK 
input of the OSERDES blocks.

This same input clock is driven to a BUFR that divides its frequency by 
2 and connects to the CLKDIV input of the OSERDES blocks and the read 
side of an asynchronous FIFO that holds the data samples.

Each OSERDES output is connected to an IODELAY element and then to a OBUFDS.

I added period constraints for all the clocks in the design into the UCF 
file and built the code. It passed PAR with 0 timing errors.



In Timing Analyzer tool, I noticed that the 500MHz input clock and its 
associated BUFIO clock paths were not analyzed, whereas all the FPGA 
fabric logic that runs @ 250MHz met the timing constraints.

How can I make sure that my design does not have any timing issues at 
the 500MHz input and BUFIO clocks?


Thanks in advance,
-Pat


PS: Originally posted on X's user forums by ShantM.

Article: 133521
Subject: Re: VHDL code for RCOM message
From: "HT-Lab" <hans64@ht-lab.com>
Date: Wed, 2 Jul 2008 08:49:03 +0100
Links: << >>  << T >>  << A >>

<jsreenivas.naidu@gmail.com> wrote in message 
news:5dbbb591-7892-4905-9e69-74c6924b5b5e@34g2000hsf.googlegroups.com...
> Hi,
>
> I am presently writing Testcases and Test benches for my Communication
> control modules which are used in Boeing spoilers.
>
> I need the code for checking (validate and verify) a Message format of
> my RCOM (remote electronic unit Communication). The message format is
>
>
>           < StartBit> <Header Word><1-29 data word><checker word(odd
> vertical parity)>
>
> Here each word is 32-bit in data word
> Header word is 5-bit
>
> It would be a great helpful if any one gives clear steps for verify
> this format

If this is not a student project then I would suggest you look into 
assertions (used with a formal tool and not a simulator). This is the only 
way to test something exhaustively. PSL/SVA are not complicated languages 
but I would still recommend going onto a course even if it is only 1 day.

In the meantime I will join Mike on Airbus :-)

Hans
www.ht-lab.com

>
> Thanks,
> Sreeniv.
> 



Article: 133522
Subject: Re: real time FIR implementation in FPGA
From: Frank Buss <fb@frank-buss.de>
Date: Wed, 2 Jul 2008 10:26:35 +0200
Links: << >>  << T >>  << A >>
raj wrote:

> I don't know how to feed the samples to FPGA input pin as the samples
> are coming from outside the chip?what is the logic behind this?

If you say "the samples are coming from outside the chip", I assume you
have already some digital signal source. Take a look at the description of
the source, then solder the pins of the FPGA to the source (maybe after
level converting) and implement the data processing in VHDL.

If you don't have digital signals, use a digital to analog converter (DAC)
and take a look at the datasheet of the DAC how to handle the data in your
FPGA.

Maybe I should filter gmail-postings :-)

-- 
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

Article: 133523
Subject: Re: real time FIR implementation in FPGA
From: Frank Buss <fb@frank-buss.de>
Date: Wed, 2 Jul 2008 10:38:20 +0200
Links: << >>  << T >>  << A >>
Frank Buss wrote:

> If you don't have digital signals, use a digital to analog converter (DAC)
> and take a look at the datasheet of the DAC how to handle the data in your
> FPGA.

Correction: I mean analog to digital converter (ADC).

-- 
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

Article: 133524
Subject: minipci breadboard with fpga
From: manuel-lozano@mixmail.com
Date: Wed, 2 Jul 2008 03:32:07 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi,

I'm looking for a minipci card with an FPGA in order to work for some
project. The PCI interface should be programmed inside the FPGA apart
from other application specific functions.

Unfortunately I have only found standard PCIs

Do anybody know any breadboard mini pci (with or without FPGA) that I
can use as starting point.

Thanks,



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