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Thanks for all the informative replies! The book that I use as a VHDL reference does not go this deeply in the subject of state machines, so I was a little lost. I had a hunch that it was maybe not a good idea... as backhus' response suggested, what I want are not latches, but registers to store values from a few possible MUX'd input sources depending on the state.. I should have been more clear on that. And I think I may have been convinced to try the one clocked process approach.. thankfully I was just finishing up the design of the states and transitions, and haven't gotten too far into writing the code, so I don't have to backtrack too much :)Article: 143876
Hi I have used the chipscope inserter before but I need a design with an ILA and VIO core and the inserter doesnt support the VIO. If someone knows a way of adding the VIO to a inserter design then that would be great. I dont really like having to insert the ILA into the code because of the problem of bringing all the signals out to the top level. I thought there may be an easier way to do it but I guess not. Jon --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 143877
On Oct 28, 8:36=A0pm, "maxascent" <maxasc...@yahoo.co.uk> wrote: > I have a design with some level of hierarchy and I want to connect a > chipscope ILA core to the bottom level. > > For example say I have 3 modules A, B and C with a signal temp in C. > Module A is the top level with B inside A and C inside B. > I would of thought that I could just do the following > > chipscope_ila U_ila( > =A0 =A0.CLK =A0 =A0 (clk), > =A0 =A0.CONTROL (control), > =A0 =A0.TRIG0 =A0 (A.B.C.temp)); > > The ila is in the top level and I want to monitor temp. > When I try and synthesize it with Synplify the program just errors. > Can anyone tell me what I am ddoing wrong? > > Thanks > > Jon =A0 =A0 =A0 =A0 Jon, if all the signals you wish to monitor are inside the module C, than it is easier to place both ICON and ILA inside that module and just pass "temp" to ILA. If you wish to monitor signals from other modules and perhaps the top level, the best solution (as suggested by others) is to bring them out to the highest level you want to monitor and place ICON and ILA there. I too never use the tools, much faster and easier to do it by hand. Regards, rudiArticle: 143878
Hello, I am involved in a design where in i am using the asynchronous fifo been given in the paper by sun-burst. (http://www.sunburst-design.com/ papers/CummingsSNUG2002SJ_FIFO2.pdf) My only requirement in that design is that i need to make afull_n signal asserted one clock before the wfull signal is asserted, but it has been designed in such a way that both get triggerred @ the same time. It would be really thankfull to let me know what changes I need to do in order to achieve this. Regards,Article: 143879
On Sat, 31 Oct 2009 05:53:04 -0700 (PDT), RSGUPTA wrote: >I am involved in a design where in i am using the asynchronous fifo >been given in the paper by sun-burst. (http://www.sunburst-design.com/ >papers/CummingsSNUG2002SJ_FIFO2.pdf) >My only requirement in that design is that i need to make afull_n >signal asserted one clock before the wfull signal is asserted, but it >has been designed in such a way that both get triggerred @ the same >time. Don't try to modify the asynch FIFO design unless you're feeling exceptionally brave. Instead, add a one-place holding buffer on the input side, in the input clock domain. Use the FIFO in such a way that this holding buffer is normally unused. Now, if the FIFO shows full, you can use that as an "almost full" signal and drop the next input item into your holding buffer, asserting "full" at the same time. As soon as the FIFO goes non-full, transfer the holding buffer's data into the FIFO (making it full once again) and, of course, deassert your "full" status signal. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 143880
The problem with having to insert the ila and icon in the hdl is that you constantly have to bring the signals up to the top level, maybe through many layers. It is easier to use the inserter but if you have a vio core too you cant place it with the inserter. Jon --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 143881
On Oct 31, 10:45=A0am, "maxascent" <maxasc...@yahoo.co.uk> wrote: > The problem with having to insert the ila and icon in the hdl is that you > constantly have to bring the signals up to the top level, maybe through > many layers. It is easier to use the inserter but if you have a vio core > too you cant place it with the inserter. > > Jon =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > This message was sent using the comp.arch.fpga web interface onhttp://www= .FPGARelated.com Here's a rule that might help you in future projects: In every module add a "debug" port 32 bits wide, or some larger width if you think you might need a larger ChipScope width. Every modules instantiating lower level modules would normally bring this to the top using an assign. The lowest modules can assign them to zero until you need them. Then when you need to hook up Chipscope the wires are already there and you can just modify the assigns where you signal sources are. And until connected all of these "wires" are ripped out during synthesis so it doesn't add to the resource requirements. By the way I agree that the ChipScope inserter would be the best way to debug but it is a real pain to find your signals after the design has been translated. I often find that buses are not named consistently for example making it a chore just to find all the bits. Regards, GaborArticle: 143882
On Oct 31, 6:00=A0am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > On Sat, 31 Oct 2009 05:53:04 -0700 (PDT), RSGUPTA wrote: > >I am involved in a design where in i am using the asynchronous fifo > >been given in the paper by sun-burst. (http://www.sunburst-design.com/ > >papers/CummingsSNUG2002SJ_FIFO2.pdf) > >My only requirement in that design is that i need to make afull_n > >signal asserted one clock before the wfull signal is asserted, but it > >has been designed in such a way that both get triggerred @ the same > >time. > > Don't try to modify the asynch FIFO design unless you're > feeling exceptionally brave. =A0Instead, add a one-place holding > buffer on the input side, in the input clock domain. =A0Use the > FIFO in such a way that this holding buffer is normally unused. > Now, if the FIFO shows full, you can use that as an "almost full" > signal and drop the next input item into your holding buffer, > asserting "full" at the same time. =A0As soon as the FIFO goes > non-full, transfer the holding buffer's data into the FIFO > (making it full once again) and, of course, deassert your > "full" status signal. > > -- > Jonathan Bromley, Consultant > In asynchronous FIFOs, precision timing of both edges of Almost Full is impossible. AF is activated by a write operation, and is thus synchronous with the write clock. AF will later be deactivated by a read operation. Since AF is usually viewed in the write clock domain, its deactivation must be transferred from the read domain. This inevitably causes issues with timing uncertainty and even metastability. The trailing edges of all the four status lines (Full, AF, Empty, AE) are inherently "sloppy", since there is no defined phase relationship between the two clocks. (Each status is activated by one clock domain, and deactivated by the other). Proper re-synchronization of the trailing edges causes an uncertainty of several clock periods. The leading edges can be very precise. A more basic question is: Why does the OP consider AF and F to be so critically important? I usually view AF and F as emergency signals, indicating that the FIFO is too small for the job at hand. In general: Asynchronous FIFOs have to straddle two clock domains. They should not be burdened with unrealistic demands on the timing precision of the trailing edges of their status signals. Peter Alfke, still interested in FIFOs.Article: 143883
just released! well there is a nice article about 3 different Audio-dsp boards from Eric Brombaugh as well Antti http://groups.google.com/group/antti-brain/files?hl=enArticle: 143884
On Oct 30, 11:14=A0pm, Brian Drummond <brian_drumm...@btconnect.com>
wrote:
> ... snip ...
>
> for a reasonably large ROM, or a complex function (e.g. function calls ne=
sted 4
> levels deep) XST will take an unbelievably long time to synthesise it. Th=
ere's
> an N^2 algorithm in there somewhere; if it takes 15 minutes for a 1000 el=
ement
> array, it'll take an hour for 2000 elements, 4 hours for 4000, etc...
Is this *still* happening? This has been CRed so many times, and I
know it's been fixed for at least some of the test cases we came up
with internally... if you have some example code that exhibits this in
the latest ISE, and you're willing to share it, let me know and I'll
try to beat the XST team around the head with it again. :-/
-Ben-
Article: 143885On Sun, 1 Nov 2009 09:58:10 -0800 (PST), Ben Jones <benjjuk@gmail.com> wrote: >On Oct 30, 11:14 pm, Brian Drummond <brian_drumm...@btconnect.com> >wrote: >> ... snip ... >> >> for a reasonably large ROM, or a complex function (e.g. function calls nested 4 >> levels deep) XST will take an unbelievably long time to synthesise it. There's >> an N^2 algorithm in there somewhere; if it takes 15 minutes for a 1000 element >> array, it'll take an hour for 2000 elements, 4 hours for 4000, etc... > >Is this *still* happening? This has been CRed so many times, and I >know it's been fixed for at least some of the test cases we came up >with internally... if you have some example code that exhibits this in >the latest ISE, and you're willing to share it, let me know and I'll >try to beat the XST team around the head with it again. :-/ I have been informed by a student employee it's still true in ISE11.1 but haven't verified it myself. Will check in the next couple of days and email you privately. Alternatively you may be able to access a pathological testcase attached to Webcase 717144, as used by above student. It asserts on every LUT entry, so you can watch it slow down... (and no, the assert is not the performance bottleneck!) - BrianArticle: 143886
On Oct 30, 10:53=A0pm, Gabor <ga...@alacron.com> wrote: > On Oct 30, 7:38=A0am, John Adair <g...@enterpoint.co.uk> wrote: > > > > > > > Did you buffer the drive to the LED. If not this a common issue for > > DONE not making the correct logic level. Double check with the JTAG > > status to be sure. > > > John Adair > > Enterpoint Ltd. > > > On 30 Oct, 01:29, crescent <hanpei...@gmail.com> wrote: > > > > On Oct 30, 1:57=A0am, John Adair <g...@enterpoint.co.uk> wrote: > > > > > Have you checked that your DONE signal has gone high thereby releas= ing > > > > the chip out of config and into operation. Use the JTAG to do a sta= tus > > > > read if you don't have access to the signal. > > > > > John Adair > > > > Enterpoint Ltd. - Home of Merrick1. The ASIC Prototype Platform. > > > > - Show quoted text - > > > > John, > > > Thank you for your reply. The signal DONE on my board drives a LED > > > through a > > > buffer. After FPGA successfully configured, the LED should light whic= h > > > is not seen > > > when programming from flash. That's to say the FPGA is under > > > configuration all the > > > time. > > Other things to check: > > 1) Atmel Dataflash has a slightly different command set than > most SPI flash parts. =A0Be sure you have the right command > for continuous array read. > > 2) If you think it's a startup issue rather than loading, you > can enable the "internal Done pipe" in the bitgen options. > > Regards, > Gabor- Hide quoted text - > > - Show quoted text - I checked the signals again, find out that there is a glitch in the middle of the two '1's in the MOSI output 001100000.... when FS[2:0] =3D111. Then, I change FS[2:0] to '101' in whicn mode the MOSI should output 0000001100...but it turns out to be 001000... So, I doubt the clock signal is 2x slower than the original clock signal. Is there any chance this would happen?Article: 143887
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Content-Type: text/plain;
charset="gb2312"
Content-Transfer-Encoding: quoted-printable
hi,
i have built a project in edk ,because my application project is very =
big,when generating linker script ,i put big sections into ddr.then,i =
download the .elf file into the borad,it works well and displays the =
results through rs232.
then,in xps,i want it to generate an ise file as a too module in ise =
project.in the project options--export to project navigator ,it generate =
a system.ise file.then ,synthesis etg.i download the .bit,.bmm,and =
my_project.elf into the borad ,but it does not display the =
results.however,i download .bit,.bmm and TestApp_Memory.elf(linker =
script in bram) files to the borad ,it works well.
so ,what the problem occurs to?? i face the problem all the time.
who can tell me? thanks in advance.
------=_NextPart_000_003B_01CA5BCA.A0409970
Content-Type: text/html;
charset="gb2312"
Content-Transfer-Encoding: quoted-printable
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<META http-equiv=3DContent-Type content=3D"text/html; charset=3Dgb2312">
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<BODY bgColor=3D#cce8cf>
<DIV><FONT size=3D2>hi,<BR> i have built a project in edk =
,because my=20
application project is very big,when generating linker script ,i put big =
sections into ddr.then,i download the .elf file into the borad,it works =
well and=20
displays the results through rs232.<BR> then,in xps,i want =
it to=20
generate an ise file as a too module in ise project.in the project=20
options--export to project navigator ,it generate a system.ise file.then =
,synthesis etg.i download the .bit,.bmm,and my_project.elf into the =
borad ,but=20
it does not display the results.however,i download .bit,.bmm and=20
TestApp_Memory.elf(linker script in bram) files to the borad ,it works=20
well.<BR> so ,what the problem occurs to?? i face the =
problem=20
all the time.<BR> who can tell me? thanks in=20
advance.</FONT></DIV></BODY></HTML>
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Article: 143888
hi,
i have built a project in edk ,because my application project is very
big,when generating linker script ,i put big sections into ddr.then,i
download the .elf file into the borad,it works well and displays the results
through rs232.
then,in xps,i want it to generate an ise file as a too module in ise
project.in the project options--export to project navigator ,it generate a
system.ise file.then ,synthesis etg.i download the .bit,.bmm,and
my_project.elf into the borad ,but it does not display the results.however,i
download .bit,.bmm and TestApp_Memory.elf(linker script in bram) files to
the borad ,it works well.
so ,what the problem occurs to?? i face the problem all the time.
who can tell me? thanks in advance.
Article: 143889"Antti" <antti.lukats@googlemail.com> wrote in message news:425235a9-b8ac-49fc-8123-be04446d12ca@r24g2000yqd.googlegroups.com... > just released! > > well there is a nice article about 3 different Audio-dsp boards from > Eric Brombaugh as well > > > Antti > http://groups.google.com/group/antti-brain/files?hl=en Hello Antti, Tried to look at it but Acrobat says the file is damaged and can't be repaired. I downloaded it a few times. Michael KellettArticle: 143890
Hi,
I was wonderring what this template of SystemC code would be, if
written in RTL for Synthesis:
********* Code Snippet 1 ***********
if (condition 1 == true) {
rd_ptr++;
status = "001";
}
else {
wait();
}
*********************************
********* Code Snippet 2 ***********
if (condition 1 == true) {
rd_ptr++;
while (a== false){
wait();
}
}
else {
wait();
}
*********************************
Both the process are sensitive to clk
Article: 143891On Nov 2, 12:12=A0pm, "MK" <m...@nospam.please> wrote: > "Antti" <antti.luk...@googlemail.com> wrote in message > > news:425235a9-b8ac-49fc-8123-be04446d12ca@r24g2000yqd.googlegroups.com... > > > just released! > > > well there is a nice article about 3 different Audio-dsp boards from > > Eric Brombaugh as well > > > Antti > >http://groups.google.com/group/antti-brain/files?hl=3Den > > Hello Antti, > > Tried to look at it but Acrobat says the file is damaged and can't be > repaired. I downloaded it a few times. > > Michael Kellett weird, i just downloaded myself, and the file is ok size on disk 4,36 MB (4=A0579=A0328 bytes) AnttiArticle: 143892
MK wrote: > Tried to look at it but Acrobat says the file is damaged and can't be > repaired. I downloaded it a few times. Works for me. Maybe try right click and "save as", then open the PDF, not within the browser, sometimes Acrobat Reader has problems when loading it from within a web browser. BTW: the W7100 microcontroller sounds interesting: 64 kB flash, 64 kB SRAM, 32 IO ports and TCP/IP for $6.40 ( http://tinyurl.com/yev4vzy ). -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 143893
Antti wrote: > just released! > > well there is a nice article about 3 different Audio-dsp boards from > Eric Brombaugh as well > > > Antti > http://groups.google.com/group/antti-brain/files?hl=en Not very FPGA related, but I like it, some interesting ideas. Maybe next time post it to sci.electronics.basics :-) The magnetic pendulum idea sounds interesting. Do you think it would be possible to build something similar with only one coil for hovering things like this: http://www.paramountzone.com/globe.htm ? -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 143894
hello,all
i have built an edk project(based microblaze) . Because my
application c code is very big,when generating linker script ,i put some
big sections into the ddr and others into bram in microblaze.finally,it
displays the results through rs232.
for now,i want to try to import the EDK Project with microblaze as
Sub-system into a ISE project and i use the cammand h "export to project
navigator",then it generate a system.ise file.but,when i put the
system_stub.bit,system_stub_bd.bmm and my_project.elf(software bits) files
into the board ,it does not work well.
however,if i replace the my_project.elf to TestApp_Memory.elf
(linking script in bram not ddr),it works well.
who can tell me the reasnon ? what can i should do?thank you very
much..
Article: 143895On Nov 2, 1:30=A0pm, Frank Buss <f...@frank-buss.de> wrote: > Antti wrote: > > just released! > > > well there is a nice article about 3 different Audio-dsp boards from > > Eric Brombaugh as well > > > Antti > >http://groups.google.com/group/antti-brain/files?hl=3Den > > Not very FPGA related, but I like it, some interesting ideas. Maybe next > time post it to sci.electronics.basics :-) > > The magnetic pendulum idea sounds interesting. Do you think it would be > possible to build something similar with only one coil for hovering thing= s > like this:http://www.paramountzone.com/globe.htm? > > -- > Frank Buss, f...@frank-buss.dehttp://www.frank-buss.de,http://www.it4-sys= tems.de eh, I think I have enough FPGA related in the previous issues, well the u2tool inside is an FPGA, but i had no time to explain the inner life in more detail in october issue the "hovering" humm, i guess it could be done so that "one coil" just lifts up some metal part and balances it, it should be possible to measure and compensate with one coil only rotation would however need more than one coil for sure AnttiArticle: 143896
I'm trying to create a ring oscillator for my FPGA design but I've run into some problems. Namely, it doesn't seem like any oscillation is occurring. I've hooked up the output signal to LEDs and the serial port, but neither of these shows any oscillations. A few things I think might be happening is that the oscillation is so fast I just can't see it, the oscillation is too fast for the board, it's getting optimized out during synthesis, or (probably) my Verilog file is implemented incorrectly. Can you help me with this? See below for the Verilog modules I'm using. module ringoscillator( input wire stop, output wire out ); wire connector; wire w1, w2, w3, w4; nandgate inputGate(.i1(stop), .i2(connector), .out(w1)); invertergate inv1(.in(w1), .out(w2)); invertergate inv2(.in(w2), .out(w3)); invertergate inv3(.in(w3), .out(w4)); invertergate inv4(.in(w4), .out(connector)); assign out = connector; endmodule module nandgate( input wire i1, i2, output wire out); assign out = ~(i1 & i2); endmodule module invertergate( input wire in, output wire out); assign out = ~in; endmodule Thanks for any help!Article: 143897
On Nov 2, 4:20=A0pm, Sam Kerr <stk...@purdue.edu> wrote: > I'm trying to create a ring oscillator for my FPGA design but I've run > into some problems. Namely, it doesn't seem like any oscillation is > occurring. I've hooked up the output signal to LEDs and the serial port, > but neither of these shows any oscillations. > > A few things I think might be happening is that the oscillation is so fas= t > I just can't see it, the oscillation is too fast for the board, it's > getting optimized out during synthesis, or (probably) my Verilog file is > implemented incorrectly. > > Can you help me with this? See below for the Verilog modules I'm using. > > module ringoscillator( > input wire stop, > output wire out > ); > > wire connector; > wire w1, w2, w3, w4; > > nandgate inputGate(.i1(stop), .i2(connector), .out(w1)); > invertergate inv1(.in(w1), .out(w2)); > invertergate inv2(.in(w2), .out(w3)); > invertergate inv3(.in(w3), .out(w4)); > invertergate inv4(.in(w4), .out(connector)); > > assign out =3D connector; > > endmodule > > module nandgate( > input wire i1, i2, > output wire out); > > assign out =3D ~(i1 & i2); > endmodule > > module invertergate( > input wire in, > output wire out); > > assign out =3D ~in; > endmodule > > Thanks for any help! looks xilinx examples if you dont get it working yourself there are many ways of doing ring oscillators some work too se sk freq meter ref design includes ring osc AnttiArticle: 143898
Sam, Most synthesis tools optimize out any unnecessary logic, so the synthesis tool will look at your code, and remove all but one inverter. It will then either not oscillate (not enough delay), or it will oscillate so fast, you will be unable to see anything on an IO pin. Read through the synthesis manual, and you will find attributes like "keep" and "save" which direct the tools to not rip things out (you really wanted to do something that obvious). The place and route tools also optimize, so this also may be happening after synthesis. AustinArticle: 143899
On Nov 2, 9:20=A0am, Sam Kerr <stk...@purdue.edu> wrote: > I'm trying to create a ring oscillator for my FPGA design but I've run > into some problems. Namely, it doesn't seem like any oscillation is > occurring. I've hooked up the output signal to LEDs and the serial port, > but neither of these shows any oscillations. > > A few things I think might be happening is that the oscillation is so fas= t > I just can't see it, the oscillation is too fast for the board, it's > getting optimized out during synthesis, or (probably) my Verilog file is > implemented incorrectly. > > Can you help me with this? See below for the Verilog modules I'm using. > > module ringoscillator( > input wire stop, > output wire out > ); > > wire connector; > wire w1, w2, w3, w4; > > nandgate inputGate(.i1(stop), .i2(connector), .out(w1)); > invertergate inv1(.in(w1), .out(w2)); > invertergate inv2(.in(w2), .out(w3)); > invertergate inv3(.in(w3), .out(w4)); > invertergate inv4(.in(w4), .out(connector)); > > assign out =3D connector; > > endmodule > > module nandgate( > input wire i1, i2, > output wire out); > > assign out =3D ~(i1 & i2); > endmodule > > module invertergate( > input wire in, > output wire out); > > assign out =3D ~in; > endmodule > > Thanks for any help! I'm not sure this works on wires as well as regs, but try: (* KEEP =3D "TRUE" *) wire connector; // This wire should be kept anyway (* KEEP =3D "TRUE" *) wire w1, w2, w3, w4; // Some of these would get ripped out Older versions of XST would not keep simple gates. The brute force method is to take out and dust off the old libraries guide and instantiate a LUT with the appropriate INIT functions for your gates. However I think that if you're using a relatively recent version of XST the KEEP attribute should do the trick. Regards, Gabor
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