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Messages from 144450

Article: 144450
Subject: Cheapest way to get a chipscope compatible cable?
From: "dlopez" <d@designgame.ca>
Date: Tue, 08 Dec 2009 14:35:37 -0600
Links: << >>  << T >>  << A >>
Hi,
It seems like Chipscope only supports the original Xilinx cable...no other
JTAG cable would work. Anyone knows if there is a way to obtain one for
less than the very high 250$ they ask for?

Thanks,

Diego	   
					
---------------------------------------		
This message was sent using the comp.arch.fpga web interface on
http://www.FPGARelated.com

Article: 144451
Subject: Re: Cheapest way to get a chipscope compatible cable?
From: "Andrew Holme" <ah@nospam.co.uk>
Date: Tue, 8 Dec 2009 21:31:55 -0000
Links: << >>  << T >>  << A >>

"dlopez" <d@designgame.ca> wrote in message 
news:XJadnTyZCM4EJYPWnZ2dnUVZ_gSdnZ2d@giganews.com...
> Hi,
> It seems like Chipscope only supports the original Xilinx cable...no other
> JTAG cable would work. Anyone knows if there is a way to obtain one for
> less than the very high 250$ they ask for?

I've got one of these:

http://www.absolute-data-services.co.uk/xilinx_platform_usb_cable.htm




Article: 144452
Subject: Re: Cheapest way to get a chipscope compatible cable?
From: John Adair <g1@enterpoint.co.uk>
Date: Tue, 8 Dec 2009 14:43:05 -0800 (PST)
Links: << >>  << T >>  << A >>
A number of parallel port based cables, like our Prog2 cable, will
work for Chipscope/Impact tools. USB solutions are not readily
available as yet unless you are a student where there is an option for
a cheaper cable. We may offer something of a solution in a little
while but remains to be debugged as yet.

John Adair
Enterpoint Ltd.


On 8 Dec, 20:35, "dlopez" <d...@designgame.ca> wrote:
> Hi,
> It seems like Chipscope only supports the original Xilinx cable...no othe=
r
> JTAG cable would work. Anyone knows if there is a way to obtain one for
> less than the very high 250$ they ask for?
>
> Thanks,
>
> Diego =A0 =A0 =A0
>
> --------------------------------------- =A0 =A0 =A0 =A0
> This message was sent using the comp.arch.fpga web interface onhttp://www=
.FPGARelated.com


Article: 144453
Subject: Re: Cheapest way to get a chipscope compatible cable?
From: "dlopez" <d@designgame.ca>
Date: Tue, 08 Dec 2009 17:01:30 -0600
Links: << >>  << T >>  << A >>
>A number of parallel port based cables, like our Prog2 cable, will
>work for Chipscope/Impact tools. USB solutions are not readily
>available as yet unless you are a student where there is an option for
>a cheaper cable. We may offer something of a solution in a little
>while but remains to be debugged as yet.
>
>John Adair
>Enterpoint Ltd.
>
>

Thanks for the reply,
I am a Student, but I couldn't find anything on the Xilinx website about
discounts...could you elaborate more?

I would definitely prefer a USB solution.

Thanks,
Diego	   
					
---------------------------------------		
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Article: 144454
Subject: Re: A new approach to FPGA and PCB System Development Platform, Santa
From: Andy Peters <google@latke.net>
Date: Tue, 8 Dec 2009 15:10:57 -0800 (PST)
Links: << >>  << T >>  << A >>
On Dec 3, 10:36=A0pm, Antti <antti.luk...@googlemail.com> wrote:
> On Dec 4, 2:09=A0am, Andy Peters <goo...@latke.net> wrote:
>
> > On Dec 3, 3:01=A0pm, Vikram <vkr...@gmail.com> wrote:
>
> > > Announcing a Seminar on A New Approach - An FPGA and PCB System
> > > Development Platform, Santa Clara, CA, USA (By Altium) - Dec'10
>
> > > #2 FPGA Design & Instant Prototyping
> > > Learn how to design complex FPGA's with an embedded processor utlizin=
g
> > > block based IP and quickly debug your design in a NanoBoard with
> > > virtual instrumentation.
>
> > FPGA design using a PCB layout tool is a recipe for disaster.
>
> > -a
>
> Altium Designer is NOT a PCB layotool.

Oh, then how is it possible that I'm doing a board-level schematic in
it right now, which will then be handed off to my layout guy so he can
do that task, also in AD?

-a

Article: 144455
Subject: FPGA kit
From: Jack <jayeshpparmar@gmail.com>
Date: Tue, 8 Dec 2009 22:55:32 -0800 (PST)
Links: << >>  << T >>  << A >>
Hi all,

I want to buy a XILINX FPGA Kit and an ALTERA CPLD kit.
would you please suggest some kits.

On internet the displayed price $189 includes kit accessories(Cables,
cds...) or i have to buy them separately. Also which accessories are
required?

Thanx


Article: 144456
Subject: Re: Cheapest way to get a chipscope compatible cable?
From: John Adair <g1@enterpoint.co.uk>
Date: Tue, 8 Dec 2009 23:47:13 -0800 (PST)
Links: << >>  << T >>  << A >>
For students http://www.digilentinc.com/Products/Detail.cfm?NavPath=3D2,395=
,716&Prod=3DXUP-USB-JTAG.
I have not used this myself but Digilent have had access to the Xilinx
programming circuit for some years so I would not expect any major
problems. Our solution will be something similar and will ship with
our development boards as an optional extra.

John Adair
Enterpoint Ltd. - Home of Drigmorn2. The Embedded FPGA Board.

On 8 Dec, 23:01, "dlopez" <d...@designgame.ca> wrote:
> >A number of parallel port based cables, like our Prog2 cable, will
> >work for Chipscope/Impact tools. USB solutions are not readily
> >available as yet unless you are a student where there is an option for
> >a cheaper cable. We may offer something of a solution in a little
> >while but remains to be debugged as yet.
>
> >John Adair
> >Enterpoint Ltd.
>
> Thanks for the reply,
> I am a Student, but I couldn't find anything on the Xilinx website about
> discounts...could you elaborate more?
>
> I would definitely prefer a USB solution.
>
> Thanks,
> Diego =A0 =A0 =A0
>
> --------------------------------------- =A0 =A0 =A0 =A0
> This message was sent using the comp.arch.fpga web interface onhttp://www=
.FPGARelated.com


Article: 144457
Subject: Re: Cheapest way to get a chipscope compatible cable?
From: Petter Gustad <newsmailcomp6@gustad.com>
Date: Wed, 09 Dec 2009 10:04:39 +0100
Links: << >>  << T >>  << A >>
John Adair <g1@enterpoint.co.uk> writes:

> A number of parallel port based cables, like our Prog2 cable, will
> work for Chipscope/Impact tools. USB solutions are not readily

Is the ChipScope/Impact software interface documented? Is there a way
I can write a plug-in for my programmer so that it will work with my
own programmer?

Petter
-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 144458
Subject: Multiport BRAM for custom CPUs
From: "de4" <de4@poczta.onet.pl>
Date: Wed, 09 Dec 2009 03:30:09 -0600
Links: << >>  << T >>  << A >>
Hello,

I hope my question won't be naive or stupid or repeaded 100 times. I wanted
to ask if there is possibility of creating RAM using FPGA BlockRam that
have for example 8 read ports. I asking because I'm creating simple
multicore processor and I've got problems with performace. Memory with
single port is big bottle neck for 8 cores unfortunetly. It would be great
to have RAM based on BRAM that I can read simultanusly on 8 diffrent
address and can initialize using coe file.
Other way is to create cache for each core but I imagine this as more
difficult...

Thank you for help and sorry for my poor english.	   
					
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Article: 144459
Subject: Re: Multiport BRAM for custom CPUs
From: Jon Beniston <jon@beniston.com>
Date: Wed, 9 Dec 2009 01:34:21 -0800 (PST)
Links: << >>  << T >>  << A >>
How many write ports do you need?

Article: 144460
Subject: Re: FPGA kit
From: John Adair <g1@enterpoint.co.uk>
Date: Wed, 9 Dec 2009 01:48:11 -0800 (PST)
Links: << >>  << T >>  << A >>
You have not said what you application is so I have made the
assumption that it's the lower end. We have a wide range from CPLD
boards to our monster Merrick1 with it's 101 FPGAs.

I will start with our Polmaddie family. Polmaddie2-5 are in
manufacture and will be available in January.

Polmaddie2, http://www.enterpoint.co.uk/cpld_boards/polmaddie2.html,
is based on a Altera MAX3128.

Polmaddie3, http://www.enterpoint.co.uk/cpld_boards/polmaddie3.html,
is based on a Xilinx XC3S50AN.

Polmaddie2/3 will come with parallel port programming cable and one
off prices are GBP 40 / USD 68.

Moving up the FPGA size our Drigmorn2 and Drigmorn3 are worth
considering. Links to these boards form http://www.enterpoint.co.uk/boardproducts.html.
For non-OEM sales these come with a parallel port cable. Drigmorn2/3
should hopefully be on our shop site later this week. Watch out for
the free shipping and clearance offers that are coming on the shop.

ISE Webpack and the Quartus equivalent are free to download from
Xilinx and Altera respectively and contain the basic tools to do
designs.

John Adair
Enterpoint Ltd.

On 9 Dec, 06:55, Jack <jayeshppar...@gmail.com> wrote:
> Hi all,
>
> I want to buy a XILINX FPGA Kit and an ALTERA CPLD kit.
> would you please suggest some kits.
>
> On internet the displayed price $189 includes kit accessories(Cables,
> cds...) or i have to buy them separately. Also which accessories are
> required?
>
> Thanx


Article: 144461
Subject: Re: Multiport BRAM for custom CPUs
From: "de4" <de4@poczta.onet.pl>
Date: Wed, 09 Dec 2009 04:15:59 -0600
Links: << >>  << T >>  << A >>
>How many write ports do you need?
>
Only one write port and eight read ports.
Write ports are not a problem because i've memory controller based on
priority and with writing I'm very careful because I'm afraid of unintend
overwriting data be many cores... I just wanted to speed up fetching
instruction and data from memory that is shared by many processor cores.

By the way thank you for reply...	   
					
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Article: 144462
Subject: Re: Multiport BRAM for custom CPUs
From: "Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk>
Date: Wed, 9 Dec 2009 10:59:47 -0000
Links: << >>  << T >>  << A >>
> Only one write port and eight read ports.
> Write ports are not a problem because i've memory controller based on
> priority and with writing I'm very careful because I'm afraid of unintend
> overwriting data be many cores... I just wanted to speed up fetching
> instruction and data from memory that is shared by many processor cores.


Why don't you just write the same thing to 8 (or 4) different RAMS?


Nial.



Article: 144463
Subject: Re: Xilinx's version of Quartus' Signaltap?
From: Martin Thompson <martin.j.thompson@trw.com>
Date: Wed, 09 Dec 2009 11:48:32 +0000
Links: << >>  << T >>  << A >>
Andy Peters <google@latke.net> writes:

> On Dec 7, 6:26am, Martin Thompson <martin.j.thomp...@trw.com> wrote:
>> laserbeak43 <laserbea...@gmail.com> writes:
>> > Hello,
>> >   I've just been shown Signaltap, A feature in Quartus Webpack
>> > Edition. Does the Webpack Edition of ISE have this feature? WOW this
>> > alone can convince me to use Altera products.
>>
>> Chipscope is the Xilinx equivalent - it's not in webpack (personally, I
>> think that's a mistake on Xilinx's part)
>>
>> But comparing it to Signaltap may (IMHO) leave you underwhelmed... it's
>> very disjointed and unintegrated in comparison. I'm still using FPGA
>> editor to change which signals to monitor, then having to update the
>> viewer by hand! V. tedious.
>
> Really? What version of ChipScope are you using?

10.1.3

>
> Use the ChipScope Core Inserter. 

Indeed, I could (and have in the past), but 

a) I'm using the EDK variety of core inserter, as it manages the JTAG
linkages with the microblaze debug module for me 

b) I then have to run MAP, PAR, bitgen again.

> All of the signals and elements of
> the design are shown in it, and you simply choose the signals to
> monitor. After you close the Inserter, go back to ISE, and re-fit.

Re-fit - 10s of minutes.

> From the ChipScope viewer, you can reconfigure the FPGA, then do an
> "Import" which lets you bring in the names of all of the signals you
> selected from the ChipScope Core Inserter project file.
>
> No need to go into the FPGA editor at all!

FPGAeditor, regenerate bitstream, 10s of seconds...  Then click "write
CDC" button, import the result into the analyser.  Still tedious :)

As I recall my experience with SignalTap (which was a while ago
admittedly) I could select a signal from a dropdown list *in the
Analyser* and it would do the tedious hacking that I currently do in
FPGAed, regen the bitstream and upload it for me.

Under some circumstances, it would redo a fit at that point, which was
irritating, but at least I was able to do it all from the analyzer GUI,
which was then always in sync with the FPGA.

[Followups set to comp.arch.fpga, as it's not very Veriloggy]

Cheers,
Martin

Crosspost & Followup-To: comp.arch.fpga
-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

Article: 144464
Subject: Re: Multiport BRAM for custom CPUs
From: "de4" <de4@poczta.onet.pl>
Date: Wed, 09 Dec 2009 06:21:21 -0600
Links: << >>  << T >>  << A >>
>> Only one write port and eight read ports.
>> Write ports are not a problem because i've memory controller based on
>> priority and with writing I'm very careful because I'm afraid of
unintend
>> overwriting data be many cores... I just wanted to speed up fetching
>> instruction and data from memory that is shared by many processor
cores.
>
>
>Why don't you just write the same thing to 8 (or 4) different RAMS?
>
>
>Nial.
>
>
>

hmmm that is not bad idea. I'm only a beginner and this solution didn't
come to my instantly... Thank you very much - that is what I needed quick
solution

OK only last question in this thread : Is there a possibility to update
Memory Init Vector in already generated BitStream file with out using
Xilinx GUI.

	   
					
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Article: 144465
Subject: Measure accurate time with a 50MHz FPGA - what are the limits?
From: "fab." <fabrizio.tappero@gmail.com>
Date: Wed, 9 Dec 2009 04:27:11 -0800 (PST)
Links: << >>  << T >>  << A >>
Hello,
I have a maybe quite simple question (simple for who knows the
answer...) about time measurement.

I have a Spartan 3 FPGA clocked at 50 MHz. I have two events (rising
edge) happening on two different pins, about 100 us ~ 300 us  apart.
I'd like to perform a time measurement (using the FPGA clock) on that
time interval with an accuracy that is higher than 1/(50E6) s. Is it
possible? Can somebody please redirect me to some docs/examples about
it.

Thank you in advance,
Fabrizio

Article: 144466
Subject: Re: Measure accurate time with a 50MHz FPGA - what are the limits?
From: Symon <symon_brewer@hotmail.com>
Date: Wed, 09 Dec 2009 12:36:09 +0000
Links: << >>  << T >>  << A >>
fab. wrote:
> 
> I have a Spartan 3 FPGA clocked at 50 MHz. I have two events (rising
> edge) happening on two different pins, about 100 us ~ 300 us  apart.
> I'd like to perform a time measurement (using the FPGA clock) on that
> time interval with an accuracy that is higher than 1/(50E6) s. Is it
> possible? Can somebody please redirect me to some docs/examples about
> it.
> 
> Thank you in advance,
> Fabrizio

Use a DCM to make a 60MHz clock. Then you can measure with a resolution 
of 1/(60E6) s.  1/60e6 < 1/50e6.

HTH, Syms.

Article: 144467
Subject: Re: very wide counter (42-bit)
From: "kendor" <jonas.reber@bfh.ch>
Date: Wed, 09 Dec 2009 06:40:43 -0600
Links: << >>  << T >>  << A >>
>I hope your comment on the declaration of WD is not what you really
>wanted...
>
>Also, en='0' disables the cnt increment, but not the prescaler (temp),
>which will lead to problems if en is disabled at the wrong time or for
>long enough.
>
>Depending on how much latency you can tolerate (other posts regarding
>register retiming/rebalancing), you may want to register the output of
>the prescaler comparison, so that it's logic path does not add to the
>counter path.
>
>Andy
>

thank you all for your follow ups!

In the comment I certainly mean prescaler - not divider ;)

I am using timespecs for high and low time - ISE11 manages to do its job
(however I have to increase its effort, which leads to quite some
processing time (30'+))
I believe to add a pipeline would be a good idea. I'm processing 4*1024
multiplexed signals and for each signal I have 10 clock cycles for my
algorithm to pass (I always switch between single incoming signals and then
to the processing and wait again for the next time the same signal is
selected... around 100us). Since I use the countervalue right from the
beginning I would need to increase the countertime at the time I switch to
the new signal. At the moment the data path needs 8 out of those 10 clock
cycles. So there's not a lot of margin to add in another pipeline stage
without having to add those in the whole algorithm (which works with
feedbacks and loops of different delays) - so I'd prefer to have the easy
way :)

I didn't think of the "from : to style timing constraint" since I was not
wanting to add 42 of those. But I'll give this a try.
Registering the prescaler comparison sounds good to.

Thanks!



	   
					
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Article: 144468
Subject: Re: Multiport BRAM for custom CPUs
From: John McCaskill <jhmccaskill@gmail.com>
Date: Wed, 9 Dec 2009 04:41:51 -0800 (PST)
Links: << >>  << T >>  << A >>
On Dec 9, 6:21=A0am, "de4" <d...@poczta.onet.pl> wrote:
> >> Only one write port and eight read ports.
> >> Write ports are not a problem because i've memory controller based on
> >> priority and with writing I'm very careful because I'm afraid of
> unintend
> >> overwriting data be many cores... I just wanted to speed up fetching
> >> instruction and data from memory that is shared by many processor
> cores.
>
> >Why don't you just write the same thing to 8 (or 4) different RAMS?
>
> >Nial.
>
> hmmm that is not bad idea. I'm only a beginner and this solution didn't
> come to my instantly... Thank you very much - that is what I needed quick
> solution
>
> OK only last question in this thread : Is there a possibility to update
> Memory Init Vector in already generated BitStream file with out using
> Xilinx GUI.
>
> --------------------------------------- =A0 =A0 =A0 =A0
> This message was sent using the comp.arch.fpga web interface onhttp://www=
.FPGARelated.com

There is a program named Data2MEM that can take a data file and insert
it into the FPGA bitstream without having to reroute the design.

See the Data2MEM Users Guide, AKA UG658, for more details. You can get
to it through the ISE help menu.

Regards,

John McCaskill
www.FasterTechnology.com

Article: 144469
Subject: Re: Possible memory leak in xst in ISE 11.3
From: Benjamin Couillard <benjamin.couillard@gmail.com>
Date: Wed, 9 Dec 2009 06:17:45 -0800 (PST)
Links: << >>  << T >>  << A >>
Thanks, I upgraded to 11.4 and it solved my problem.

On 8 d=E9c, 15:00, "MM" <mb...@yahoo.com> wrote:
> I had a webcase on this issue. My design failed in Win32 but synthesized
> fine in 64-bit Linux. Supposedly the problem was fixed in 11.4, which is =
now
> available for download. It is a huge download as usual, so it won't be un=
til
> tomorrow when I can try if it actually works.
>
> /Mikhail
>
> "Benjamin Couillard" <benjamin.couill...@gmail.com> wrote in message
>
> news:cb32d393-d872-47dd-9a7a-84a086442217@m3g2000yqf.googlegroups.com...
>
>
>
> > Hi everyone,
>
> > I updated to ISE 11.3 recently and I noticed that memory consumption
> > for xst.exe during synthesis is really high (more than 2.5 gigs for
> > me). I use vista professional 64-bit. Memory usage is so high that I
> > can't use any other application (I have 3 gigs in all). Plus synthesis
> > seems slower, so is it possible that there is some kind of memory
> > leak? =A0Am I the only one that has this problem?
>
> > Best regards


Article: 144470
Subject: Re: Measure accurate time with a 50MHz FPGA - what are the limits?
From: Gabor <gabor@alacron.com>
Date: Wed, 9 Dec 2009 06:27:04 -0800 (PST)
Links: << >>  << T >>  << A >>
On Dec 9, 7:36=A0am, Symon <symon_bre...@hotmail.com> wrote:
> fab. wrote:
>
> > I have a Spartan 3 FPGA clocked at 50 MHz. I have two events (rising
> > edge) happening on two different pins, about 100 us ~ 300 us =A0apart.
> > I'd like to perform a time measurement (using the FPGA clock) on that
> > time interval with an accuracy that is higher than 1/(50E6) s. Is it
> > possible? Can somebody please redirect me to some docs/examples about
> > it.
>
> > Thank you in advance,
> > Fabrizio
>
> Use a DCM to make a 60MHz clock. Then you can measure with a resolution
> of 1/(60E6) s. =A01/60e6 < 1/50e6.
>
> HTH, Syms.

Hope that was tongue-in-cheek.  Of course he didn't say
just how much faster he needs to measure.  Twice as fast
as the clock? Use DDR sampling with the existing 50 MHz
clock to get 100 megasamples per second.  4 times as fast?
Generate 4 clock phases using the DCM and sample on all
four.  Much faster?  Take a look at some old Virtex E
appnotes for high-speed LVDS that use carry chain delays
to grab the same input on multiple clock phases.

regards,
Gabor

Article: 144471
Subject: EDK problem
From: "moonlight721" <245298537@qq.com>
Date: Wed, 09 Dec 2009 08:39:23 -0600
Links: << >>  << T >>  << A >>
Hi 

Thanks for the HELP in advance

I use the EDK9.1i to make my design,then I come to the EDK10.1 to update
my 
design, that works half year ago,but for now,it does not work!The
error is “ No license for component <plb_uart16550_v1_00_c> found”
,since I made my design in EDK9.1i thus I used the
“plb_uart16550_v1_00_c”,but it works before,but now it doesn't,
could you help me find out the problem! Is it the plb_uart16550_v1_00_c
cann't use in EDK10.1 anymore? Or the other reason?
my board is Virtex II pro 30

Thanks again



Article: 144472
Subject: Spartan 3E starter Kit
From: "thranduil" <vlasinac@gmail.com>
Date: Wed, 09 Dec 2009 08:39:34 -0600
Links: << >>  << T >>  << A >>
Hello,
i want to buy Spartan 3E starter kit and I am wonder if someone managed to
make it works like a standard USB device.

Thank you



Article: 144473
Subject: Re: Problems reading from PHY registers using plb_temac and
From: Bob <rsg.uclinux@gmail.com>
Date: Wed, 9 Dec 2009 06:58:12 -0800 (PST)
Links: << >>  << T >>  << A >>
Hi Mikhail - thanks for your response.

I don't think it is software because the high-level code is the same,
unless it is in the Xilinx low-level code, which looks fine.

Also, I just added a loop with a one-second delay.  In it, I read and
display the two ID registers, then pause; even after five times
through, I still get the invalid values.  Actually, what appears to
get it to read the ID registers correctly is the code to reset the PHY
by setting bit 15 in the control register; after this, the ID
registers work correctly, as do many of the others, but not the
register that controls the crossover feature!

I'm starting to wonder about how the PHY is reset.  I don't have any
physical access to that signal, so I cannot view it on a scope.  But
the PHY data sheet states it must be at least 10 ms long, and remain
active for at least 10 clock cycles.  Could that be different?

Regards,
-Bob

On Dec 8, 2:58=A0pm, "MM" <mb...@yahoo.com> wrote:
> I have this working in both 8.2 and 10.3. I've never tried 9.1. I suspect
> however that this is a software porblem. Make sure that PHY is not being
> reset when you try to read it the first time. If that's not the case perh=
aps
> the MDIO interface is not reset properly before the first read... If the
> behaviour consistent you could just ignore the first read as a simple
> workaround.
>
> /Mikhail
>
> "Bob" <rsg.ucli...@gmail.com> wrote in message
>
> news:bd19585a-98ee-461f-a18f-8389ba0d3b67@p30g2000vbt.googlegroups.com...
>
> >I am having problems reading from the Ethernet PHY chip on both my
> > custom board and on the Xilinx ml403 board, both of which use the same
> > part (Marvell 88E1111) and design.
>
> > Background: For our custom board, the Ethernet PHY chip incorrectly
> > detects and enables its crossover feature approximately 50% of the
> > time. The solution is to disable this feature, as we have no need for
> > it. =A0However, to do so, I must read and write to the PHY registers.
>
> > Using EDK 11.3i, I can indeed correctly read and write these
> > registers, and implement a software fix. =A0However, this is an old
> > design, and the project is in the "end game". =A0Therefore, there is
> > much resistance to changing the EDK version at this late stage;
> > everything else works, there are a number of custom IP that would need
> > to be updated, and of course, drivers would need to be updated or re-
> > written. =A0So, I've tried the same approach with our existing 9.1i
> > tools, but reading and writing works sporadically.
>
> > The easiest example of the problem are the two PHY ID registers (2 and
> > 3), that should always return the values $0141 and $0cc2 respectively,
> > and that for the 9.1i version, they are both read incorrectly the
> > first time, and then correctly the second time! =A0Specifically, I read
> > 0x0000 and 0x0400 the first time (both incorrect), and later, read
> > 0x0141 and 0x0cc2 (both correct). =A0There are other examples, but this
> > is the most obvious.
>
> > Note that this occurs even when building a design for the ml403, using
> > the Base System Builder.
>
> > I'm thinking some constraints might be needed on the signals of the V4/
> > PHY interface, but I don't know how to specify them. =A0Has anyone an
> > example or a reference to guide me? =A0Or am I missing something else?
>
> > Thanks,
> > -Bob


Article: 144474
Subject: No Reserve Board Sales
From: John Adair <g1@enterpoint.co.uk>
Date: Wed, 9 Dec 2009 09:23:52 -0800 (PST)
Links: << >>  << T >>  << A >>
As it proved popular last time we are again listing boards with minor
faults for sale on ebay. No reserve we just want to clear some space
before we move offices. First board listed is a Darnaw1 - XC3S1200E
verson.

John Adair
Enterpoint Ltd.



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