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In some cases the xilinx programming software cannot reprogram the device if a free running clock is on a pin. Disabling the clock enables reprogramming. MIKE "Jim Raynor" <chris_cheung66@hotmail.com> schrieb im Newsbeitrag news:502T8.42773$Aa4.2105237@news0.telusplanet.net... > Hi, > > > "M. Randelzhofer" <mrandelzhofer@uumail.de> wrote in message > news:afhr7s$qgr$06$1@news.t-online.com... > > Depends on the manufacturer. > > Xilinx 95xx have pullups in the programming state which is default on new > > devices. > > Xilinx recommends to switch off any clocks or fast signals on any pin for > > programming the device. > > In practice this seems to be necessary only for already programmed parts > or > > very full parts. > > So take care in your XC95xx designs if you use a free running clock and > > consider switching off the clock oscillator with an output enable for > device > > programming. > > > > MIKE > > > > I am wondering if what will happen if I don't do that.............. > Please response. > > Thanks > > > > > > > > > "Minlin Fan" <minlinf@hotmail.com> schrieb im Newsbeitrag > > news:3d1ad654$0$27308$afc38c87@news.easynet.co.uk... > > > Hi all, > > > > > > Before being programmed, will a blank CPLD affect the rest of the > circuit > > on > > > a board? What status are all the pins with such a blank CPLD? > > > > > > Cheers. > > > Minlin > > > > > > > > > > > >Article: 44751
Hi, I am working on programming a GAL 16v8 chip. I am using the ALtera Max plus compiler but i was not able to find the equivalent device. Can someone shed some light on this, THanks a lot -SandeepArticle: 44752
Sandeep Unni wrote: > > Hi, > > I am working on programming a GAL 16v8 chip. I am using the ALtera Max > plus compiler but i was not able to find the equivalent device. Can > someone shed some light on this, You cannot find it, because Altera do not make GAL16V8. They used to have 20 pin EP3x0 devices, but no longer. Probably your best bet, is Atmel ATF16V8BQL / ATF16V8CZ devices, and their free WinCUPL tool chain. -jgArticle: 44753
Don't worry. Just change it to anything you want between 3.0 and 5.25 V. Peter Alfke, Xilinx Applications ============================= Joerg Schneide wrote: > Hello, > > is it possible to change the VCCIO (without damage or other negative effects) > in the range of 3.3-5V of a XC9572 when it is powered up? > > thanks, > > Jörg.Article: 44754
"Martin Sauer" <msauer@gmx.net> schrieb im Newsbeitrag news:3D1CCA39.5000604@gmx.net... > Hello, > > > do you know if there any literature which describe the programming of a > Xilinx CoolRunnerII CPLD? I want to program this CPLD with a > Microcontroller via the JTAG interface. Have a look at xapp058, it describes what you want to do. Including C sources. -- MfG FalkArticle: 44755
"Lorenzo Lutti" <lorenzo.lutti@DOHtiscalinet.it> ha scritto nel messaggio news:g43T8.79989$Kt3.1923784@twister2.libero.it... > I implemented a state machine [...] Thank you. -- LorenzoArticle: 44756
> >> There is *no* physical licensing mechanism that might prevent a user from > >> continuing to maintain existing designs in the indefinite future, as long as > >> you need it, as long as you want. No problem! > >I don't mean to offend you or anyone else at Xilinx, but this is a > >pretty silly licensing scheme. > > I think it is a legal liability issue. If they license it for one year > only, you can't come back sue them 5 years later. Yes, and if a customer decides, that he will not pay 2500 Bucks for only one year of usage - thats what the EULA says - and therefore switches to another FPGA Vendor, he will not come back five years later either. And: Maybe customers do not want to a license where Xilinx might come back five years later and sue the customer. (Yes, I know Peter, no intent to do this yada yada... Unisys had no intent in the 70s to sue anybody over the LZW patents. But the times they are a changing...) Also: Xilinx uses the same license in germany where this type of license is clearly against the law. One would believe that a multi billion dollar company would by able to hire lawyers to check there licenses... Kolja SulimmaArticle: 44757
Thats close to the 2 DCM configuration I'd suggesteed, but if you pull the feedbacks out through the IOB's then back into the DCMs then you don't have to make any phase adjustment to the DCM because the potentially unequal external loading is now included in the feedback path and is servoed out while the DCM is locking. Regards Peter Alfke <peter@xilinx.com> wrote in message news:<3D1C8B75.E615B134@xilinx.com>... > Here is an even better answer from one of the Xilinx experts ( who wants to remain > anonymous...) > > I think the best thing to do is : > > CLK--+--DCM-----BUFG---internal clock > | > +--DCM-----BUFG---to FDDRRSE primitive(s) > > The top DCM and BUFG are used for the internal clock. The bottom DCM > and BUFG are used to drive FDDRRSE primitives. Each BUFG feeds back > to it's own DCM. The bottom BUFG can also then be phase-adjusted to > move the clock where he needs it. By connecting the D0 and D1 inputs > to the FDDRRSE primitives to VCC and GND (or vice-versa), you will > get an exact copy of the clock, or it's inverse (180 degree phase > shift). Of course, there will be the clock-to-out delay of the IOB > DDR flop, but that can be adjusted/corrected with the phase shift > of the bottom DCM that drives these IOB flops. > > There will be a slightly better duty cycle if two BUFGs are used > with the bottom DCM -- one for CLK0 and one for CLK180 vs. the > single BUFG method that I described above. > > > > > > > > Peter Alfke wrote: > > > You don't need two DCMs, one is enough. It generates the two phases (0 and 180 ) with > > as good a precision as is possible ( 50 ps resolution). Then you can route these > > signals on two glabal clocks. > > Thiis more accurate than doing local inversion in ths I/O. > > > > Peter Alfke, Xilinx Applications > > ======================== > > JArticle: 44758
Which version of Xilinx software are you using? I am using ISE 4.2i. When I change timing constraints, i.e. ucf file, with an external editor, ISE sometimes do not recognize it, even when I select rerun on the "Implementation" icon. But when I changed the ucf file like what you did, ISE launches Notepad (which sucks of course), and after saving the ucf file a message window pops up to ask for reset implementation. If I select "Reset", the new constraint file will be recognized for sure. I seems quite stupid, but I don't know why. \LC cfk <cfk_alter_ego@pacbell.net> wrote in message news:TSIQ8.6690$ll2.353811755@newssvr21.news.prodigy.com... > I guess this is really a design flow question. I am using ISE and > implementing a PCI interface in a VirtexE. I have now gotten to the stage > where I need to add some timing constraints. The question is, should those > timing constraints be added to the .UCF file under "Design Entry > Utilities>User Constraints>Edit Implementation Constraints File" or some > other file. I have tried using Constraints Editor, somewhat unsuccessfully > to add constraints so maybe part of the issue is I dont really know how to > add them properly. I can add IOSTANDARD's and LOC's with no problem to the > UCF, but now timing has become an issue. As always, any suggestions will be > greatly appreciated. > > Charles > >Article: 44759
If you feel that you want to use an Altera part you could surely impliment your design in one of their 32 macros cell CPLDs such as a 7032 or 3032, both under a $1. Jim Granville <jim.granville@designtools.co.nz> wrote in message news:<3D1D02B0.7EFE@designtools.co.nz>... > Sandeep Unni wrote: > > > > Hi, > > > > I am working on programming a GAL 16v8 chip. I am using the ALtera Max > > plus compiler but i was not able to find the equivalent device. Can > > someone shed some light on this, > > You cannot find it, because Altera do not make GAL16V8. > They used to have 20 pin EP3x0 devices, but no longer. > > Probably your best bet, is Atmel ATF16V8BQL / ATF16V8CZ devices, > and their free WinCUPL tool chain. > > -jgArticle: 44760
If there isn't any, then you may be able to use a logic analyzer to record the sequence, then play back the bitstream using your uC. Martin Sauer <msauer@gmx.net> wrote in message news:<3D1CCA39.5000604@gmx.net>... > Hello, > > > do you know if there any literature which describe the programming of a > Xilinx CoolRunnerII CPLD? I want to program this CPLD with a > Microcontroller via the JTAG interface. > > Thank you for your Answer. > > bye > > martinArticle: 44761
I've had trouble in the past on similar questions with the first tier support folks at vendor A. It seems like they being newbys and getting assigned to the phone bank, combined with FPGA design tools relying mainly on "hold time correct by architecture" means the AE people don't do well on hold time questions. One guy just told me to turn off the message. Take a look at what you are doing with your clocks. If you have something other than every clock pin being driven by the exact same net, then this could be the source of your troubles. If you must use that clocking configuration, I've solved problems like that by forcing offending flop pairs apart (by location constrants) so that the data delay is larger than the clock skew. Regards "Roland Manders" <roland.manders@philips.com> wrote in message news:<3d1b1d7b$0$223$4d4ebb8e@read-nat.news.nl.uu.net>... > Hi, > > I have the following problem. > > After synthesizing a design with leonardo Maxplus is used to place and route > the > design everything functions as it should. > > However using the same *.edf file in Quartus after fitting and performing > timing > analysis the the following message is produced: > > ->Warning: Circuit may not operate. 1629 non-operational path(s) clocked by > clock clk have clock skew larger than the data delay. See the Compilation > Report for details. > > I have tried the solution as Altera has given with setting the LPM memories > used to a REGISTERED data in (it was already set to REGISTERED). > > Anyone any idea how to solve this problem. And why does Maxplus not give any > warning/errors..... > > Kind regards, > RolandArticle: 44762
Kolja Sulimma wrote: > > > >> There is *no* physical licensing mechanism that might prevent a user from > > >> continuing to maintain existing designs in the indefinite future, as long as > > >> you need it, as long as you want. No problem! > > > >I don't mean to offend you or anyone else at Xilinx, but this is a > > >pretty silly licensing scheme. > > > > I think it is a legal liability issue. If they license it for one year > > only, you can't come back sue them 5 years later. > > Yes, and if a customer decides, that he will not pay 2500 Bucks for > only one year of usage - thats what the EULA says - and therefore > switches to another FPGA Vendor, he will not come back five years > later either. > > And: Maybe customers do not want to a license where Xilinx might come > back five years later and sue the customer. > > (Yes, I know Peter, no intent to do this yada yada... Unisys had no > intent in the 70s to sue anybody over the LZW patents. But the times > they are a changing...) > > Also: Xilinx uses the same license in germany where this type of > license is > clearly against the law. One would believe that a multi billion dollar > company would by able to hire lawyers to check there licenses... > > Kolja Sulimma I agree completely with your points. Whenever I am asked to sign a contract that contains language that I find objectionable, I balk no matter how much I am told that "that is never enforced" or "that is only for trouble makers" or what ever the excuse is. The bottom line is - make the contract say what you intend. So Xilinx, why DO you have a one year license if the software does not stop working and you don't plan to stop anyone from using it? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 44763
I'm working on a design where there is a need to use two clocks that have 180 degree phase between them. I thought of two options : the first , is two sample on both edges of one clock. and the second is two produce two phased clocks using a DCM. please not that the design include also Select RAM units , which can work only on positive edge. please advice.Article: 44764
Kevin Brace wrote: > > rickman wrote: > > > > > > > > I don't know if it is still continuing, but a few months ago, I > > > ordered a WebPACK CD from Insight Electronics free of charge. > > > > > > http://208.129.228.206/solutions/kits/xilinx/webpack/ > > > > Thanks Kevin, the web page is still good so I have made my request. > > He's hoping it works!!! > > > > Hopefully you will get the CD (Actually a CD-R.). > I believe the CD is sent through USPS. > Let news:comp.arch.fpga know when you actually get the CD. > > Kevin Brace (In general, don't respond to me directly, and respond > within the newsgroup.) The Webpack CD came today and it does appear to be a CD-R. It is version 4.2. Anyone know what the current version is? From the messages in this thread, I think 4.2 is current. I will install it on Monday and let you know if there are any problems. BTW, this is purely an Insight service. The CD does not have Xilinx on it anywhere. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 44765
"Eyal Shachrai" <eyals@hywire.com> schrieb im Newsbeitrag news:70029bf5.0206290851.4a1f8939@posting.google.com... > I'm working on a design where there is a need to > use two clocks that have 180 degree phase between > them. I thought of two options : the first , is two > sample on both edges of one clock. and the second > is two produce two phased clocks using a DCM. > please not that the design include also Select RAM units , > which can work only on positive edge. Its a question of the frequency. If you are running some DDR (double data rate) stuff @200 MHz (-> 400MBit/s) or more, Xilinx recommends to use two global clock buffers to create the two clock and to NOT use the clock inversion inside the CLBs/IOBs. If your timing is more relaxed, I think the local clock inversion will work fine. -- MfG FalkArticle: 44766
thanks for the info. since i dont have the option of changing the target chip, i tried the synario complier. the device issue is solved but now i am facing another problem.. the synario compiler does not recognise the std_logic_unsigned package. it keeps giving a 'the following variable has not been declared' error. the same code compiles well in max plus. do the Synopsys libraries (of which std_logic_unsigned is a part of) need to be imported into Synario? if so how? any other suggestions please? -Sandeep Jim Granville <jim.granville@designtools.co.nz> wrote in message news:<3D1D02B0.7EFE@designtools.co.nz>... > Sandeep Unni wrote: > > > > Hi, > > > > I am working on programming a GAL 16v8 chip. I am using the ALtera Max > > plus compiler but i was not able to find the equivalent device. Can > > someone shed some light on this, > > You cannot find it, because Altera do not make GAL16V8. > They used to have 20 pin EP3x0 devices, but no longer. > > Probably your best bet, is Atmel ATF16V8BQL / ATF16V8CZ devices, > and their free WinCUPL tool chain. > > -jgArticle: 44767
"Martin Sauer" <msauer@gmx.net> wrote in message news:3D1CCA39.5000604@gmx.net... > Hello, > > > do you know if there any literature which describe the programming of a > Xilinx CoolRunnerII CPLD? I want to program this CPLD with a > Microcontroller via the JTAG interface. I've been there and done that. However: While getting the player to program was quite easy, and Xilinx also offered a precompiled player, the development tools left a bit to be desired. When I converted the generated svf files for the 32 macrocell part to xsvf, the resulting files from an older webpack would not program and verify the part properly, the files from 4.x would not erase it properly. So I ended up with a mix of versions in order to program the devices. It was not an electrical problem. I also achieved some rather impressive results when the device wasn't properly erased before programming - the maximum was 300mA current consumption, no load on any pin. /KasperArticle: 44768
rickman wrote:
>
>
> The Webpack CD came today and it does appear to be a CD-R. It is
> version 4.2. Anyone know what the current version is? From the
> messages in this thread, I think 4.2 is current. I will install it on
> Monday and let you know if there are any problems.
>
> BTW, this is purely an Insight service. The CD does not have Xilinx on
> it anywhere.
>
I am glad the free CD(-R) service was still available.
The latest version of ISE WebPACK I believe is 4.2WP2.0, but 4.2WP3.0
should be coming out soon in theory (4.2i SP3 is already out.).
Honestly, I don't really see much difference between ISE WebPACK 4.1 and
ISE WebPACK 4.2, so I don't know if ISE WebPACK 4.1 users have to
upgrade to WebPACK 4.2.
At least it doesn't cost anything to upgrade.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 44769rickman wrote: > > Whenever I am asked to sign a > contract that contains language that I find objectionable, I balk no > matter how much I am told that "that is never enforced" or "that is only > for trouble makers" or what ever the excuse is. The bottom line is - > make the contract say what you intend. > > So Xilinx, why DO you have a one year license if the software does not > stop working and you don't plan to stop anyone from using it? > > -- Well, this is a country that graduates far more lawyers than engineers. And they are always looking for something to do... Peter Alfke, speaking fo himself, so Xilinx does not get sued.Article: 44770
Eyal Shachrai wrote: > > please not that the design include also Select RAM units , > which can work only on positive edge. Why do you say that? Last time I looked all Xilinx RAMs could be clocked with either the rising or the falling edge, as a user option. Peter Alfke, Xilinx Applications > >Article: 44771
Does anyone know how I can preserve FFs in LeonardoSpectrum?
When I synthesize a design with LeonardoSpectrum, it aggressively
removes FFs it considers equivalent, which is fine normally, but this
becomes a major problem when writing a constraint file for Quartus II.
I read LeonardoSpectrum Reference Manual, but I am not sure which
keyword I should use to prevent equivalent FF removal, and the syntax of
a constraint file.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 44772Kyle, We have a board that does what you need. Its the QuickUSB Starter Kit and it has an Altera ACEX 10K30 onboard along with a USB 2.0 module that you can use to configure the Altera FPGA and use as a very fast PC interface. The 10K30 part is pin-compatible with a 10K100 if you need more space. We can put the bigger part on if you need it. Check it out at www.quickusb.com Blake "Kyle Davis" <kyledavis@nowhere.com> wrote in message news:g%gK8.3805$Zd.261084368@newssvr13.news.prodigy.com... > Hi folks, > I am looking for FPGA board that use USB port or IEEE 1394 (Firewire) for > downloading to the chip. My notebook only comes with USB and IEEE1394 port > so using FPGA board that only use parallel or serial port won't work! > > Thanks in advance! > > >Article: 44773
On 29 Jun 2002 09:51:32 -0700, eyals@hywire.com (Eyal Shachrai) wrote: > >please not that the design include also Select RAM units , >which can work only on positive edge. >please advice. Ummmm, what Select RAMs only work on the positive edge? From the Virtex-II Users Guide (from Xilinx Website, ug002.pdf) comes the following: Page 56: "The control signals clock (CLK), clock enable (CE) and set/reset (SR) are common to both storage elements in one slice. All of the control signals have independent polarity. Any inverter placed on a control input is automatically absorbed." This can be seen in fig 15 on page 57. If you are using the Block Select RAM, this is covered on page 65: "CLK, EN, WE, and SSR polarities are defined through configuration." While this detail is not shown in the block diagram (fig 29) it is shown in the timing diagram, fig 30. This can also be confirmed in the FPGA editor. Philip Freidin Philip Freidin FliptronicsArticle: 44774
Hi, Since my last post did not get any answer, and before I give up I decided to try again .. Are there any benchmark/figure/data regarding the accuracy of the Xpower tool ? Steven Derrien
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