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Messages from 47300

Article: 47300
Subject: Altera Cyclone low-cost FPGA chips?
From: cheponis <mac@culver.net>
Date: Mon, 23 Sep 2002 03:25:05 -0700
Links: << >>  << T >>  << A >>
Hi, does anyone here have any info on the new Altera "cyclone" 
inexpensive chips?

The only reference I've seen is 
http://www.bayarea.com/mld/mercurynews/business/4133199.htm

Thanks.


Article: 47301
Subject: Re: Xilinx ISE5.1 and Windows NT
From: kolja@bnl.gov (Kolja Sulimma)
Date: 23 Sep 2002 04:00:30 -0700
Links: << >>  << T >>  << A >>
> : Really, the Xilinx tools work pretty good under Wine. I used to have a 
> : dual boot system, but Xilinx/Wine (as well as Actel/Wine, the other tool 
> : chain I use) has been working so well that I dumped Windows about 6 months.
> 
> Duane, what is your option to download the bitstream to the FPGA under Linux?
> 
> I looked hard at running impact.exe under wine, but as impact probably uses
> a windriver.sys file to  access the parallel port, it seems not feasable
> with wine.

It became extreamly simple to write your own download code since Linux
includes the new parport driver.

Here is one example
http://groups.google.de/groups?hl=de&lr=&ie=UTF-8&selm=9i1146%24g90jk%241%40ID-31589.news.dfncis.de&rnum=3

And another one:
http://groups.google.de/groups?q=bitstream+linux+group:comp.arch.fpga&hl=de&lr=&ie=UTF-8&selm=3A9ACE4C.6922CAA5%40wanabe.nl&rnum=2

Here is some older code that does not use the parport driver:
http://groups.google.de/groupsq=bitstream+linux+group:comp.arch.fpga&hl=de&lr=&ie=UTF-8&selm=9muuu9%24s1d%241%40eng-ser1.erg.cuhk.edu.hk&rnum=1

BTW:
These codes are a lot faster than impact.
All these programs solve the problem described in
http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=6545
while the solution given in answer 6545 does not fix it.

Parallel Download Cable III has no instability problem! All the
trouble with this cable reported in this newsgroup is due to Hardware
Debugger software bugs. (A race condition that is correctly identified
in the code activated by XIL_HWD_PCAB_FIX, but not fixed.)

Kolja Sulimma

Article: 47302
Subject: Re: Apex unused pins voluntarily assigned by Quartus?
From: "Mikhail Matusov" <matusov@ANNTIsquarepegSPPAMM.ca>
Date: Mon, 23 Sep 2002 13:32:28 GMT
Links: << >>  << T >>  << A >>
Thank you very much, Christoph!

I was looking into the *.csf.htm report and this information wasn't there.
Interestingly my pin file doesn't have explanation about the GND* while it
does about the GND+. But, this, I guess, is because I am not using the
latest version of Quartus.

Thank you again,
/Mikhail





From: Christoph Fritsch (christoph_fritsch@gmx.de)
Subject: Re: Apex unused pins voluntarily assigned by Quartus?
Newsgroups: comp.arch.fpga
View this article only
Date: 2002-09-20 09:34:03 PST


Hi Mikhail,

please read carefully through the pin-file you get from Quartus.
It says:

 -- GND+   : Unused input. This pin should be connected to GND. It may also
be connected  to a  valid signal  on the board  (low, high, or toggling)  if
that signal is required for a different revision of the design.

 -- GND*     : Unused  I/O  pin.   This pin can either be left unconnected
or connected to GND.  Connecting this pin to GND will improve the device's
immunity to noise.

This should answer the question on "what it means"

To resever the FAST pins as input's (beeing tri-stated) go into the compiler
settings dialog -> chips&devices -> assign pins.  Select the pin and use a
name you like (dummy1...3) and select "reseve pin even if it does not exist
in the design"

HTH
Christoph

--





Article: 47303
Subject: Re: Xilinx RAM16x1D, Write fails in functional Simulation
From: Ray Andraka <ray@andraka.com>
Date: Mon, 23 Sep 2002 13:33:51 GMT
Links: << >>  << T >>  << A >>
set the timingChecksOn generic to false.  Also, for the sake of synthesis put
synthesis translate_off pragmas around the library unisim and the black box
generics

itsme wrote:

> I want to simulate the Xilinx RAM16x1D
> using Modelsim, but all Writes fail.
> After writing to the RAM the Data in the Ram is invalid (DPO='X').
> I get Timing Errors:
>
> # ** Warning: */RAM16X1D SETUP High VIOLATION ON WE WITH RESPECT TO WCLK;
> #   Expected := 0.01 ns; Observed := 0 ns; At : 20 ns
> #    Time: 20 ns  Iteration: 3  Instance: /test_sram/prg_ram
>
> But I like to do just funktional simulation.
> So Setup und Hold times should not be checked
> and the Functional Model should not rely on any Setup or Hold Times
> Maybe I use the wrong LIBs?
> Can anyone help?
> thanks peter
>
> Here is my VHDL source:
> ----------------------------------------------------------------
> ----------------------------------------------------------------
> LIBRARY ieee;
>     use IEEE.STD_LOGIC_1164.ALL;
>     use IEEE.STD_LOGIC_UNSIGNED.ALL;
>     use IEEE.STD_LOGIC_ARITH.ALL;
>

--synthesis translate_off

>
> library unisim;
>     use  UNISIM.all;
>

--synthesis translate_on

> entity test_sram is
> end test_sram;
>
> architecture Behavioral of test_sram is
>
> ----------------------------------------------------------------
> component RAM16X1D

--synthesis translate_off

>
>   generic (
>        TimingChecksOn: Boolean := FALSE;  --<<<<<< this should be false
>        InstancePath:   STRING  := "*"; --don't need this
>        Xon:  Boolean := True;--don't need this
>        MsgOn:  Boolean := False);--don't need this

--synthesis translate_off

>
>   port (
>     WE : in std_logic;
>     D : in std_logic;
>     WCLK : in std_logic;
>     A0 : in std_logic;
>     A1 : in std_logic;
>     A2 : in std_logic;
>     A3 : in std_logic;
>     DPRA0 : in std_logic;
>     DPRA1 : in std_logic;
>     DPRA2 : in std_logic;
>     DPRA3 : in std_logic;
>     SPO : out std_logic;
>     DPO : out std_logic
>   );
> end component;

attribute syn_black_box:boolean;
attribute syn_black_box of RAM16x1D:component is TRUE;

>
>
> signal    WE : std_logic;
> signal    D: std_logic;
> signal    CLK:std_logic;
> signal    A:std_logic_vector(3 downto 0);
> signal    DPA:std_logic_vector(3 downto 0);
> signal    DPO:std_logic;
> signal    SPO:std_logic;
>
> begin
>
> ----------------------------------------------------------------
>    PRG_RAM: RAM16X1D
>   generic map(MsgOn => True)
>
>         port map (
>     WE => WE,
>     D =>  D,
>     WCLK =>CLK,
>     A0 =>A(0),
>     A1 =>A(1),
>     A2 =>A(2),
>     A3 =>A(3),
>     DPRA0 => DPA(0),
>     DPRA1 => DPA(1),
>     DPRA2 => DPA(2),
>     DPRA3 => DPA(3),
>     SPO => SPO,
>     DPO => DPO);
>
> process
> begin
>  wait for 5 ns;
>  CLK <='0';
>  wait for 5 ns;
>  CLK <='1';
> end process;
>
> process
> begin
>   D<='1';
>   A <="0001";
>   DPA<="0000";
>   WE<='0';
>   wait until CLK'event and CLK='1';
>   wait until CLK'event and CLK='1';
>
>   -- Write '1' to Location 1
>   D<='1';
>   WE<='1'; -- 1 auf adr 1 schreiben, Adr 0 lesen
>   wait until CLK'event and CLK='1';
>   WE<='0';
>   wait until CLK'event and CLK='1';
>   -- here I get a 'X' as SPO !!!???
>   wait until CLK'event and CLK='1';
>
>   -- Read Location 1
>   -- Here I get 'X' on DPO
>   -- but I want to see here '1'
>   DPA<="0001";
>   wait until CLK'event and CLK='1';
>   wait until CLK'event and CLK='1';
>
>   wait;
> end process;
>
> end Behavioral;

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 47304
Subject: Re: Altera Cyclone low-cost FPGA chips?
From: "ds" <nospam@cwix.com>
Date: Mon, 23 Sep 2002 13:49:13 GMT
Links: << >>  << T >>  << A >>
http://www.altera.com/products/devices/cyclone/cyc-index.jsp?xy=hp1_cychp

http://biz.yahoo.com/prnews/020923/sfm042_1.html

- DS

"cheponis" <mac@culver.net> wrote in message
news:3D8EEC01.1000306@culver.net...
> Hi, does anyone here have any info on the new Altera "cyclone"
> inexpensive chips?
>
> The only reference I've seen is
> http://www.bayarea.com/mld/mercurynews/business/4133199.htm
>
> Thanks.
>



Article: 47305
Subject: MTBF
From: "Manuel Zaera Sanz" <Manuel.Zaera.Sanz@cern.ch>
Date: Mon, 23 Sep 2002 15:54:30 +0200
Links: << >>  << T >>  << A >>
Dear sirs,
     I would like to have a general idea about the MTBF of a FPGA.

Thank you.



Article: 47306
Subject: Re: Altera Cyclone low-cost FPGA chips?
From: rickman <spamgoeshere4@yahoo.com>
Date: Mon, 23 Sep 2002 10:04:57 -0400
Links: << >>  << T >>  << A >>
You will find the Altera press release here

http://www.altera.com/corporate/news_room/releases/products/nr-cyclone.html?xy=whp1_cycpr


Or you can start on the reading about the details here

http://www.altera.com/products/devices/cyclone/cyc-index.jsp

Looks like they are finally responding to Spartan.  This can only be
good for the users.


cheponis wrote:
> 
> Hi, does anyone here have any info on the new Altera "cyclone"
> inexpensive chips?
> 
> The only reference I've seen is
> http://www.bayarea.com/mld/mercurynews/business/4133199.htm
> 
> Thanks.

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 47307
Subject: Fast serial interconnect bus using spartan-II
From: meng.engineering@bluewin.ch (Markus Meng)
Date: 23 Sep 2002 07:23:48 -0700
Links: << >>  << T >>  << A >>
hi all,

has anybody done this using spartan-ii with - for example -
an LVDS interface?

What I require is a fast serial - bus like - connection between
3 or 4 electronic modules. Those modules are close to each other
but in separate cabinets. I would like to use - let's say - RJ11
connector and cabling, the speed should be ~ 100 Mbps

markus

Article: 47308
Subject: Re: MTBF
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Mon, 23 Sep 2002 07:30:40 -0700
Links: << >>  << T >>  << A >>

--------------ECABA1D0EF195B9C2B5A6EBF
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

 http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=11768

answer number 11768.

Austin

Manuel Zaera Sanz wrote:

> Dear sirs,
>      I would like to have a general idea about the MTBF of a FPGA.
>
> Thank you.



Article: 47309
Subject: Re: Overheat with XCV-600E
From: pierrotlafouine@hotmail.com (Pierre Lafrance)
Date: 23 Sep 2002 07:36:49 -0700
Links: << >>  << T >>  << A >>
Thaks all
I have already made few tests you suggested me.
I'll come with result when I find the problem in couple of weeks (I
have to recompile an other FPGA for an other urgent project).

Life is good, it feed us with problems to solve... 
Only engineer can enjoy this.
Cheer

Pierre


Philip Freidin <philip@fliptronics.com> wrote in message news:<23fsou8f5u9472u205cclfgd89dlmil99v@4ax.com>...
> While 65C is hot to touch, this is well within normal operating
> temperature.
> 
> Here are some tests you could try, after re-checking that you
> dont have I/O contention (output connected to output).
> 
> A) Power the board but dont configure the FPGA. It should be cold.
> 
> B) Power the board but dont clock the FPGA. It should be cold.
> 
> C) Create a dummy design that drives the outputs with alternating
>    0 and 1, but bulk of chip is empty. It should be cold to warm.
> 
> If any of these run hot, you need to figure out why. For B and C,
> you could selectively disable output till you find out which one
> is having contention issues (if that is the problem)
> 
> Philip
> 
> 
> 
> On 19 Sep 2002 14:55:31 -0700, pierrotlafouine@hotmail.com (Pierre Lafrance)
> wrote:
> >Hi all
> >I respined a product, changing the old Xilinx XV-300 with a XCV-600E.
> >Of course, I had to change voltage regulator from 2.5 to 1.8 volts,
> >and few 5 volts CPLD to 3.3v.
> >
> >The problem is : the XCV-600E overheat, and 1 of the prototype just
> >died.
> >I tried to find any hardware signal that would exceed voltage but
> >couldn't.  Hardware seems to be just fine.  I suspect the chips itself
> >to overheat.  I just put a heatseak temporarly, but would like to
> >solve the problem if I can.
> >
> >Simulation with XPower estimate the chips temperature to be 50C, but I
> >measure up to 65C.
> >
> >The disign use 75% of BRAM, and 75% of FF of the XCV-600E.
> >Clock is 82MHz.
> >
> >Anybody experienced overheat with 600E ?
> >
> >Cheers !
> >
> >Pierre
> 
> Philip Freidin
> Fliptronics

Article: 47310
Subject: Re: Altera Cyclone low-cost FPGA chips?
From: rickman <spamgoeshere4@yahoo.com>
Date: Mon, 23 Sep 2002 10:55:14 -0400
Links: << >>  << T >>  << A >>
rickman wrote:
> 
> You will find the Altera press release here
> 
> http://www.altera.com/corporate/news_room/releases/products/nr-cyclone.html?xy=whp1_cycpr
> 
> Or you can start on the reading about the details here
> 
> http://www.altera.com/products/devices/cyclone/cyc-index.jsp
> 
> Looks like they are finally responding to Spartan.  This can only be
> good for the users.

After taking a quick look at the Cyclone family, I can see they are
taking a slightly different approach than Xilinx.

The Xilinx Spartan II series is based on the Virtex family just as the
Spartan was based on the XC4000.  In contrast, it looks like the Cyclone
family is not directly based on any existing Altera family.  

Comparing the Spartan II to the Cyclone shows that the Cyclone has a
higher LUT to IO ratio.  The Cyclone looks a little more like a
potential future Spartan III based on the Virtex II family which also
has a high LUT to IO ratio.  

SpartanII 2S50E 2S100E 2S150E 2S200E 2S300E
LUTs       1536   2400   3456   4700   6144
IOs         182    202    263    289    329
ratio         8     12     13     16     19

Cyclone  EP1C3 EP1C6 EP1C12 EP1C20
LUTs      2910  5980  12060  20060
IOs        104   185    249    301
ratio       28    32     48     67

As it turns out this makes the Cyclone parts very expensive in high IO
count applications.  Further, Altera seems to not have small chip scale
packages for the low end of the family.  Looks like they really tried to
go for a low price, limited options product line, even more so than the
Spartan II.  The high LUT count may prove a benefit for some
applications though.  


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 47311
Subject: Altera Cyclone 'FPGA'
From: "Leon Heller" <leon_heller@hotmail.com>
Date: Mon, 23 Sep 2002 15:18:06 +0000 (UTC)
Links: << >>  << T >>  << A >>
I see that Altera is referring to the new Cyclone devices as 'FPGAs'. I
don't recall them using the term FPGA, before. Is this a new marketing ploy?

Leon
--
Leon Heller, G1HSM
leon_heller@hotmail.com
http://www.geocities.com/leon_heller



Article: 47312
Subject: Re: fpga eval kits
From: Rene Tschaggelar <rets@esr.phys.chem.ethz.ch>
Date: Mon, 23 Sep 2002 17:55:14 +0200
Links: << >>  << T >>  << A >>
Your request is far beyond an evaluation kit. You want a
PCI card with complete software interface. Plus you want
CPU core inside the FPGA.

Rene

newb wrote:
> Hello,
> 
> I am interested in integrating a virtual cpu that can take 
 >instructions from a pc and then compute them within the fpga,
> then return the computed result back to the computer. I would 
 > like to know if anyone could suggest a fpga evaluation kit that
> would be ideal for this situation. Thank you.


Article: 47313
Subject: Re: Fast serial interconnect bus using spartan-II
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Mon, 23 Sep 2002 18:23:10 +0200
Links: << >>  << T >>  << A >>
"Markus Meng" <meng.engineering@bluewin.ch> schrieb im Newsbeitrag
news:aaaee51b.0209230623.700eae42@posting.google.com...
> hi all,
>
> has anybody done this using spartan-ii with - for example -
> an LVDS interface?

For LVDS you need Spartan-IIE.

> What I require is a fast serial - bus like - connection between
> 3 or 4 electronic modules. Those modules are close to each other
> but in separate cabinets. I would like to use - let's say - RJ11
> connector and cabling, the speed should be ~ 100 Mbps

Havent done this yet, but should be easy. Just use a LVDS-Pair for data, a
second for Clock, and, If you really love luxury, a third for a frame pulse.
@ 100 Mbit/s and single data rate clocking, this should be easy.

--
MfG
Falk




Article: 47314
Subject: Re: Altera Cyclone low-cost FPGA chips?
From: tech@auroranetworks.com (Jack)
Date: 23 Sep 2002 09:28:25 -0700
Links: << >>  << T >>  << A >>
It's in EE Times as well.  Looks pretty good.  I found datasheets, app
notes, lots of other material linked through their press release.

http://www.altera.com/corporate/news_room/releases/products/nr-cyclone.html

Jack

cheponis wrote:
> Hi, does anyone here have any info on the new Altera "cyclone" 
> inexpensive chips?
> 
> The only reference I've seen is 
> http://www.bayarea.com/mld/mercurynews/business/4133199.htm
> 
> Thanks.

Article: 47315
Subject: Re: Fast serial interconnect bus using spartan-II
From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver)
Date: Mon, 23 Sep 2002 17:03:39 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <amng0g$74hgf$1@ID-84877.news.dfncis.de>,
Falk Brunner <Falk.Brunner@gmx.de> wrote:
>> What I require is a fast serial - bus like - connection between
>> 3 or 4 electronic modules. Those modules are close to each other
>> but in separate cabinets. I would like to use - let's say - RJ11
>> connector and cabling, the speed should be ~ 100 Mbps
>
>Havent done this yet, but should be easy. Just use a LVDS-Pair for data, a
>second for Clock, and, If you really love luxury, a third for a frame pulse.
>@ 100 Mbit/s and single data rate clocking, this should be easy.

Silly observation, but couldn't you just use Ethernet as your
connection media at that data rate?  I know it is in some ways
overkill, but it gives you sometihng guarenteed to work.
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 47316
Subject: Re: Altera Cyclone low-cost FPGA chips?
From: "Jan Gray" <jsgray@acm.org>
Date: Mon, 23 Sep 2002 10:04:25 -0700
Links: << >>  << T >>  << A >>
I have started some Cyclone links and commentary at fpgacpu.org.

Jan Gray, Gray Research LLC




Article: 47317
Subject: Unused pins in Apex20KE
From: prashantj@usa.net (Prashant)
Date: 23 Sep 2002 10:25:39 -0700
Links: << >>  << T >>  << A >>
hi,

I'm using the A15E board from Altera (DSP Development board). I have a
design which has a clk input, reset input and an LED output. I do not
use any other I/O's. While compiling my design, I assign RESET and LED
output to the correct pins on the board. I assume the CLK inputs get
assigned correctly by themselves.

What needs to be done to the unused pins in the Apex20KE device on the
A15E board ? Do I need to assign the rest of the I/O pins to GND or
anything else, or can I go ahead and compile my design with just the 2
assignments above and not bother about the rest of the pins assuming
that the board design has taken care of what happens to the unassigned
pins.

Anyone with Altera boards experience ?

Thanks,
Prashant

Article: 47318
Subject: Re: external switch to CPLD input
From: jjjkkl@hotmail.com (John)
Date: 23 Sep 2002 10:48:53 -0700
Links: << >>  << T >>  << A >>
Jim Granville <jim.granville@designtools.co.nz> wrote in message news:<3D8D2E62.4B25@designtools.co.nz>...
> John wrote:
> > 
> > I would like to use a push-button switch (either normally open or
> > normally closed) to drive a logic one (3V) or logic zero to a Xilinx
> > CoolRunner XPLA3 CPLD. The input current should be no more than a few
> > uA. Can anyone suggest a circuit for this using my switch, 3V supply,
> > and hopefully just a small amount of resistors (and caps, if
> > necessary)?
> 
>  See also other postings on this 
> 
>  The smallest/simplest switch connection is using a SPCO
> 
> Vcc -----\
>           o--------- PIN
> GND ----- 
> 
>  This works best with a pin-keeper, and draws no current in either
> state. 
>  It also has bounce-removal.
>  Some CPLDs have symmetric pinkeepers built in, on the others,
> you can drive the OP-IP to create a pinkeeper.

Can I connect Vcc or GND directly to the input pin (with no
resistors), regardless of whether I have a pin-keeper? How do I
calculate the current drawn this way.. can I just model the CPLD side
of the input pin as some resistor value to ground?
I don't think the Xilinx CoolRunner XPLA3 has a pin-keeper. When you
suggest creating one, do you mean on the CPLD using HDL or using
external components?


>  For SPNO (tact ) type switches, you need a pullup (10-100K), 
> and then Icc is drawn when pressed, and you also have 
> bounce to handle.
I'm handling debouncing in logic.

When the switch is in its open state, the pin would be left floating.
Should I connect it directly to ground, or to ground using a pulldown?
When the switch is closed, how would I find the current and voltage at
the pin when I'm using the 10-100K pullup (ie. again, how do I model
the CPLD side of the input)?

Thanks a lot for your response.. I'm kinda new to all this as you can
probably tell, so thanks for helping me out!

>  If you want a 'clean edges' signal, then use a TinyLogic HC1G14 and
> a pullup, plus series RC to filter the bounce.
> 
> - jg

Article: 47319
Subject: Re: Unused pins in Apex20KE
From: Christoph Fritsch <christoph_fritsch@gmx.de>
Date: Mon, 23 Sep 2002 20:24:27 +0200
Links: << >>  << T >>  << A >>
Hi Prashant.
 
> While compiling my design, I assign RESET and LED output to the correct 
> pins on the board. I assume the CLK inputs get assigned correctly by themselves.
Depends on your designflow. If you use DSPBuilder and use the AltLib 
elements for the development board, yes!

> What needs to be done to the unused pins in the Apex20KE device on the
> A15E board ? 

Nothing else.

> can I go ahead and compile my design with just the 2
> assignments above and not bother about the rest of the pins assuming
> that the board design has taken care of what happens to the unassigned
> pins.

If you use the generated scripts (and QuartusII default settings) all
unused
IO will be set to "outputs driving ground". 

If you want to make sure that nothing goes wrong, prepare a script that
configures those pins on the Apex which are meant to be inputs from 
other devices (like the ADC) as unused inputs (which will be tristated,
if not used
in the design). All unconnected pins should be left "outputs driving
ground",
which is default for unused pins for Quartus. 

Christoph

Article: 47320
Subject: Re: MTBF
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 23 Sep 2002 12:07:32 -0700
Links: << >>  << T >>  << A >>

--------------3F52D7D9B40117DA1E0FB7FB
Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353"
Content-Transfer-Encoding: 7bit

Here is the "executive summary" from page 19 of that 218-page report:

After testing devices for millions of device hours at 125 degr C, the
calculated failure rate at Tj = 55 degr C is between 5 and 30 FIT, where
one FIT = one failure per billion device hours.

So the MTBF per device (i.e. per packaged chip) is somewhere between 33
million and 200 million hours, which means somewhere between four
thousand and 25 thousand years.

Peter Alfke
================================================
Austin Lesea wrote:

>  http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=11768
>
> answer number 11768.
>
> Austin
>
> Manuel Zaera Sanz wrote:
>
>> Dear sirs,
>>      I would like to have a general idea about the MTBF of a FPGA.
>>
>> Thank you.
>



Article: 47321
Subject: Re: external switch to CPLD input
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Tue, 24 Sep 2002 07:40:53 +1200
Links: << >>  << T >>  << A >>
John wrote:
> 
> Jim Granville <jim.granville@designtools.co.nz> wrote in message news:<3D8D2E62.4B25@designtools.co.nz>...
> > John wrote:
> > >
> > > I would like to use a push-button switch (either normally open or
> > > normally closed) to drive a logic one (3V) or logic zero to a Xilinx
> > > CoolRunner XPLA3 CPLD. The input current should be no more than a few
> > > uA. Can anyone suggest a circuit for this using my switch, 3V supply,
> > > and hopefully just a small amount of resistors (and caps, if
> > > necessary)?
> >
> >  See also other postings on this
> >
> >  The smallest/simplest switch connection is using a SPCO
> >
> > Vcc -----\
> >           o--------- PIN
> > GND -----
> >
> >  This works best with a pin-keeper, and draws no current in either
> > state.
> >  It also has bounce-removal.
> >  Some CPLDs have symmetric pinkeepers built in, on the others,
> > you can drive the OP-IP to create a pinkeeper.
> 
> Can I connect Vcc or GND directly to the input pin (with no
> resistors), regardless of whether I have a pin-keeper?

yes ( use Vccio )

> How do I calculate the current drawn this way.. 

There is nominally zero static current in either state

> can I just model the CPLD side
> of the input pin as some resistor value to ground?

No, a pineeper is a snap-action current source

> I don't think the Xilinx CoolRunner XPLA3 has a pin-keeper. When you
> suggest creating one, do you mean on the CPLD using HDL or using
> external components?

See Peter A's post - you make a 'pinkeep' using regen pin drive
( but this does mean consuming a IO pin )

Vcc-----\       Pin        IPb
         o-------|---+------|>----+--->
GND ----             |     OPb    |
                     +------<|----+ 

Here, the pin is an OP, set to == the IP, ie async regen path.
( some synthesis tools will love this :)

The switch has to deliver enough brief current to force the 
Output buffer past the IP buffer threshold, thereafter it snaps, 
and holds that state until pulled the other way.
( If the option is there, set the OPb for the lowest drive )

> 
> >  For SPNO (tact ) type switches, you need a pullup (10-100K),
> > and then Icc is drawn when pressed, and you also have
> > bounce to handle.
> I'm handling debouncing in logic.
> 
> When the switch is in its open state, the pin would be left floating.
> Should I connect it directly to ground, or to ground using a pulldown?

using a pull down

> When the switch is closed, how would I find the current and voltage at
> the pin when I'm using the 10-100K pullup (ie. again, how do I model
> the CPLD side of the input)?

100K at 3V, is 3V/0.1M -> 30uA - this is drawn only during button press.

> 
> Thanks a lot for your response.. I'm kinda new to all this as you can
> probably tell, so thanks for helping me out!
> 
> >  If you want a 'clean edges' signal, then use a TinyLogic HC1G14 and
> > a pullup, plus series RC to filter the bounce.
> >
> > - jg

Article: 47322
Subject: Re: Timing accuracy with Modelsim
From: "Lorenzo Lutti" <lorenzo.lutti@DOHtiscalinet.it>
Date: Mon, 23 Sep 2002 20:26:28 GMT
Links: << >>  << T >>  << A >>
"Lorenzo Lutti" <lorenzo.lutti@DOHtiscalinet.it> ha scritto nel
messaggio news:xnmj9.74239$Hc7.617967@twister1.libero.it...

[...]

As usual, five minutes after I've sent the message I found the solution.
Thank you all, anyway. :)

P.S. Which books (either online and not) do you suggest as a
beginner/intermediate VHDL reference focused on programmable logic
syntesis? I am reading some generic VHDL books like the "VHDL Cookbook",
but they are very abstract and obsolete.

--
Lorenzo



Article: 47323
Subject: Re: Fast serial interconnect bus using spartan-II
From: "Stephen Bradshaw" <pleasecontactraquairforemailvia@www.traquair.com>
Date: Mon, 23 Sep 2002 21:42:03 GMT
Links: << >>  << T >>  << A >>
Markus,

Check out the HEART communications used with HERON DSP Systems.

HERON is an off the shelf board level product family  that combines
Spartan-II or Virtex-II FPGAs, as well as DSPs and analog I/O. It might give
you some ideas.

http://www.traquair.com/catalog/heron.systems.html

HEART allows the resources, which take the form of modules, to communicate
with each other in increments of 67MBytes/sec. There are some options that
should be available shortly that will seamlessly extend the communications /
data paths between "cabinets" in the manner consistent with what you
describe.

Regards,
Stephen Bradshaw
Traquair



"Markus Meng" <meng.engineering@bluewin.ch> wrote in message
news:aaaee51b.0209230623.700eae42@posting.google.com...
> hi all,
>
> has anybody done this using spartan-ii with - for example -
> an LVDS interface?
>
> What I require is a fast serial - bus like - connection between
> 3 or 4 electronic modules. Those modules are close to each other
> but in separate cabinets. I would like to use - let's say - RJ11
> connector and cabling, the speed should be ~ 100 Mbps
>
> markus



Article: 47324
Subject: Re: fpga eval kits
From: "A. Nelson" <anelson@NS.lumenera.com>
Date: Mon, 23 Sep 2002 17:46:30 -0400
Links: << >>  << T >>  << A >>
Go to http://www.insight-electronics.com

and check out their Xilinx evaluation boards. They have a Spartan-II based
PCI eval. board.

"newb" <n/a@ee.net> wrote in message news:ee791fd.-1@WebX.sUN8CHnE...
> Hello,
>
> I am interested in integrating a virtual cpu that can take instructions
from a pc and then compute them within the fpga, then return the computed
result back to the computer. I would like to know if anyone could suggest a
fpga evaluation kit that would be ideal for this situation. Thank you.





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