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"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message
news:apbvos$87m2$2@ID-84877.news.dfncis.de...
> "Noddy" <g9731642@campus.ru.ac.za> schrieb im Newsbeitrag
> news:1035529157.441767@turtle.ru.ac.za...
>
> > (a) I installed ModelSim with ISE, but do not have a license for
ModelSim
> so
> > have to use starter license. When ModelSim was called for the watch tut,
I
> > got a warning that the design was too big. Does this mean I am going to
be
> > severely limited in simulations when I move onto bigger and better
things?
>
> Modelsim with an evaluationlicense will slow down to 1% if you design is
> largen than 500 lines HDL. IT will further slow down to 0.1% after 200
> lines, AFAIK.
>
Falk,
I did not realize that you were the one who gave those percentages.
Where did you get them from? Also, is there a type in the 0.1% after 200
lines (perhaps 2000 lines)?
Thanks,
Theron
> >
> > (b) What, if there are any, the equivalents of the Functional Simulation
> and
> > Timing Simulation in Foundation?
>
> Functional -> Behavioural
> Timing -> Post Place& Route
>
> BUT, as this toppic has been discussed a few times, in general it is
> sufficient to do a Behavioural sim to ckech the logic function. Then apply
a
> timing constaint to your clock(s) and IOs and let the static timing
> analyzertell you if you design meets the speed you need or not.
> This is much faster and checks more (all?) datapaths, which can be hardlx
> covered in a timing sim.
>
> > (c) Is there another way to simulate my schematic in ISE without it
using
> > ModelSim?
>
> Use another simulator. But IMHO Modelsim runs fine after you got over the
> critical point.
>
> > (d) It was never very apparent in Foundation, so I didn't really bother
> > about it, but upon completion of schematic design, does the system
convert
> > this design into HDL before simulation?
>
> ?? Dunno.
>
> --
> MfG
> Falk
>
>
>
>
Article: 48876"Rain One" <rainyfork@yahoo.com> wrote in message news:mp5u9.96051$La5.315399@rwcrnsc52.ops.asp.att.net... > We have designed our own PCI core on a Spartan II. > However, we cannot get burst reads to work at all. > The computer is an pentium III and we use the Windriver tool. > > Does anyone have a suggestion of how to make this work? > > I think i read somewhere that the only way to do this is through a DMA. > is this true? Are you talking about your board being a target or a master? Who is doing the burst initiating, and what is your target? If your design is the target, does your core support target bursts? If so, then who is the master (initiator of the bursts), the x86? If so, that will only give you 4 transfers (depending on the CPU and PCI bridge etc.) max at a time. If some other device, does the other device support bursts as a master? This isn't meant insultingly at all, but something tells me you don't really understand the concept of target/master on PCI. There is no such thing as "DMA" on the PCI bus, really. There are targets, and masters (initiators), and to support burst transfers, both have to support burst transfers. If either one doesn't support bursts, then you won't get bursts. Have you hooked up a PCI analyzer or a logic analyzer to your PCI bus to see what is happening? Did you actually design your own core from scratch, or are you using some "core" from the web? AustinArticle: 48877
They have purchasing information on how to specify a part number (c/i speed grade, etc), but nothing on chip labeling <ae> wrote in message news:ee79f55.0@WebX.sUN8CHnE... > I don't know but the data sheets for it should have the info?Article: 48878
In article <mp5u9.96051$La5.315399@rwcrnsc52.ops.asp.att.net>,
Rain One <rainyfork@yahoo.com> wrote:
>We have designed our own PCI core on a Spartan II.
>However, we cannot get burst reads to work at all.
I assume you mean the P-III reading from your card. It's true, the chipset
on your motherboard will not do read aheads. The reason is that the P-III
is not asking for a burst- it's only asking for a single word. It will not
request the next word until you feed it the read from the first word. Thus
the chipset does not know how much to read from the memory and will not do a
burst. The chipset could speculatively burst, but it's dangerous: perhaps
the address space ends right in the middle of the burst, or a read on your
card triggers an action (it's not simple memory).
However, it almost certainly buffer writes, so at least you can write to
your card fast.
One possibility to tell the processor that the your card has cacheable
memory, then it may do cacheline reads from your card as a single burst.
The PCI chipset has to support this (I'm guessing that most will only do
cache reads from memory, not PCI), you need to support the readline command
in your PCI target, your card has to look like simple memory (I'm guessing
it doesn't), so you're probably out of luck.
Another possibility is to find a superscaler processor which holds off
issuing read requests for a while to see if there are more forthcoming reads
to adjacent addresses (or merges read requests to adjacent addresses
together in the read request queue). I suppose this is theoretically
possible, but I don't know of any processor which actually does it.
Hmm... I wonder if the x86 pusha and popa instructions will issue burst
requests? It's worth a try...
If performance matters, you need to make a bus mastering PCI core and have
your card transfer the data directly to memory.
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 48879rrr@ieee.org (Rajeev) writes: > I'm looking for an inexpensive 3.3V Device Programmer > specifically for XC17S200APD8C DIP-8 Serial EPROM. Depends on what you consider inexpensive. You could use the Xilinx MultiLinx to program the proms using the JTAG port. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 48880
Petter Gustad <newsmailcomp3@gustad.com> writes: > rrr@ieee.org (Rajeev) writes: > > > I'm looking for an inexpensive 3.3V Device Programmer > > specifically for XC17S200APD8C DIP-8 Serial EPROM. > > Depends on what you consider inexpensive. You could use the Xilinx > MultiLinx to program the proms using the JTAG port. The parallel cable is of course cheaper than the MultiLinx (USB, and serial). If you don't have ISP support you can wire up a DIP socket and make your own programmer. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 48881
swda_ic@yahoo.com (sean da) wrote in message news:<c8f47ccb.0210242054.5cad2e17@posting.google.com>... > HI, > > I am designing a low speed(less than 1MHz clock) digital signal > processing unit. > > It comprise: > 1)4K bit ROM > 2)8*8 multiplier > 3)2 12 bit accumulators > 4)1K SRAM > 5) 1 dozen registor and some control logic circuits. > > Please recommend a right choice for the FPGA chips, which has the > right capacity and good price. I have a ISE 4.2 foundation package > from Xilinx, nor sure which series FPGA I should choose, X4000, X9000, > Vertex , Spartan ..., Other vendors product also are considered. > > Appreciate! Take a look at Actel's ProASIC+ "flash-based", re-programmable FPGA. The advantage is it's more ASIC-like in that it does not require an external serial EEPROM to boot-load on power-up. In other words, it instantly comes up live. A second advantage is that you can "sample" your design to prospective buyer/licensee as a single, pre-programmed chip as opposed to a XILINX and a pre-programmed boot ROM combination. A third advantage is security. If you set the security bit, it can't be copied. If you set the "never-erase" bit, it can never be re-programmed or copied. Regards, Jerry D. Harthcock www.quickcores.comArticle: 48882
All, There is an answer record with the information that you're looking for here: http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=1067 It didn't come up immediately when I searched for "part marking", so I'll make sure that our web team has a look at that. Hopefully this clears up future confusion. Cheers, Ryan Tony M wrote: > They have purchasing information on how to specify a part number (c/i speed > grade, etc), but nothing on chip labeling > > > <ae> wrote in message news:ee79f55.0@WebX.sUN8CHnE... > >>I don't know but the data sheets for it should have the info? > > >Article: 48883
I have been learning a little verilog. With the idea to play with my own
CPU.
It seems that one can build multi step processes that run by using a process
time
eg
always
begin
#1;
do register transfer
#1;
do some other transfer
#1
do something else
end
This loops around and around doing that. How do you specify which clock it
should be using to do this? Is this a normal way to do things, or is a state
machine more normal
eg
always @(posedge clk)
begin
switch ( state_reg)
//Do something depending on the state
end
end
Article: 48884Summary: The PLL's are real, a VCO, phase comparitor and the works, the DLL is a delay line with a variable tap. Both vendors A and X have great descriptions in their app notes. President, Quadrature Peripherals Altera, Xilinx and Digital Design Consulting email: kayrock66@yahoo.com http://fpga.tripod.com ----------------------------------------------------------------------------- edaudio2000@yahoo.co.uk (ted) wrote in message news:<c54bf83f.0210240357.153132bf@posting.google.com>... > Just as a matter of interest, > > How are DLLs and PLLs implemented internally in the hardware? > > Are they "proper" PLLs with VCOs, dividers, etc? > > How are DLLs implemented? > > Thanks in advanceArticle: 48885
I always refer to my serial I2C EEPROM databooks when I need to remember something about I2C. President, Quadrature Peripherals Altera, Xilinx and Digital Design Consulting email: kayrock66@yahoo.com http://fpga.tripod.com ----------------------------------------------------------------------------- russelmann@hotmail.com (Rudolf Usselmann) wrote in message news:<d44097f5.0210241830.1ec19d23@posting.google.com>... > "Soul in Seoul" <Far@East.Design> wrote in message news:<3db74e36@news.starhub.net.sg>... > > Hi, > > > > I went to yahoo for "Lecture I2C Bus" and it returned me a bunch of french > > websites. > > Has anyone seen a good decent lecture notes on I2C bus? > > > > Thanks. > > There is a free I2C IP core on OpenCores.org. Perhaps it's > source code and documentation will help you ? > > Cheers, > rudi > ------------------------------------------------ > www.asics.ws - Solutions for your ASIC needs - > FREE IP Cores: http://www.asics.ws/free_ip.shtmlArticle: 48886
Maybe the Xilinx factory guys can correct me if I'm wrong here, but I think for at least the Vertex 2 family, those global buffers are for clocks only. So you either have to use gernal purpose routing and suck it up, or use the deicated GSR wire, but I guess thats not being recommended these days by Xilinx. Best Regards President, Quadrature Peripherals Altera, Xilinx and Digital Design Consulting email: kayrock66@yahoo.com http://fpga.tripod.com ----------------------------------------------------------------------------- "FPGA admirer" <> wrote in message news:<ee79ec7.-1@WebX.sUN8CHnE>... > Hello all, hopefully you can help me with some idea as to what is causing my problem. Instead of the GSR being distributed on a global buffer, the GSR input is being sent to a CLB then from that CLB being sent to every other CLB in the design that uses Global Reset. This is causing extremely high fanout for this signal and I believ consuming massively unneeded routing requirements. I did not notice this problem till I saw the hgih fanout in the floorplanner and checked the design in the FPGA editor, and wow! this signal is all over the chip in nearly every CLB but not on a global net. > > During synthesis I receive this warning: > > Warning: No global set/reset (GSR) net could be used in the design becuase the design contains the unlinked cell '/ver7-Optimized/AWGFIFOIntergace/AddressCounterRAM' > > The RAM referred to was generated using Logiblox, although I do not understand what the unlinked cell means. The RAM is being used by the design and doesn't seem to be optimized out from my observation. > > I have specified an input pad on the chip as GlobalReset. This signal is instantiated onto the GSR input of the STARTUP block. I then pass the GlobalReset signal onto each of my VHDL modules. Am I supposed to pass the GSR signal instead of the GlobalReset? I have two clock buffers in use that are not giving me this error and there are global/clock buffers still available. > > Thanks for any help!Article: 48887
You might want to look at the tutorials at http://tutor.al-williams.com -- I show a few methods of doing simulation with WebPack ISE there. They all actually use MODSIM, but the easy thing is to use TestBencher (or whatever its called) to handle the dirty work. For simple stuff, that seems to work best. Anyway, the tutorial does cover doing it that way or using ModelSim. Good luck! Al Williams AWC http://www.al-williams.com/pldhome.htmArticle: 48888
#1 doesn't synthesize into hardware. You can use it for simulation only. The synthesizer will ignore it. -Kevin "Ralph Mason" <masonralph_at_yahoo_dot_com@thisisnotarealaddress.com> wrote in message news:r9ku9.1270$8o1.241669@news.xtra.co.nz... > I have been learning a little verilog. With the idea to play with my own > CPU. > > It seems that one can build multi step processes that run by using a process > time > > eg > always > begin > #1; > do register transfer > #1; > do some other transfer > #1 > do something else > end > > This loops around and around doing that. How do you specify which clock it > should be using to do this? Is this a normal way to do things, or is a state > machine more normal > > eg > > always @(posedge clk) > begin > switch ( state_reg) > //Do something depending on the state > end > end > >Article: 48889
Hello there, I'm working on a reverse engineering project in which i need to overwrite a signal(8 bits) at a bus at 5 MHz. I'm using a xilinx 9572xl cpld to do this task. Unfortunately, when i write the signal i want, my cpld holds it for a while at the bus and then the chip at the bus overwrite mine. And xilinx enters on a "strange behavior" like missing clock rising edges. I have alredy tried to short some output pins to increase the current suplied. Even though, the same problem continues. I have read xilinx datasheets and application notes, but i couldn't find nothing useful to solve this problem. Does anyone has an advice/tip to help me? Regards, Yusuke PS. (1)Sorry for posting this e-mail at this group, i couldn't find comp.arch.cpld. (2)Sorry for my poor English skillsArticle: 48890
--------------E38B19167B389B49141F6B7D Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hi Yusuke, Most likely, you have the Bus-Hold circuitry enabled - You can find an explanation of bus hold and learn how to disable it here. Thanks, Mark yusuke wrote: > Hello there, > I'm working on a reverse engineering project in which i need to > overwrite a signal(8 bits) at a bus at 5 MHz. I'm using a xilinx > 9572xl cpld to do this task. Unfortunately, when i write the signal i > want, my cpld holds it for a while at the bus and then the chip at the > bus overwrite mine. And xilinx enters on a "strange behavior" like > missing clock rising edges. > I have alredy tried to short some output pins to increase the current > suplied. Even though, the same problem continues. I have read xilinx > datasheets and application notes, but i couldn't find nothing useful > to solve this problem. > Does anyone has an advice/tip to help me? > Regards, > Yusuke > PS. (1)Sorry for posting this e-mail at this group, i couldn't find > comp.arch.cpld. > (2)Sorry for my poor English skillsArticle: 48891
Earlier I wrote: "One can also build a simple barrel processor... Then you can have a 4-deep pipeline without need for any result forwarding muxes ..." See slides 2-7 in this MIT architecture lecture by Asanovic: http://abp.lcs.mit.edu/6.823/lectures/lecture23.pdf. Jan Gray, Gray Research LLCArticle: 48892
VirtualSean wrote: > Thanks guys. > > As a follow-up to Uwe and Peter's kind replies... > > If the clock has the absolute capabilites of 0 and 1 (low and high) > which have clear semantic in digital systems, is the "edge" exploited > as a 3rd "state" - is the "transition" period (latency) recognized by > circuitry and acted-upon (e.g., to "prepare" for the low state, in a > falling edge, or for the high state (in a rising edge)? > > Further, is there any granularity in the edge beyond "being between" > high and low? Can anyone offer a simplified example of the > "preparation" (if this concept is proper) that a chip[set] might > perform "on/at the edge"? Is this just wiggle-room, elbow-room where > the "latency" of the transition is exploited by a chip[set] to perform > certain actions? > > Phew. > > Thanks much for any further information. There are usually requirements for an "edge" to work. Usually it's 1/10th of a clock period, so if you have a triangle wave instead of a square wave, your logic may not function the way you like. The critical events usually occur when the voltage crosses a threshold, and most of the time you want that to happen as fast as possible. This boils down to analog functioning - the transistors can move so many electrons so fast, and you want things to always work. There is also the concept of "setup and hold" time - the time before the clock edge happens many of your signals need to be stable. Again this is a spec defined by the underlying analog circuit. So some signals need to change before the clock so that when the clock edge happens all your digital information is where you want it. Digital electronics is still all analog components. Just lots of 'em :-) Patience, persistence, truth, Dr. mike -- Mike Rosing www.beastrider.com BeastRider, LLC SHARC debug toolsArticle: 48893
> Ok... so are you saying that in order to simulate your design that you have > made in ISE, you have to go out and get a license for ModelSim aswell??? Yes, but for ISE users moldelsim it's completely free of charge... > Otherwise, ISE has no internal simulator?? Why doesn't Xilinx make a > simulator part of ISE to save customers a whole stack of cash? > > adrian -- Yusuke --Article: 48894
Hi, Is it possible to build a crystal oscillator circuit using standard FPGA IO pins? i.e. 1 input an 1 output pin connect internally by an inverter and the crystal connect externally across the pins? Has anyone had any luck doing this? Thanks, ScottArticle: 48895
"Ralph Mason" <masonralph_at_yahoo_dot_com@thisisnotarealaddress.com> writes: > I have been learning a little verilog. With the idea to play with my own > CPU. > > It seems that one can build multi step processes that run by using a process > time > > eg > always > begin > #1; > do register transfer > #1; > do some other transfer > #1 > do something else > end You will usually find code like this in test pattern generators. > This loops around and around doing that. How do you specify which clock it > should be using to do this? Is this a normal way to do things, or is a state > machine more normal There is no clock involved. It's simply 1 time-unit delay. You can (but don't have to) specify what a time unit is by using the `timescale directive. However, if you specify it in one file you need to specify it in all others. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 48896
> Is it possible to build a crystal oscillator circuit using > standard FPGA IO pins? i.e. 1 input an 1 output > pin connect internally by an inverter and the crystal > connect externally across the pins? Thats not a good idea! Use the simple inveter oscillator with an 74hcu04. The 'u' is importand, because it's the unbuffered version. Martin -- JOP - a Java Optimized Processor for FPGAs. http://www.jopdesign.comArticle: 48897
> SOLUTIONS I CANT DO THAT WOULD WORK
> 1.) Put a schmidt trigger on the signal (requires board change)
You can transform the function of a schimdt trigger to the time domain. I've
done this a couple of times:
process(clk, reset)
begin
if (reset='1') then
spike_a <= "000";
elsif rising_edge(clk) then
if sd_clk='1' then -- a slower clock
--
-- delay
--
spike_a(0) <= sdi(1); -- s shift register, sdi is the input
spike_a(2 downto 1) <= spike_a(1 downto 0);
end if;
end if;
end process;
--
-- integrate
--
-- filter input
--
with spike_a select
rx_a <= '0' when "000", -- rxa is the filtered output
'0' when "001",
'0' when "010",
'1' when "011",
'0' when "100",
'1' when "101",
'1' when "110",
'1' when "111",
'X' when others;
hope this helps
Martin
--
JOP - a Java Optimized Processor for FPGAs.
http://www.jopdesign.com
Article: 48898"Theron Hicks" <hicksthe@egr.msu.edu> schrieb im Newsbeitrag news:apc53v$2rph$1@msunews.cl.msu.edu... > > Modelsim with an evaluationlicense will slow down to 1% if you design is > > largen than 500 lines HDL. IT will further slow down to 0.1% after 200 > > lines, AFAIK. > > > > Falk, > I did not realize that you were the one who gave those percentages. > Where did you get them from? Also, is there a type in the 0.1% after 200 > lines (perhaps 2000 lines)? Yes, damm typo. Looks like I need a new keyboard, too much peanut contamination ;-)) And the numbers are AFAIK, I read them in some post from others (at least the 2000 lines slowdown). The 500 lines slowdown is directly annonced by modelsim if you have just a evaluation license. -- MfG FalkArticle: 48899
"Martin Schoeberl" <martin.schoeberl@chello.at> schrieb im Newsbeitrag news:i0tu9.165945$N_6.2385302@news.chello.at... > > Is it possible to build a crystal oscillator circuit using > > standard FPGA IO pins? i.e. 1 input an 1 output > > pin connect internally by an inverter and the crystal > > connect externally across the pins? > Thats not a good idea! Use the simple inveter oscillator with an 74hcu04. > The 'u' is importand, because it's the unbuffered version. > Martin Looks like this is a very basic question which should be put into the FPGA FAQ. -- MfG Falk
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