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ISP PROM's are getting erased but on programming it fails. Can I conclude that the PROMS are gone bad. Because for same settings in an other board, the PROM's are getting programmed well.Article: 73351
I was finally able to compile the code. But when i tried to run the code I got the following message, --> run.x ld.so.1: run.x: fatal: relocation error: file run.x: symbol cerr: referenced symbol not found Killed Exit 137 Does anyone have a clue to what must have gone wrong. The code compiled successfully as --> gmake -f Makefile.gcc g++ -O3 -Wall -I. -I.. -I../../../include -c display.cpp g++ -O3 -Wall -I. -I.. -I../../../include -c numgen.cpp g++ -O3 -Wall -I. -I.. -I../../../include -c main.cpp g++ -O3 -Wall -I. -I.. -I../../../include -c stage1.cpp g++ -O3 -Wall -I. -I.. -I../../../include -c stage2.cpp g++ -O3 -Wall -I. -I.. -I../../../include -c stage3.cpp g++ -O3 -Wall -I. -I.. -I../../../include -L. -L.. -L../../../lib-gccsparcOS5 -o run.x display.o numgen.o main.o stage1.o stage2.o stage3.o -lsystemc -lm 2>&1 | c++filt Regards AARUL JAIN Javier Castillo <jcastillo@opensocdesign.com> wrote in message news:<Xns95645803872B9jcastilloopensocdesi@193.147.184.15>... > aaruljain@gmail.com (Aarul Jain) wrote in > news:15891236.0409130014.5e7a0662@posting.google.com: > > > Hello > > > > I am trying to learn systemc. Systemc was already installed in one of > > the servers and I am using Solaris 2.8 with gcc 3.3 > > > > I am trying to run example programs from the installation directory. > > However when I run make i get error message > > > > -------compiles the code and generates .o -------- > > ---- > > g++ -I. -I.. > > -I/_TOOLS_/dist/systemc-2.0.1/sparc-sun-solaris2.8/include -L. -L.. > > -L/_TOOLS_/dist/systemc-2.0.1/sparc-sun-solaris2.8/libS/gcc-3.2.2 -o > > run.x source.o sink.o fft.o main.o -lsystemc -lm 2>&1 | c++filt > > Undefined first referenced > > symbol in file > > CoolLog::CoolLog[in-charge](char const*, char*, > > bool)/_TOOLS_/dist/systemc-2.0.1/sparc-sun-solaris2.8/libS/gcc-3.2.2/li > > bsystemc.a(sc_main.o) ld: fatal: Symbol referencing errors. No output > > written to run.x collect2: ld returned 1 exit status > > > > I tried to do everything I could but it seems there is some problem in > > makefiles. > > > > Following are the makefiles I used. > > > > Makefile > > > > TARGET_ARCH = gccsparcOS5 > > > > CC = g++ > > OPT = -O3 > > DEBUG = -g > > OTHER = -Wall > > EXTRA_CFLAGS = $(OPT) $(OTHER) > > # EXTRA_CFLAGS = $(DEBUG) $(OTHER) > > > > MODULE = run > > SRCS = source.cpp sink.cpp fft.cpp main.cpp > > OBJS = $(SRCS:.cpp=.o) > > > > include ../Makefile.defs > > > > > > Makefile.defs > > > > ## Variable that points to SystemC installation path > > SYSTEMC = /_TOOLS_/dist/systemc-2.0.1/sparc-sun-solaris2.8 > > > > > > INCDIR = -I. -I.. -I$(SYSTEMC)/include > > LIBDIR = -L. -L.. -L$(SYSTEMC)/libS/gcc-3.2.2 > Hello: > > Try to use gcc 3.2 instead 3.3 > > Regards > > Javier Castillo > jcastillo@opensocdesign.com > www.opensocdesign.com > > > > > > LIBS = -lsystemc -lm $(EXTRA_LIBS) > > > > > > EXE = $(MODULE).x > > > > .SUFFIXES: .cc .cpp .o .x > > > > $(EXE): $(OBJS) $(SYSTEMC)/libS/gcc-3.2.2/libsystemc.a > > $(CC) $(CFLAGS) $(INCDIR) $(LIBDIR) -o $@ $(OBJS) $(LIBS) 2>&1 | > > c++filt > > > > .cpp.o: > > $(CC) $(CFLAGS) $(INCDIR) -c $< > > > > .cc.o: > > $(CC) $(CFLAGS) $(INCDIR) -c $< > > > > clean:: > > rm -f $(OBJS) *~ $(EXE) core > > > > ultraclean: clean > > rm -f Makefile.deps > > > > Makefile.deps: > > # $(CC) $(CFLAGS) $(INCDIR) -M $(SRCS) >> Makefile.deps > > > > #include Makefile.deps > > > > > > Please help somebody, bu mailing me a running code or suggesting any > > modifications to this code. > >Article: 73352
I have a RocketIO simulation environment including a working testbench
running using ISE 4.2iSP2, VCS 5.1 under Solaris 5.1. However, this is
a slow and outdated machine and I'm trying to migrate it to a newer
environment, namely ISE 62iSP3, VCS 7.1.1 under Linux. But even though
the sources are exactly the same the simulation does not work. The
TXN/TXP outputs from the GT_CUSTOM_IO module are X.
Are there any known issues with the combination above?
There seem to be an error in the documentation regarding the LMC_HOME
variable. In our distribution of ISE 6.2i SP3 we have the following
PDF file:
$XILINX/doc/usenglish/books/docs/sim/sim.pdf
On page 202 the example says:
setenv LMC_HOME ${XILINX}/verilog/smartmodel/sol/image
However, there is no such directory. There is a directory
${XILINX}/smartmodel/sol/image but the example in
$XILINX/smartmodel/sol/simulation/vcs/setup suggests the following:
setenv LMC_HOME $XILINX/smartmodel/sol/installed_sol
Which is different from page 202 of sim.pdf. This is confusing. Answer
record 18852 (which is for VCS 6.1/5.2/5.1) suggests the latter so
this is most likely correct, which is what I have used in my
simulation (replaced "sol" with "lin" under Linux).
Petter
--
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Article: 73353Hi I have designed a little tristate bus matrix using Quartus 4.1 (web edition, SP1). The design uses tristate buffers and bi-directional pins that operate as both inputs and outputs (only one way at a time obviously). When I create a symbol for the design (call it symbol A) and use 'A' at the top level of my project, the simulation results are all as expected hence proving that my design works fine. However, if I use 'A' in another .bdf file, add pins etc and then make a new symbol for this design, which in effect is exactly the same as 'A', and I call the new symbol 'B', if I use 'B' in the top level of the project and simulate it, the design doesn't work. This makes no sense to me at all as I am essentially using exactly the same design, but just at different hierarchical layers. When synthesising the second way, I do get a warning about the preservation of boundary logic to do with bi-directional pins being used at different hierarchical layers. I have looked at the help files under "preserve hierarchical boundary logic option" and it recommends that I turn the "preserve_hierarchical_boundary" setting to off. I can't find this option in the Assignment editor as it suggests. Where would I be able to change this setting which supposedly would cure my bi-directional synthesis problem? Has anyone else had this problem and if so, how did you overcome it? If somone could help me out it would be greatly appreciated! Thanks RyanArticle: 73354
On 16 Sep 2004 13:52:46 -0700, sharan_env@yahoo.com (vlsi-student) wrote: >Hi All, > >I am good in Digital System design with Verilog and VHDL Coding. But I >never implemented myself any design on FPGA. Now I am trying to learn >myself the issues related to FPGA implementation. Hi Sharan, Welcome to the gentle world of FPGAs. If your efforts to date have been targetted towards ASICs, the overall flow is the same. Specification, design, coding, test benches, simulation, implementation, simulation, verification. Some things that can be quite problematic in ASIC design, have easier solutions in FPGA land. Clock and power distribution inside the chip are done, and have been done by experts, so these are typically better than what an ASIC designer achieves. Also, there are some features in FPGAs that are a major challenge in ASICs, or are the bleeding edge. In FPGAs they are just part of the chip. Examples include DLL/DCM/PLL, DCI, Dual Port memories, Multipliers, High speed serial (SerDes), Soft and Hard CPU IP. A major part of ASIC design is adding support for manufacturing test, (as opposed to verifying your design intent). This is un-needed with FPGAs, as they are fully tested before you get them (except for anti-fuse products). >So I would like to know what are the important topics I need to >learn..especially implementation issues like configuring your FPGA for >the respective Board environments, configuring I/O's etc. As I have a >Spartan board with Xilinx tool, I would like to learn all the issues >related to implementation. The best thing is to just get started with the examples and tutorials from Xilinx. As for I/O configuration, such as selecting I/O standards, you need to read the documents on the chips that the FPGA connects to, and then select the appropriate mode in the FPGA. When there are multiple choices for outputs, I recommend selecting the lowest drive strength, lowest voltage swing, and slowest edge rate, that still meets the needs of the destination. This leads to lower system noise. >So Please help regarding this... Hope this gets you started in the right direction. >Thanks. > >Best Regards, >VLSI Student Philip =================== Philip Freidin philip.freidin@fpga-faq.com Host for WWW.FPGA-FAQ.COMArticle: 73355
. I have looked at the help files
> under "preserve hierarchical boundary logic option" and it recommends
> that I turn the "preserve_hierarchical_boundary" setting to off. I
> can't find this option in the Assignment editor as it suggests. Where
> would I be able to change this setting which supposedly would cure my
> bi-directional synthesis problem?
>
> Thanks
> Ryan
Hi Ryan,
You can make this seting from the Assignment Editor->Logic Options
Panel. Open the Assignment Editor and click on the Logic Options button in
the upper right hand corner. Once this is done, if you click on the
Assignment Name field you should see this setting in the drop down. This
Assignment should be applied to the Instance of A for which you want to turn
this value OFF. This is specified in the To field of the Assignment Editor.
Therefore the easiest sequence of steps is:
1. Open the Project Navigator->Hierarchy Tab.
2.Find the instance of A for which hierarchy should not be preserved.
3.Right click on the instance and select Locate in Assignment Editor. You
will see a row with the Instance name in there.
4.Click on the Logic Options button in the upper right hand corner of the
Assignment Editor.
5. Select the Preserve Hierarchy Boundary setting in the cell that is at the
intersection of Assignment Name and the row in Step 3.
6. Set the value in the cell adjacent to the cell in Step 5 under the Value
column.
Hope this helps.
Subroto Datta
Altera Corp.
Article: 73356actela, ??? V4 is 90nm and V2P is 130 nm. V4 is columnar architecture, V2P is tradional center and perimeter IO. V4 has 1 more metal layer than V2P. 'nearly identical'? not even close ??? Austin actela wrote: > I admit I'm puzzled. Within a given 'package' form-factor, > the Virtex-4 and Virtex2P parts are going to have > nearly identical circuitry (since they come off the same > lithographic manufacturing process.) > > If you developed a field-process to extract the config-bitstream > of 1 loaded/configured FPGA, presumably you could do it to any > other FPGA based on the same die. > > So does it really matter whether the 'secret key' was unique to each > customer's bitstream? > > Adam Megacz wrote: > >> Austin Lesea <austin@xilinx.com> writes: >> >>> See my other posting today. >> >> >> >> Okay, so, it appears that my argument became invalid about a week ago >> when the Virtex4 shipped. My apologies for this. >> >> But at the same time, so did the argument "we can't document the >> bitstream because it will compromise customer design security".... So, >> what is the current reason for not publishing the bitstream format? >> >> >>> And, you are correct, we have no NVRAM in our FPGA devices right >> >> >> >> I was probably a bit too specific there; I meant any sort of >> customer-writable memory that doesn't get cleared when you take away >> the main power supply to the device. The battery-backed memory for >> storing a customer-specific decryption key is close enough -- in fact, >> this is what Dallas Semico uses (rather than flash or some other >> zero-current storage). >> >> I'm quite happy to see this; unlike previous schemes, this is >> something I would actually trust. A customer-specific (or >> design-specific) key is definately the only way to go for any sort of >> real security. >> >> - a > >Article: 73357
Adam, http://support.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=&iLanguageID=1&multPartNum=1&sTechX_ID=al_power details what we used to do, vs. what we do now. Also look in section 3 of any datasheet for the Iccint, Iccaux, and Icco current requirements. As of V2, we require that the current provided be at least the quiescent current needed, and no more than that. Austin Adam Megacz wrote: > Austin Lesea <austin@xilinx.com> writes: > >>no power on surge in the core, > > > This sounds interesting; I didn't notice it on the Xilinx site... do > you have a link with more information? > > - aArticle: 73358
Hi, According to AHB protocol ,will the AHB-Slave gives retry only for the first non-seq address from the Master(like my doubt is,can the Slave issue a RETRY even in the middle of a burst of transfer)..Please reply me soon..I am in the middle of my design and i need to take care of this issue....it's pretty urgent... Regards, MackArticle: 73359
I'm just an undergrad student, but I am interested in getting started in some FPGA projects. I would really like to some day build up a usable SoC system to play with. OpenCores.org has been fun site to read through. I envision something with a RISC core, ethernet, usb (HID) and some sort of vga/lvds/dvi. What would be the best way to get started? Can you recommend some software and a EVB for someone learning the basics but wanting to expand over time? Thanks in advance!Article: 73360
Hi Pepper, I'd recommend using a Google Groups search of comp.arch.fpga to find yourself a suitable evaluation board, vga answers, etc. All this stuff gets chatted about on here a lot. You could also look at Xilinx's website; they have a cheap'n'cheerful $99 Spartan-3 board which might be a good start for you. Have fun, Syms. "Pepper Orlando" <woodenbicycle@hotmail.com> wrote in message news:c00eb680.0409200944.59cf7540@posting.google.com... > I'm just an undergrad student, but I am interested in getting started > in some FPGA projects. I would really like to some day build up a > usable SoC system to play with. OpenCores.org has been fun site to > read through. I envision something with a RISC core, ethernet, usb > (HID) and some sort of vga/lvds/dvi. What would be the best way to get > started? Can you recommend some software and a EVB for someone > learning the basics but wanting to expand over time? > Thanks in advance!Article: 73361
But with the Icarus Verilog support of Initial blocks, can't the power-up state be provided exceptionally clean? If the reset is actually used for more than initial states, then the reset is *needed* but if it's just for power-up, are there things that the initial block synthesis support wouldn't cover? "Stephen Williams" <spamtrap@icarus.com> wrote in message news:bff5f$414c5379$40695902$27606@msgid.meganewsservers.com... > Steven K. Knapp wrote: > > > You may be able to remove the user reset completely. Is your user reset > > only to guarantee the initial state of the design (a common ASIC practice)? > > If so, you can eliminate this reset signal, which will potentially make your > > design significantly smaller. > > > > Xilinx FPGAs have an internal Global Set/Reset signal that is asserted at > > the end of the configuration process, guaranteeing the initial conditions. > > This can't be good advice. I have a co-worker who does that often, > and I get to write drivers for the resulting chips. It bugs me a lot. > > Using the configuration process to initialize things to a safe > startup state is nice and all (especially for "roms" and the like) > but RESET is *not* the same thing. > > -- > Steve Williams "The woods are lovely, dark and deep. > steve at icarus.com But I have promises to keep, > http://www.icarus.com and lines to code before I sleep, > http://www.picturel.com And lines to code before I sleep." >Article: 73362
A google search on the quoted "tqfp proto" came up without a hit but had a couple sponsor links that looked like they might fill your needs: www.epboard.com and www.beldynsys.com . I don't have a "preferred supplier" so a proper google search should provide you some answers. "Daragoth" <daragoth@kuririnmail.com> wrote in message news:317379a8.0409180924.34c11ebc@posting.google.com... > "John_H" <johnhandwork@mail.com> wrote in message news:<L642d.14$l1.2394@news-west.eli.net>... > > To make a complete system, what do you have/want for the system clock? Is > > there a need for an on-board oscillator? > > > > What about power? Are you supplying a predetermined external fixed voltage? > > An external voltage to satisfy the FPGA? Several external voltages to match > > the FPGA's every whim? > > > > Are you expecting your I/O to be 5V tolerant/compatible? > > > > These questions and perhaps a few more might be needed to get the fully > > working board. > > > > Another thought might be to get a TQFP prototyping board (or adapter) and > > wire together your own regulators, bypass, and frequency sources. There are > > 100 pin TQFP packages that are pretty small - the support stuff might take > > up the most room. > > > Yeah, I need an onboard oscillator running at a minimum of 4 MHz. > Power is going to be coming from two fixed external sources, one at > 3.43V and another at 5V. > > Where would I be able to find one of these TQFP proto boards? They > sound interesting. Thanks. > > -Darien G.Article: 73363
"rickman" <spamgoeshere4@yahoo.com> wrote in message news:414E757B.4AB4DBDB@yahoo.com... > A piece of code is not really going to help you understand your problem > or how to code in HDL. You need to consider that an HDL is just that, a > Hardware Description Language and *NOT* a software programming > language. I know that not everyone thinks or works like I do, but I > find I fight the language much less if I design my hardware in my head > or on paper and then use the HDL to describe my hardware. > > If you want to do a matrix operation, you really need to design the > hardware to do that, then code that hardware. Just trying to write a > software description of the problem will not in general give you a > reasonable solution in the generated hardware. > > So think about the architecture you expect and then learn how to > describe that hardware in your chosen HDL. Directly translating C to > HDL is not a good way to go. I agree entirely with this, every time I start a new VHDL module the first thing I do is sketch out the hardware on a piece of paper, then write the HDL to describe it. Nial ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design Cyclone Based 'Easy PCI' proto board www.nialstewartdevelopments.co.ukArticle: 73364
I'm using Quartus II and EPM7160SLC. Is there a way to control the power-up state of an lpm_dff register without using an external power-on reset circuit or a state machine? I've tried putting inverters before and after it but they seem to be optimised out. I would like it to power-up with the LSB set and all other bits zero. Thanks, Andrew.Article: 73365
rickman <spamgoeshere4@yahoo.com> wrote in message news:<41488BBA.4B570E72@yahoo.com>... > When it comes to memory, it can be hard to infer it in a way that is > compatible with multiple hardware platforms. well i hope some time soon they make it somehow "standard", cause right now altera just lost (again! cause it's the second time in few months i see it happening) against xilinx, cause the boss said it was already too much trouble having generates for ASIC and for FPGA, to have another one for another family we were just evaluating (we'd need to modify lots of files). And also because we werent seeing any gains in LUTs (the same design was using more LUT4 in altera than on xilinx), nor on speed, Quartus II 3.0 was a lot slower than ISE 5.2. Though Quartus was meeting timing with more slack, i guess ISE 6.3 and Quartus 4.0 are even better. guys! it's time you start doing "standard" things so that code is portable *without* modifications (provided that FPGA families have the same functionality, dual ported RAM, etc. of course!) I use the GENERATE feature > of VHDL to provide separate memory descriptions depending on the > particular chip I am targeting. That way the same files are used for > each different target, you just change the flag telling the software > which chip to target. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 73366
I am trying to follow the Xilinx "Introduction to Programmable Logic". I try to implement in FPGA. But when I try to assign I/O pin in PACE's DOL. I found I can not assign Loc=P36. The drop-down list does not has the entry. I am using Webpack6.2i for Spartan 3. Why?Article: 73367
I'm rather new at Modelsim, so please bear with me. Couldn't find answer to these questions, in manual or in search. I'm running simulation in batch mode. (Currently just using command window, will migrate to Cygwin later.) My batch file is something like this: vlog -lint tb_test.v vsim -c tb_test -wlf test.wlf < test.do So, the simulation runs fine, spits messages, etc. When viewing the waveform, what's the best way to bring up the waves, with the pre-selected signals (or not) without having to open the main Modelsim windows? I find it tedious to open the main window, open the waves, select dataset, then format, especially because I'm in debugging stage where I change the testbench a lot. There has to be a better way than having to go through a series of mouse clicks. I can tolerate the main window opening, as long as I can have the waves show up with signals loaded... am I making sense? Any help would be appreciated.Article: 73368
Hi I wanted to know if Altera Max II was shipping. Altera's website says it is shipping but do not know if the EPM570 is shipping. Any news about it? ThanksArticle: 73369
Does anyone know if it is possible to use the "system monitor" analog inputs as regular A/Ds and use the digital data output from these convertors as inputs to internal logic in the FPGA?Article: 73370
Michael, Yes. The 200Ks/s successive approximation converter eight differential 1 V p-p inputs, as well as the Vccint sense channel, and the temperature sense channel. There are alarm registers for all channels, and various modes it can operate in. Upon power up, before configuration, the A/D is in monitor mode, and outputting data if needed using a JTAG command. The temperature sensor has a shut down feature to prevent operation in excess of the absolute maximum specified ratings. The primary purpose for the A/D is to sense internal voltages, and the die temperature. I don't know how many times you have wanted to know the die temperature, but we need to know that quite often, especially when someone claims that the device is not meeting timing (which it usually is, except they are running it at 110C!). Lots to learn here about what the A/D might be useful for. One application is to detect tampering in security applications, among others. Austin Michael wrote: > Does anyone know if it is possible to use the "system monitor" analog > inputs as regular A/Ds and use the digital data output from these > convertors as inputs to internal logic in the FPGA?Article: 73371
Hi, > I wanted to know if Altera Max II was shipping. Altera's website says > it is shipping but do not know if the EPM570 is shipping. > > Any news about it? All is going well on the engineering front. The EPM1270 is sampling now, and the remaining members (including the EPM570) are scheduled to begin sampling by the begining of 2005. If more precise dates are required, please contact your Altera rep directly. Regards, Paul Leventis Altera Corp.Article: 73372
While the subject is open, Austin why doesn't Xilinx integrate higher performance A/Ds on board. Say 60 Msps, 10 to 12 bits would be nice. Is it a matter of market demand? "Austin Lesea" <austin@xilinx.com> wrote in message news:cino83$k6j1@cliff.xsj.xilinx.com... > Michael, > > Yes. > > The 200Ks/s successive approximation converter eight differential 1 V > p-p inputs, as well as the Vccint sense channel, and the temperature > sense channel. There are alarm registers for all channels, and various > modes it can operate in. Upon power up, before configuration, the A/D > is in monitor mode, and outputting data if needed using a JTAG command. > > The temperature sensor has a shut down feature to prevent operation in > excess of the absolute maximum specified ratings. > > The primary purpose for the A/D is to sense internal voltages, and the > die temperature. I don't know how many times you have wanted to know > the die temperature, but we need to know that quite often, especially > when someone claims that the device is not meeting timing (which it > usually is, except they are running it at 110C!). > > Lots to learn here about what the A/D might be useful for. One > application is to detect tampering in security applications, among others. > > Austin > > Michael wrote: > > Does anyone know if it is possible to use the "system monitor" analog > > inputs as regular A/Ds and use the digital data output from these > > convertors as inputs to internal logic in the FPGA?Article: 73373
Simon Peacock wrote: > > yes and no... older parts can be cheaper..... we are paying about $12 for > our parts... and Spartan 3 maybe cheaper per LUT... but when you don't need > as many as are available.. you are paying for a lot of unused silicon... and > the extra regulator of course... :-) Why would you be paying for unused silicon? Is your design a lot smaller than the smallest S3 part, the XC3S50? If so, then I guess a newer part won't do you any good. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 73374
sebastian wrote: > > rickman <spamgoeshere4@yahoo.com> wrote in message news:<41488BBA.4B570E72@yahoo.com>... > > > When it comes to memory, it can be hard to infer it in a way that is > > compatible with multiple hardware platforms. > > well i hope some time soon they make it somehow "standard", cause > right now altera just lost (again! cause it's the second time in few > months i see it happening) against xilinx, cause the boss said it was > already too much trouble having generates for ASIC and for FPGA, to > have another one for another family we were just evaluating (we'd need > to modify lots of files). There's your problem. Your designs should be done in a modular fashion so that there are common files for memory componets. I have a single file for memory blocks with the required code to infer or instantiate the various memory styles. I select the chip family and select infer vs. instantiate. When I need to add something, I only have one file to modify. Further, additions should not affect any established code, so I don't need to do regression tests. > And also because we werent seeing any gains > in LUTs (the same design was using more LUT4 in altera than on > xilinx), nor on speed, Quartus II 3.0 was a lot slower than ISE 5.2. > Though Quartus was meeting timing with more slack, i guess ISE 6.3 and > Quartus 4.0 are even better. I would not expect any gains in LUTs going from Xilinx to Altera. As you found, often the Xilinx design can use less. But that itself is not the issue since the cost per LUT is not the same. I am not sure what you mean about Quartus being slower. Are you referring to the run time to compile a design? > guys! it's time you start doing "standard" things so that code is > portable *without* modifications (provided that FPGA families have the > same functionality, dual ported RAM, etc. of course!) Many forms of RAM can port between FPGA families. I suggest that you explore the common ground and try to use compatible memory styles. Excluding a vendor based on your coding style keeps you from getting the best price from the remaining vendor. The design I am working on now uses compatible memory even though the Altera ACEX part is targeted. The only thing I can't do in a Xilinx Spartan 3 is the async read of memory. In the Spartan 3 (and most of their other chips) the read requires one clock cycle. That requires changes in other parts of my architecture. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
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