A.
The one i have used in my project is xc2s100 which has 40k bits of blockram
so the module instantiation cannot exceed this address size.
//this is the dualport block ram module instantiation procedure in TOP module
dual_port_blockram dpr( .clk(clk),
.wr(dpw),
.writeadd(dpadd[4:0]),
.readadd(dpread[4:0]),
.datainput(data[7:0]),
.dataout1(dataout1[7:0]),
.dataout2(dataout2[7:0])
);
//and here is the code for the dual port block ram:
module dual_port_blockram(clk,wr,writeadd,readadd,datainput,dataout1,dataout2);
input clk;
input wr;
input [4:0]writeadd;
input [4:0]readadd;
input [7:0]datainput;
output [7:0] dataout1;
output [7:0] dataout2;
reg [7:0] ram [4:0];
reg [4:0] readadd1;
reg [4:0] readadd2;
always @(posedge clk)
begin
if(wr)
ram[writeadd]<=datainput;
readadd1 <= writeadd;
readadd2 <= readadd;
end
assign dataout1 = ram[readadd1];
assign dataout2 = ram[readadd2];
endmodule
// i hope this works fine without any problems if you have any problems
// do contact crash2ash@gmail.com apart from this if you have any
// questions regarding the verilog coding you can contact in this mail id..
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