A. (Lifted from Xilinx's web site, Answer record 8055)
The Verilog and VHDL examples below are for Virtex designs; similar methods
can be used for
other devices. For more information, please consult the Xilinx "Libraries
Guide", Chapter 12 at:
http://toolbox.xilinx.com/docsan/3_1i/docsan.htm
NOTE: Tested in Synplify 5.2.2a and Exemplar 1999.1i
Solution 1:
VHDL LOC example
-- Exemplar and Synplify --
library IEEE;
use IEEE.std_logic_1164.all;
entity flops is port(
di: in std_logic;
ce : in std_logic;
clk: in std_logic;
qo: out std_logic;
rst: in std_logic);
end flops;
architecture inst of flops is
component FDCE port( D: in std_logic;
CE: in std_logic;
C: in std_logic;
CLR: in std_logic;
Q: out std_logic);
end component;
attribute LOC: string;
attribute LOC of U0: label is "CLB_R2C3.S0";
attribute LOC of U1: label is "CLB_R2C4.S0";
attribute LOC of U2: label is "CLB_R6C8.S0";
signal q0,q1 : std_logic;
begin
U0 : FDCE port map(D => di,
CE=> ce,
C => clk,
CLR => rst,
Q => q0);
U1: FDCE port map(D => q0,
CE=> ce,
C => clk,
CLR => rst,
Q => q1);
U2: FDCE port map(D => q1,
CE=> ce,
C => clk,
CLR => rst,
Q => qo);
end inst;
Solution 2:
VHDL RLOC example
-- Exemplar and Synplify --
library IEEE;
use IEEE.std_logic_1164.all;
entity flops is port(
di: in std_logic;
ce : in std_logic;
clk: in std_logic;
qo: out std_logic;
rst: in std_logic);
end flops;
architecture inst of flops is
component FDCE port( D: in std_logic;
CE: in std_logic;
C: in std_logic;
CLR: in std_logic;
Q: out std_logic);
end component;
attribute RLOC: string;
attribute RLOC of U0: label is "R0C0.S0";
attribute RLOC of U1: label is "R0C1.S0";
attribute RLOC of U2: label is "R1C1.S0";
signal q0,q1 : std_logic;
begin
U0 : FDCE port map(D => di,
CE=> ce,
C => clk,
CLR => rst,
Q => q0);
U1: FDCE port map(D => q0,
CE=> ce,
C => clk,
CLR => rst,
Q => q1);
U2: FDCE port map(D => q1,
CE=> ce,
C => clk,
CLR => rst,
Q => qo);
end inst;
Solution 3:
Verilog RLOC Example with Synplify attribute
For Exemplar, replace the attribute with:
examplar attribute <instance_name> rloc <location>
For example:
replace
/*synthesis rloc="r1c0.s0" */
with
/*exemplar attribute u0 rloc r1c0.s0 */
-----------------------------------------------------------
module flops (di, ce, clk, qo, rst);
input di;
input ce;
input clk;
output qo;
input rst;
wire q0, q1;
FDCE u0(.D(di),
.CE(ce),
.C (clk),
.CLR (rst),
.Q (q0))/*synthesis rloc="r0c0.s0" */;
FDCE u1 (.D (q0),
.CE(ce),
.C (clk),
.CLR(rst),
.Q (q1))/* synthesis rloc="r0c0.s1" */;
FDCE u2(.D (q1),
.CE(ce),
.C (clk),
.CLR (rst),
.Q (qo)) /* synthesis rloc="r1c0.s0" */;
endmodule
Solution 4:
Verilog LOC Example using Synplify attribute
For Exemplar, replace the attribute with:
examplar attribute <instance_name> loc <location>
For example:
replace
/*synthesis rloc="r1c0.s0" */
with
/*exemplar attribute u0 rloc r1c0.s0 */
----------------------------------------------------------------
module flops (di, ce, clk, qo, rst);
input di;
input ce;
input clk;
output qo;
input rst;
wire q0, q1;
FDCE u0(.D(di),
.CE(ce),
.C (clk),
.CLR (rst),
.Q (q0))/*synthesis loc="CLB_r2c3.s0" */;
FDCE u1 (.D (q0),
.CE(ce),
.C (clk),
.CLR(rst),
.Q (q1))/* synthesis loc="CLB_r4c5.s1" */;
FDCE u2(.D (q1),
.CE(ce),
.C (clk),
.CLR (rst),
.Q (qo)) /* synthesis loc="CLB_r6c2.s0" */;
endmodule
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