| Vendor | Xilinx/Altera |
| FAQ Entry Author | Ray Andraka |
| FAQ Entry Editor | Philip Freidin |
| FAQ Entry Date | 11/30/2002 |
Q. Can I build adders faster than the adders with Carry chains |
A. (Extracted from one of Ray's Articles, 11/19/2002The reason for doing a carry save adder is to defer the add carry to the lastadder in the tree. Normally this is done in order to permit construction of just one fast adder. The speed of an adder tree is limited by the speed of the propagation through any path in the tree, and the worst case paths are from the lsb of an input to the msb of the output. In other technologies, a ripple carry adder is slower than fancier carry look-ahead schemes, but the fancy schemes take up considerably more logic. By deferring the carry to the last stage, one only has to build one of these expensive adders. The rest of the adders have the same cost as the ripple carry adder but without the ripple propagation. So by doing this, you speed up the adder tree as if all the adders were the more expensive fast adders. Now enter the FPGA, with its dedicated adder carry chains (these actually do have some carry look-ahead built in, but it is hidden from the user). In the case of the FPGA it is very hard, impossible in many cases, to build an adder that is faster than the built in adder function because the dedicated resources are so much faster than the general purpose routing. Since that ripple adder is the fastest one can build in the fpga, there is no penalty (in fact there is an advantage) to using them through out the adder tree rather than only at the final add. The advantage is that by doing this, all the carry logic is put on the dedicated resources, so you essentially get the carry half of all the 3:2 adders for free. If you decided to build an adder without using the chains (including the Carry Save type), you need two LUTs per full adder instead of the one because you can't take advantage of the dedicated carry logic, so not only do you get no speed advantage in an FPGA by using a CSA tree, but you also get soaked for twice the resources, and in fact you get a speed degradation due to the irregular routing. The bottom line is that carry save adder trees DO NOT MAKE SENSE for FPGAs that have dedicated adder resources. |