The Unsorted, Unformatted FPGA FAQ

Last updated 12/08/2009

For VHDL questions you should probably first look in the VHDL-FAQ first

For Verilog questions you should probably first look in the Verilog-FAQ first

There are also news groups for both languages: comp.lang.vhdl and comp.lang.verilog
which you access the same way you access comp.arch.fpga

0001    JTAG Config
0002    DONE Pin Stuff (not yet done, looking for volunteers)
0003    Understanding Serial Config (not yet done, looking for volunteers)
0004    Global Clock Nets (not yet done, looking for volunteers)
0005    FloorPlanning (not yet done, looking for volunteers)
0006    Understanding The Bitstream Format for Parallel Configuration
0007    What is the difference between FPGAs and CPLDs
0008    How do I instantiate Block RAMS
0009    Which products are supported each version of Xilinx software
0010    How doI do RLOCs with VHDL
0011    Howdo I do RLOCs with Verilog
0012    How do I implement DES (a link to a Xilinx App note)
0013    How do I implement RIJNDAEL (A link to Nicholas Weavers page that describes his implementation (quite fast too))
0014    How do I choose between Xilinx and Altera
0015    What editors have language sensitive coloring
0016    Wired AND/OR
0017    Tell me about Metastables
0018    Divide an integer by N.5
0019    Divide a clock by N.5
0020    FPGA based CPUs (not yet done, looking for volunteers)
0021    How can I back a Windows NT 4 system, including the registry
0022    How many permutations can a 4LUT have
0023    Clocking RAMS and Flip Flops
0024    Schematics vs Verilog/VHDL
0025    Tell me about the MCS file format
0026    Tell me about bit files
0027    Creating PCB symbols for FPGAs using ORCAD
0028    Downloading a Bitstream under Linux
0030    How to initialize SRL16E
0031    How to initialize Block RAM
0032    Tell me about decoupling and bypass capacitors ( a link to a Xilinx App note)
0033    How fast can an FPGA go ( a link to a Xilinx App note where some of the logic runs at 644 MHz)
0034    Can I build adders faster than the adders with Carry chains
0035    Can I use wirewrap with FPGAs
0036    Configuring an FPGA with a cheap serial EPROM and a PIC processor
0037    Building a crystal oscillator with an FPGA (not yet done, looking for volunteers)
0038    Configuring an FPGA from a processor
0039    Switching clocks without glitches
0040    Startup Power Consumption(A link to a Xilinx App note that discusses startup power for Spartan-II and Spartan-IIE devices)
0041    How do I design FIFOs (not yet done, looking for volunteers)
0042    Issues for prototyping ASICs with FPGAs
0043    Steps to make a Printed Circuit Board (PCB)
0044    How to get the Xilinx parallel cable to work on Linux kernels 2.6.x

If you would like to write any of the above pages that are looking for volunteers, please
download a copy of an empty template , and fill it in.

Email it to the maintainer of FPGA-FAQ at

      philip.freidin A T  fpga-faq.org

for publication.

Thanks.