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On Jan 22, 5:14=A0am, Florian Stock <st...@esa.informatik.tu- darmstadt.de> wrote: > whygee <why...@yg.yg> writes: > > rickman wrote: > >> On Jan 21, 12:45 pm, whygee <why...@yg.yg> wrote: > >>> OTOH has anybody read about the "upcoming" memristor-based FPGA ? > >> No, I have not read about this. =A0But the stuff I have read about > >> memristors indicates they are some years away from commercial > > > Xilinx seems to use to buy things and swallow companies, > > maybe they'll get a hint and speed things up this way ? > > Xilinx is maybe big, but the memristor stuff came from HP, I think they > cant buy them (maybe they cooperate). Another =A0big thing HP announced > was "field programmable nanowire interconnect" - nanowire crossbar to > connect everything, would reduce the size by 95% (but also no commercial > application up to now). Did HP claim that it would reduce the size of the interconnect by 95%? They have to provide ways of controlling each crossbar interconnect. That is not free in terms of real estate. Also, if they are going to design with local routing, there will need to be a way to control each segment individually. I am sure it will be more compact than the current configuration storage/pass transistor, but I doubt that it will be 95% smaller. A lot of the routing is just that, routing, and that does not get any smaller at all. I haven't heard any details, but I am expecting the advantage to be more in the area of speed. I believe the transistors are a significant part of routing delay. I would expect the simple structure of the memristor to have less parasitics and be a lot faster, but only time will tell. The real paradigm shift with memristors may be the ability to self- reconfigure. SRAM can also do this, but only in the LUTs. The interconnect is still fixed unless the parts are actually reconfigured from PROM. The memristor will make it easier for circuits to completely reconfigure themselves based purely on data processing. It may open a whole new area of research for reconfigurable computing. Knowing HP, I expect any FPGA they come up with will not be another 4- LUT based device. It will have an architecture that will allow some new ways of using FPGAs. RickArticle: 137576
I think they could sell very well. in an ongoing battle, i had tried the INCLUDE_IO=0 solution from page 121 in XPS_LL_TEMAC.PDF after trying to connect the clock in 8 different ways and always getting errors, I had no choice as to run XILDECOMP.EXE on the encrypted sources. and of course,the INCLUDE_IO parameter is not at all used in the SGMII module wrapper so whatever i did had to fail this is not yet reason to hit the sack, but the story before this is bad enough to make one really mad at times AnttiArticle: 137577
Respected Sir, In my Partial reconfiguration design, 'clk' and 'dataclk' are the two clocks going to both 'static' and reconfigurable' modules. Can you please guide me on what to write in UCF file to declare them as GLOBAL CLOCKS. Thanking You Regards Rishi MathurArticle: 137578
On Jan 15, 2:15=A0pm, Antti <Antti.Luk...@googlemail.com> wrote: > Hi > > so here are rewards: > > 500EUR for the IP core fix (other then increase the timeouts what > didnt fix the problem) > > 250EUR for the fix to properly restart the DMA engine so that it can > continue after being > stopped by software > > the rewards are valid as long as i have not solved the problem. > if i get it working myself i will immediatly post tat c.a.f. > > the solution has to be applicable for MPMC2 v 1.9 > > upgrade of the complete system to MPMC3 is not an option > (we do not have the time) > > Antti Lukats > who does want to move on, and not to fight with Xilinx bugs any more. WITHDRAWN i have fully given up trying to get the MPMC2 ever work we are migrating to MPMC3 but unfortunatly there are 2 different FULL SHOWSTOPPER type of issues with the MPCM3 releated to XPS_LL_TEMAC in SGMII mode the issues will be fixed in 11.1 tools but we do not have the time to wait that long :( AnttiArticle: 137579
On Jan 5, 9:37=A0am, Antti <Antti.Luk...@googlemail.com> wrote: > On Jan 4, 10:54=A0pm, hal-use...@ip-64-139-1-69.sjc.megapath.net (Hal > > > > Murray) wrote: > > >a few days ago i had a "ISSUE LIST" in excel table > > >where i note the possible issues, their probability, methods of > > >testing, etc.. > > > >the table had 26 items. > > > >but one VERY important item was missing, > > >something that should always be on the list: > > > >"stupid software bug" > > > Don't overlook the smart software bugs. > > > Many years ago, as a project was wrapping up, I made a list of the > > places where a bug could come from. =A0I wish I had saved a copy. > > > The list included > > =A0 bugs in microcode > > =A0 bugs in microcode assembler > > =A0 bugs in data sheet > > > The one that I would have missed if I hadn't done it: > > =A0 bugs in my reading of a datasheet > > > -- > > These are my opinions, not necessarily my employer's. =A0I hate spam. > > LOL > > it took me 2 minutes to understand it. > > right! > > * stupid software bug (already on the list) > * smart software bug (not yet on the list) > > thanks! :) > Antti > PS this time it is the stupid bug, but sometimes it would the other > one after lots of more fight with the problem, excluding many possible causes i have come to conclusion that the only answer to the quiz would be single word XILINX the bug is somewhere there, and i leave it so. all attempts to fix it, or fix the results of it, or reaarange the system in the attempt to prevent the issue have failed Antti who usually does not give up so easily on technical problemsArticle: 137580
Hi, I encount problems when I download Xilinx ISE 10.1. When I go through with its default selection, it choses proxy mode (The 2nd of the three options). The error is: Read Operation Failed If I select direct Internet connection, the following error pops up: The following error was encounted during installation: 11:Archive could not be allocated.. I don't know how to deal with it. Could you help me? Thanks a lot.Article: 137581
On Jan 22, 12:49 pm, fl <rxjw...@gmail.com> wrote: > Hi, > I encount problems when I download Xilinx ISE 10.1. When I go through > with its default selection, it choses proxy mode (The 2nd of the three > options). The error is: > > Read Operation Failed > > If I select direct Internet connection, the following error pops up: > > The following error was encounted during installation: > 11:Archive could not be allocated.. > > I don't know how to deal with it. Could you help me? Thanks a lot. the first thing you need to do is not install directly from the internet. you should choose to store all the install files to a separate directory first, and then launch the installer from there.Article: 137582
Hi, im working with XPS and I'm trying to write my own dcr slave. Right now I'm almost done with the hardware. But what I don't really get is how do I access the DCR register when I make the PPC the dcr master. What is better to use the xilinx routines Xio_dcrIn and Xio_dcrOut. Also on some places I saw people using some kind of inline assembler macros. like mtdcr and mfdcr. If someone has an working example would be awesome. Thanks for the help. SebastianArticle: 137583
Jim Lewis a écrit : > maverick >> Hi, >> I am trying to program Xilinx Virtex-5 PCI Express Development kit >> with Digilent USB programming cable with Digilent suuported >> programming software. So far I have not been able to program the FPGA. >> Does this cable or the software suuport Virtex5 series FPGA? Is there >> a link to those listed FPGA devices supported by Digilent USB cable >> and accompanied software ? >> >> >> Thanks > > Have you tried contacting digilent at support@digilentinc.com? > I would suspect that their software only supports Digilent boards. Hi I don't which of their software you're talking about. I'm using their configuration tool (can't remember its name at the moment) with their USB cable to configure a custom board with an XC3S250E without any problem. NicolasArticle: 137584
rickman wrote: > On Jan 22, 1:00 am, whygee <why...@yg.yg> wrote: >> Hi :-) <snip> >> I'm interested to read and compare numbers from different FPGA familie= s >> for 8, 16 and 32-bit wide adders (latency, area cost etc.). >=20 > Xilinx used to publish numbers for a few basic functions in their data > sheets, but I don't see that in the current ones. But I can tell you > that the propagation delay for the carry chain is on the order of 0.1 > to 0.2 ns per bit. The input to the carry chain and carry output take > a few ns, but the incremental delay per bit is very low. Odd that > they don't even publish that number in the current data sheet. that's curious. maybe the new technologies are so variable that they count on the user to submit the design to their SW and find the real values ? > Altera > and Lattice are comparable. In fact, the Lattice parts use a *very* > similar design as they have the rights to many of the Xilinx basic > patents from buying the Lucent Orca line which used the patent rights > Lucent bought from Xilinx as part of a second source agreement. that's an excellent information to know, which explains why Lattice seems to perform quite well. Gr=FCsse aus Paris, > Rick yg --=20 http://ygdes.com / http://yasep.orgArticle: 137585
Hi again :-)
rickman wrote:
> On Jan 21, 9:15 pm, whygee <why...@yg.yg> wrote:
>> Hi Rick !
>> rickman wrote:
>>> Have you considered a different family?
>> I'm already satisfied with what I got from Actel
>> ("it works and has what i want")
>> and I bet that any issue I'll have with SDRAMs
>> will not be related to the FPGA family itself,
<snip>
> I am of the opinion that with the top three FPGA vendors, Xilinx,
> Altera and Lattice, there is not a lot to "evaluate".
that is one of my worries, an old one indeed.
lack of choice, capture of the design into a vendor's "ecosystem"
and the long-term consequences. That's why I was so reluctant
to their products during so many years. Fortunately,
things change, even me.
> Each vendor has
> at least one high end line that is fast, dense and has lots of bells
> and whistles. They also have at least one line of economy chips that
> are cheap and yet still very capable. Unless you are planning to push
> the limitations of any of these chips, what is there to evaluate?
how fast, easy, cheap and not alienating their tools are.
I recently did a review of the market and I'm still not joyful.
However surprises may happen and I want to be there when it happens.
> I didn't get the impression that this is about a product,
not yet. There are too many variables to take into account,
and my money making activities are often more than satisfied
with an under-used PIC. I prepare for the distant, better future.
> so if you are
> just using this as a learning tool, what basis do you have for
> evaluation? What is your criteria?
I guess that you will not like my answer, but what about
"I see if I like it, if it "speaks" to me, if I understand its perspective..."
Yes, it's completely subjective but sometimes it's not possible
to name coherent criteria when they collide /but/ there is still
freedom to balance them.
> I know that I would choose the
> device that is easiest to prototype with and later worry about that
> device I want to use in a product.
prototyping ease is essential.
then there are countless other... parameters.
> BTW, when you say you have no support tools for the Altera device, I
> think i told you that the Altera FPGA tools are available free.
you did.
I just wasn't happy with Altera's policies and other details
so it put this issue on hold. There are other vendors to "evaluate"
and that have less constraining methods.
>>> You can clock an SDRAM as slow as you want to some
>>> point. You do have to provide a periodic refresh cycle unless you are
>>> doing that in software. But the clock speed won't have much to do
>>> with the SI and power decoupling issues.
>>
>> <afterthought>
>>
>> And if the SDRAM can be clocked as slowly as one wants,
>> then I could even "prototype" the SDRAM interface
>> with "bitbang"-like software, and then move slowly from
>> soft to VHDL as it starts to work...
>
> That will be interesting. There are limits to how slow it can run,
> check the data sheet.
of course.
> The initialization is not all that bad, at
> least if you are using SDRAM. I did one of those some 10 years ago.
> I just made a FSM and it worked the first time.
Either you're lucky, or you're very good, or SDRAM is less
complex than I thought ;-)
> I did find a lot of
> good app notes and data sheets at Micron Semi. I don't know if they
> are still available. I have them in print form. 8^*
I'll go hunting datasheets when I feel courageous enough.
Meanwhile, I decided to make a major rework of the yasep.org website,
my JavaScript vice is biting me hard at this moment :-/
>>> If you are interested in MISC processors,
>>> comp.lang.forth is a good place.
>> :-)
>> However YASEP is not MISC, it's just "small" :-)
>> But Forth and the likes are definitely worth caring.
>
> YASEP... Yet Another Small Embedded Processor? I feel the same way
> about mine.
that's funny :-)
is it available online ? do you have any documentation about it ?
> I designed a CPU some 8 years ago based on the Forth
> model. It turned out remarkably similar to Bernd Paysan's b16, but
> with very different instruction format. From the work I have done, it
> appears that the data path will dominate the size of the design. Then
> the efficiency is determined by how well your instruction set uses
> parallelism in the data path.
That does not scare me...
> There is a lot to learn by working with someone else's design.
sure.
> I guess I am saying you can learn a lot more from someone else than you
> can by yourself.
I have examined countless architectures. Besides the PCs that I know
quite deeply, I have many other machines and families, either as
chips, machines, book, archives... I won't list them.
I have learnt a lot in the past 15 years but even with VHDL simulators,
I was missing real hardware interactions.
And experience is better when you get it yourself, get your own fingers
burnt etc.
>>> The [Altera] programming cable is not a lot of money.
>> I consider making my own,
>> once I have time and all the SW issues solved.
> I'll let this whole can of worms alone.
One more reason to let Altera at the bottom of my priority list.
> There is another thread about
> using Windows or more specifically, Vista. It is getting long winded
> and the more radical elements are coming out.
The Vista thread is interesting as it shows several cultural drifts.
I do my best to keep my dependence from M$ as low as possible.
I'm now seriously considering a SPI-only interface and
I've found some platforms that allow one to avoid proprietary
JTAG interfaces. And a SPI interface is as easy as bitbanging
on the parallel printer port on any PC (even recent ones,
just not from the local supermarket).
>> It looks like a "dirty hack" with 25mil wires from IDE cables
>> is the fastest, cheapest and easiest way now.
>> Maybe it won't work but it will probably help me
>> understand and get a first foot in the sh^Wmatter...
>
> Man, you *are* a masochist! Good luck.
thanks ;-)
I'll take pictures of whatever comes out, whenever it does.
I'd like to do something basic and easy, tonight.
>> http://yasep.org
> I took a look. I'm just curious, why are you designing your own processor?
Some answers are there : http://yasep.org/docs/vsp05.txt (this is OLD).
Maybe http://yasep.org/docs/yasep.html is not enough and should be
supplemented. However, contrary to the F-CPU era, I now prefer
to design, experiment, etc. instead of constantly justifying myself.
It always takes too much time, energy etc. and in the end,
everyone is sour. I don't want this, so there is not even a forum
or a mailing list that will distract me. It's personal.
And Usenet is a wild weird place too, and I don't want to troll.
> I assume you are aware that there are literally dozens of
> other processors out there... hence the name.
then... why are there "only" dozens ? :-)
and why did you design yours ?
and why why...
too many questions, too little fun :-/
best regards and thanks for all the insights,
> Rick
yg
--
http://ygdes.com / http://yasep.org
Article: 137586Florian Stock wrote: > Xilinx is maybe big, but the memristor stuff came from HP, I think they > cant buy them (maybe they cooperate). Another big thing HP announced > was "field programmable nanowire interconnect" - nanowire crossbar to > connect everything, would reduce the size by 95% (but also no commercial > application up to now). stop making me salivate ;-) > Florian yg -- http://ygdes.com / http://yasep.orgArticle: 137587
Hello everyone. I'm a newbie with Altera. So I'm looking for someone who can answer that question. As for Xilinx, From Virtex pro can support Floating point operators.Article: 137588
KJ <lkjrsy@gmail.com> wrote: > I'm a newbie with Altera. So I'm looking for someone who can answer > that question. > As for Xilinx, From Virtex pro can support Floating point operators. Either Altera or Xilinx FPGAs can do floating point, but it takes a lot of cells to do. Also, often adders are bigger than multipliers, as the prenormalization and postnormalization for an adder (or subtracter) are big. If you can do fixed point, (or scaled fixed point) even if the width is larger, it may be a lot smaller and faster. -- glenArticle: 137589
Hal Murray wrote: >> I'm interested to read and compare numbers from different FPGA families >> for 8, 16 and 32-bit wide adders (latency, area cost etc.). > > You could build your own. Just make a list of whatever you want > and make a design with an example. Try it on any family you are > curious enough about to invest the time. I only have Actel available :-/ And addition with the A3P is ... quite slow. However I deal with it, and I accept Actel's justification : a netlist designed with their tool is much closer to the behaviour in a "standard gates" ASIS (hence the name). Whether it's the most efficient and the best of all worlds is another debate (in which I don't want to be involved). > I think the reason that stuff dropped out of advertising is that > dedicated carry logic makes them faster than lots of other logic > so who cares. The hard/slow part is probably routing the data > over to the adder. It seems so. -- http://ygdes.com / http://yasep.orgArticle: 137590
John Adair wrote: > I'm not sure if you just want a module with 2.54mm pins or a > development board with SDRAM but we can offer both. > > For a module we dil header style SDRAM modules. These are out of stock > just now but should be available in a few weeks. These modules are > aimed at our Raggedstone range range of boards. > > In the development board area we have Darnaw1 http://www.enterpoint.co.uk/moelbryn/darnaw1.html > which currently has 128Mbit SDRAM on as standard but we have a batch > going through shortly where we are looking at increasing the SDRAM and > SPI Flash sizes on the XC3S1600E versions. > > There is also a new product coming that is very much aimed at > microprocessor applications based in FPGA and that will have 256Mbit > SDRAM in a X32 organisation and has capability to go to 512Mbit. I'm > expecting to announce this properly in 3-4 weeks time when have run > some tests on it. thank you, i'll have a look :-) > John Adair > Enterpoint td. YG -- http://ygdes.com / http://yasep.orgArticle: 137591
hi ! rickman wrote: > Just don't even go there. For all practical purposes, changing the > diameter will have no noticeable effect in this situation. Don't > encourage the guy! hummm... not even to test the principle before making a PCB ? -- http://ygdes.com / http://yasep.orgArticle: 137592
"whygee" <whygee@yg.yg> wrote in message news:49780cf9$0$28668$7a628cd7@news.club-internet.fr... > Marty Ryba wrote: >> The other new potential player in the game is Achronix > I've seen that, too. > actually, only the website. > I would be very curious to see how this unfolds. > I hope that it's not "yet another promising technology > that fails for whatever reason like most precedent ones"... > only those that succeed, or fail miserably, are remembered :-/ True. For me, I see it as hedging my bets since I'm not sure the TMR-based approaches being worked via the Xilinx consortium will survive my orbit environment (among the worst cases out there). So, I need the Achronix framework to succeed, and the radiation hardening to work too (or not die for lack of funds). > Concerning Achronix, there is no mention or detail > concerning the design/development environment, > can you tell us anything about this, the requirements, > the tools, etc. ? I don't have direct experience; we're at the early prototyping stage using COTS Xilinx-based boards. The web site says that you build a standard EDIF netlist using Synplify or similar (I guess they give you some design support files), then put that through their P&R and programming tools which also support Modelsim (and a couple others) for post-P&R simulation. That sounds a lot like my current tool flow (Modelsim, Synplify Pro, then to ISE). We'll see... -Marty (physicist/systems engineer masquerading as a EE)Article: 137593
whygee <whygee@yg.yg> wrote: > rickman wrote: >> Just don't even go there. For all practical purposes, changing the >> diameter will have no noticeable effect in this situation. Don't >> encourage the guy! > hummm... > not even to test the principle before making a PCB ? I agree that one should know what one is doing before designing a PC board. Believing that width doesn't matter and using very narrow traces isn't a good start, though. -- glenArticle: 137594
Hi all, I need to generate a squarewave in increments of 2 Hz.(Accuracy should be 1Hz). I thought I use a PIC18 and a AD9833 but I keep thinking about the MAX3000A. I think the implementation should be simpler on it but I just can't get started thinking that it is not going to work. I thought I use an external oscillator and divide the freq. down (with the MAX3000A) to what a set of BCD (8 to 12 bits) switches are set to. Last time I use a MAX3000A I drew the schematic but this time I thought Verilog HDL would seem simpler. Any thought on it? Comments/suggestions welcome. ThanksArticle: 137595
On Jan 22, 1:06=A0pm, jleslie48 <j...@jonathanleslie.com> wrote: > On Jan 22, 12:49 pm, fl <rxjw...@gmail.com> wrote: > > > Hi, > > I encount problems when I download Xilinx ISE 10.1. When I go through > > with its default selection, it choses proxy mode (The 2nd of the three > > options). The error is: > > > Read Operation Failed > > > If I select direct Internet connection, the following error pops up: > > > The following error was encounted during installation: > > 11:Archive could not be allocated.. > > > I don't know how to deal with it. Could you help me? Thanks a lot. > > the first thing you need to do is not install directly from the > internet. you should choose to store all the install files to a > separate directory first, > and then launch the installer from there. Another note. The downloads on the Xilinx website all direct you to use an installer program (usually a 47 MB download itself). The alternative is to "download files individually" which bypasses the Xilinx downloader and allows you to download the install archive, usually a single zip or tar.gz file of 1 to 2 GB. Since the download server does not use FTP, you need a clean connection to avoid errors causing you to restart the entire process. This has been noted on the Xilinx forums and many people are annoyed by it. Xilinx responded that their http based downloader works better to serve large numbers of downloads. Often your best choice is to request a CD or DVD by mail, especially if your Internet connection is not blazing fast. Good luck, GaborArticle: 137596
I have a new design with a XCS05 based on a well proved design where the fpga runs during few minutes and then fails while expulses an extrange substance from inside the VCC and GND pins, in some pads is like spounge-white in other is black, the chip runs cold, never warms up. I have a lot of experience on this chip and I have never seen that. Then the chip appears to have a few inputs crossed to GND and worked never more. We crossed all the VCC pads with wire-wrapping with no results, no current loops. The prototype worked well (this is the first series PCB). Any Idea?Article: 137597
Thanks all! I'm looking xio.h and xparameters.h files. This morning I'll try to write and read sram... I hope to achieve a good result. Daniele P.s.: Kappa anche io sono italiano, non vorrei disturbarti eccessivamente nè investirti del ruolo di docente, ma se dovessi avere dei problemi posso far affidamento su di te? Ho iniziato ad affacciarmi al mondo degli FPGA da pochissimo (2 mesi) e dopo uno sguardo iniziale a manuali di VHDL e a semplicissimi tutorials sto cercando di entrare nella filosofia del campo. Sto operando su una piattaforma ML505 e sto cercando di prendere dimestichezza con i vari bus, periferiche (buttons,switches,leds,memories...) Intanto ti ringrazio per l'indirizzamento. Saluti!Article: 137598
it seems that first references to the upcoming Spartan family are in the wild already http://www.linkedin.com/in/ericschristiansen I assume the spartan-6 mentioned there is not a typo (actually i am almost sure it isnt) AnttiArticle: 137599
#include "xparameters.h"
#include "stdio.h"
#include "xutil.h"
#include "fsl.h"
#include "xgpio_l.h"
#include "xio.h"
//====================================================
int main (void) {
Xuint32 segnale,Data,Data1,sum;
int i;
print("-- Inizo main() --\r\n\n");
do{
//riceve il primo valore dai dip switches
print("Digitare il primo dato attraverso i dip switches\r\n e premere un
push button per confermare\r\n\n");
do{
segnale = XGpio_mGetDataReg (XPAR_PUSH_BUTTONS_5BIT_BASEADDR, 1);
Data = XGpio_mGetDataReg (XPAR_DIP_SWITCHES_8BIT_BASEADDR,1);
}while(segnale == 0);
xil_printf("Dato letto da DIP_Switches_8Bit: 0x%x\r\n\n", Data);
// ciclo di ritardo per rilasciare gli switch
xio_out32(XPAR_SRAM_MEM0_BASEADDR,Data);
..
I COMPILED THE CODE AND THE RESULT IS:
Building target: TestApp_Memory.elf
mb-gcc -o TestApp_Memory.elf TestApp_Memory.o -mno-xl-soft-mul
-mxl-pattern-compare -mcpu=v7.10.a
-L../../microblaze_0_sw_platform/microblaze_0/lib -xl-mode-executable
-T../../../TestApp_Memory/src/TestApp_Memory_LinkScr.ld
TestApp_Memory.o: In function `main':
/cygdrive/c/da_cancellare/SDK_projects/TestApp_Memory/Debug/../../../TestApp_Memory/src/TestApp_Memory.c:53:
undefined reference to `xio_out32'
/cygdrive/c/da_cancellare/SDK_projects/TestApp_Memory/Debug/../../../TestApp_Memory/src/TestApp_Memory.c:60:
undefined reference to `xio_in32'
collect2: ld returned 1 exit status
make: *** [TestApp_Memory.elf] Error 1
Build complete for project TestApp_Memory
WHAT'S WRONG?
Thanks...
Daniele
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