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Threads Starting Jan 2007
113978: 07/01/01: SunLei: help on Xilinx USB download cable
113992: 07/01/02: Andreas Ehliar: Re: help on Xilinx USB download cable
114024: 07/01/03: SunLei: Re: help on Xilinx USB download cable
113981: 07/01/01: Rick North: PPC PLB <=> FPGA fabric
113982: 07/01/01: Ben Jackson: Re: PPC PLB <=> FPGA fabric
114004: 07/01/02: Siva Velusamy: Re: PPC PLB <=> FPGA fabric
114021: 07/01/02: Jeff Cunningham: Re: PPC PLB <=> FPGA fabric
114062: 07/01/03: Peter Ryser: Re: PPC PLB <=> FPGA fabric
113985: 07/01/02: <smount>: Surface mount ic's
113988: 07/01/02: David R Brooks: Re: Surface mount ic's
113990: 07/01/02: Jonathan Bromley: Re: Surface mount ic's
114027: 07/01/03: David R Brooks: Re: Surface mount ic's
114000: 07/01/02: <smount>: Re: Surface mount ic's
113993: 07/01/02: Symon: Re: Surface mount ic's
114008: 07/01/02: DJ Delorie: Re: Surface mount ic's
114013: 07/01/02: James T. White: Re: Surface mount ic's
114016: 07/01/02: DJ Delorie: Re: Surface mount ic's
114031: 07/01/03: Symon: OT. Re: Surface mount ic's
114082: 07/01/04: Symon: Re: OT. Re: Surface mount ic's
114085: 07/01/04: Jonathan Bromley: Re: OT. Re: Surface mount ic's
114097: 07/01/04: Ben Jones: Re: OT. Re: Surface mount ic's
114117: 07/01/04: Bob Perlman: Re: OT. Re: Surface mount ic's
114065: 07/01/03: Bob Perlman: Re: Surface mount ic's
114089: 07/01/04: Jonathan Bromley: Re: Surface mount ic's
114136: 07/01/05: Brian Drummond: Re: Surface mount ic's
114159: 07/01/05: Philip Freidin: Re: Surface mount ic's
114166: 07/01/06: Tim: Re: Surface mount ic's
114425: 07/01/15: Tim: Re: Surface mount ic's
114717: 07/01/23: <pbgbbrsh@ludd.invalid>: Re: Surface mount ic's
114721: 07/01/23: Jan Panteltje: Re: Surface mount ic's
114739: 07/01/23: <pbFJKD@ludd.invalid>: Re: Surface mount ic's
114771: 07/01/24: David R Brooks: Re: Surface mount ic's
114774: 07/01/24: <pbFJKD@ludd.invalid>: Re: Surface mount ic's
114783: 07/01/24: Jan Panteltje: Re: Surface mount ic's
113994: 07/01/02: PeteS: Re: Surface mount ic's
114007: 07/01/02: Dave Pollum: Re: Surface mount ic's
114033: 07/01/03: Guru: Re: OT. Re: Surface mount ic's
114036: 07/01/03: <homelab@hotmail.co.uk>: Re: OT. Re: Surface mount ic's
114038: 07/01/03: Dave Pollum: Re: OT. Re: Surface mount ic's
114042: 07/01/03: Tim: Re: Surface mount ic's
114051: 07/01/03: Jon Elson: Re: Surface mount ic's
114066: 07/01/03: Brian Davis: OT. Re: Surface mount ic's
114079: 07/01/04: vasile: Re: Surface mount ic's
114086: 07/01/04: Brian Davis: Re: OT. Re: Surface mount ic's
114087: 07/01/04: Dave Pollum: Re: Surface mount ic's
114116: 07/01/04: Andy Peters: Re: Surface mount ic's
114192: 07/01/06: John McCaskill: Re: Surface mount ic's
114477: 07/01/17: matt.oppenheim@gmail.com: Re: Surface mount ic's
113995: 07/01/02: quad: Bitstream programming
114040: 07/01/03: Koen Van Renterghem: Re: Bitstream programming
113997: 07/01/02: colin: lead free bga pads
114002: 07/01/02: PeteS: Re: lead free bga pads
114084: 07/01/04: Symon: Re: lead free bga pads
114115: 07/01/04: PeteS: Re: lead free bga pads
114135: 07/01/05: Symon: Re: lead free bga pads
114153: 07/01/05: PeteS: Re: lead free bga pads
114174: 07/01/06: Symon: Re: lead free bga pads
114072: 07/01/04: colin: Re: lead free bga pads
113998: 07/01/02: Ulrich Bangert: Strange JTAG TCK problems with Spartan XC3S400
114001: 07/01/02: Dave Pollum: Re: Strange JTAG TCK problems with Spartan XC3S400
114009: 07/01/02: Fred: ISE Simulator radix question
114012: 07/01/02: Mike Treseler: Re: ISE Simulator radix question
114014: 07/01/02: Fred: Re: ISE Simulator radix question
114045: 07/01/03: Xiaqing Wu: Re: ISE Simulator radix question
114261: 07/01/09: Fred: Re: ISE Simulator radix question
114168: 07/01/05: Duth: Re: ISE Simulator radix question
114262: 07/01/09: Fred: Re: ISE Simulator radix question
114010: 07/01/02: Tom J: Xilinx: Connecting an on-chip memory-like component to Microblaze
114011: 07/01/02: Tom J: Re: Xilinx: Connecting an on-chip memory-like component to Microblaze
114017: 07/01/02: Siva Velusamy: Re: Xilinx: Connecting an on-chip memory-like component to Microblaze
114047: 07/01/03: Siva Velusamy: Re: Xilinx: Connecting an on-chip memory-like component to Microblaze
114019: 07/01/02: Jeff Cunningham: Re: Xilinx: Connecting an on-chip memory-like component to Microblaze
114041: 07/01/03: Tom J: Re: Xilinx: Connecting an on-chip memory-like component to Microblaze
114048: 07/01/03: Tom J: Re: Xilinx: Connecting an on-chip memory-like component to Microblaze
114056: 07/01/03: Tom J: Re: Xilinx: Connecting an on-chip memory-like component to Microblaze
114098: 07/01/04: Tom J: Re: Xilinx: Connecting an on-chip memory-like component to Microblaze
114018: 07/01/02: Eric Smith: EDK 8.2 bidir gpio in XBD (board definition)
114071: 07/01/03: Eric Smith: Re: EDK 8.2 bidir gpio in XBD (board definition)
114026: 07/01/02: <camel_1213@yahoo.com>: Wishbone I2C Application
114028: 07/01/03: Daniel O'Connor: Re: Xilinx ISE 8.2.3 - Re-Creating Projects
114029: 07/01/03: jerzy.gbur@gmail.com: Re: Memory controller design
114030: 07/01/03: Pablo: FPGA-CPU THROUG ETHERNET
114032: 07/01/03: Jon Beniston: Re: FPGA-CPU THROUG ETHERNET
114111: 07/01/04: Venu: Re: FPGA-CPU THROUG ETHERNET
114034: 07/01/03: Guru: PPC cache errata
114037: 07/01/03: cpmetz@googlemail.com: Re: PPC cache errata
114046: 07/01/03: Ben Jackson: Re: PPC cache errata
114139: 07/01/05: Brian Drummond: Re: PPC cache errata
114061: 07/01/03: Peter Ryser: Re: PPC cache errata
114063: 07/01/03: Erik Widding: Re: PPC cache errata
114073: 07/01/04: Guru: Re: PPC cache errata
114075: 07/01/04: cpmetz@googlemail.com: Re: PPC cache errata
114099: 07/01/04: Guru: Re: PPC cache errata
114110: 07/01/04: Erik Widding: Re: PPC cache errata
114138: 07/01/05: cpmetz@googlemail.com: Re: PPC cache errata
114039: 07/01/03: jetq88: Spartan3 XC3S400 won't work after upgrading ISE from ISE6.3 to ISE8.2
114043: 07/01/03: bjzhangwn@gmail.com: Re: Spartan3 XC3S400 won't work after upgrading ISE from ISE6.3 to ISE8.2
114044: 07/01/03: jjlindula@hotmail.com: Using Altera's SerialLite to create a high-speed data link between Two or more FPGA's
114095: 07/01/04: jjlindula@hotmail.com: Re: Using Altera's SerialLite to create a high-speed data link between Two or more FPGA's
114049: 07/01/03: cpope: xilinx spi example under linux
114069: 07/01/03: Peter Ryser: Re: xilinx spi example under linux
155917: 13/10/16: <orly.bialer@me.com>: Re: xilinx spi example under linux
156279: 14/02/04: selvance: RE: xilinx spi example under linux
114050: 07/01/03: nana: Chipscope
114090: 07/01/04: SunLei: Re: Chipscope
114052: 07/01/03: Olivier Scalbert: newbie needs help
114054: 07/01/03: Peter Alfke: Re: newbie needs help
114055: 07/01/03: John_H: Re: newbie needs help
114057: 07/01/03: PeteS: Re: newbie needs help
114104: 07/01/04: Olivier Scalbert: Re: newbie needs help
114078: 07/01/04: Olivier Scalbert: Re: newbie needs help
114088: 07/01/04: Jonathan Bromley: Re: newbie needs help
114105: 07/01/04: Olivier Scalbert: Re: newbie needs help
114053: 07/01/03: <dcaulfield@lowtechsolutions.net>: Mapper using wrong EMAC with PowerPC in V4FX60
114060: 07/01/03: leevv: Re: Mapper using wrong EMAC with PowerPC in V4FX60
114058: 07/01/03: Ray: FPGA ROUTING
114059: 07/01/03: Peter Alfke: Re: FPGA ROUTING
114064: 07/01/03: Ray: Re: FPGA ROUTING
114067: 07/01/03: JJ: Re: FPGA ROUTING
114080: 07/01/04: vasile: Re: FPGA ROUTING
114083: 07/01/04: Symon: Re: FPGA ROUTING
114081: 07/01/04: vasile: Re: FPGA ROUTING
114070: 07/01/03: Davy: DC timing violation, what to do first?
114074: 07/01/04: Jerome: Re: DC timing violation, what to do first?
114118: 07/01/04: Mike Lewis: Re: DC timing violation, what to do first?
114147: 07/01/05: Mike Lewis: Re: DC timing violation, what to do first?
114076: 07/01/04: Kim Enkovaara: Re: DC timing violation, what to do first?
114077: 07/01/04: Davy: Re: DC timing violation, what to do first?
114120: 07/01/04: Nico Coesel: Re: DC timing violation, what to do first?
114124: 07/01/04: Davy: Re: DC timing violation, what to do first?
114126: 07/01/05: Thomas Stanka: Re: DC timing violation, what to do first?
114156: 07/01/05: Jim Lewis: Re: DC timing violation, what to do first?
114091: 07/01/04: Tim Verstraete: [XST 8.2.3] DSP48 inference multiply/add
114092: 07/01/04: Jonathan Bromley: Re: [XST 8.2.3] DSP48 inference multiply/add
114096: 07/01/04: Jonathan Bromley: Re: [XST 8.2.3] DSP48 inference multiply/add
114155: 07/01/05: Mike Treseler: Re: [XST 8.2.3] DSP48 inference multiply/add
114172: 07/01/06: Brian Drummond: Re: [XST 8.2.3] DSP48 inference multiply/add
114176: 07/01/06: yttrium: Re: [XST 8.2.3] DSP48 inference multiply/add
114209: 07/01/07: Ray Andraka: Re: [XST 8.2.3] DSP48 inference multiply/add
114093: 07/01/04: Tim Verstraete: Re: [XST 8.2.3] DSP48 inference multiply/add
114094: 07/01/04: Tim Verstraete: Re: [XST 8.2.3] DSP48 inference multiply/add
114100: 07/01/04: axr0284: measure setup and hold time
114130: 07/01/05: Lars: Re: measure setup and hold time
114140: 07/01/05: axr0284: Re: measure setup and hold time
114256: 07/01/09: Lars: Re: measure setup and hold time
114288: 07/01/10: axr0284: Re: measure setup and hold time
114341: 07/01/12: backhus: Medwedjew - who was that guy?
114352: 07/01/12: Brian Drummond: Re: Medwedjew - who was that guy?
114102: 07/01/04: wallge: iterative algorithms + tightly coupled CPU with cloud of logic in FPGA
114112: 07/01/04: JJ: Re: iterative algorithms + tightly coupled CPU with cloud of logic in FPGA
114151: 07/01/05: Derek Simmons: Re: iterative algorithms + tightly coupled CPU with cloud of logic in FPGA
114106: 07/01/04: John: Virtex 4 FIFO question
114108: 07/01/04: John: Re: Virtex 4 FIFO question
114148: 07/01/05: Brad Smallridge: Re: Virtex 4 FIFO question
114109: 07/01/04: idp2: Unconnected Blocks??
114113: 07/01/04: idp2: Re: Virtex 4 FIFO question
114114: 07/01/04: idp2: Re: Virtex 4 FIFO question
114119: 07/01/04: Joel: LatticeMico32 Problem
114121: 07/01/04: Jon Beniston: Re: LatticeMico32 Problem
114123: 07/01/04: fpgaman: Re: LatticeMico32 Problem
114125: 07/01/04: Brian Davis: ISE 8.2sp3 clobbering source file timestamps?
114137: 07/01/05: Lars: Re: ISE 8.2sp3 clobbering source file timestamps?
114144: 07/01/05: Brian Davis: Re: ISE 8.2sp3 clobbering source file timestamps?
114127: 07/01/05: Manfred Balik: Altera Cyclone II die revision?
114251: 07/01/08: Subroto Datta: Re: Altera Cyclone II die revision?
114131: 07/01/05: Lars: Spartan3E minimum clock-to-output (hold time)
114132: 07/01/05: Lars: Re: Spartan3E minimum clock-to-output (hold time)
114134: 07/01/05: Symon: Re: Spartan3E minimum clock-to-output (hold time)
114142: 07/01/05: Bob: Re: Spartan3E minimum clock-to-output (hold time)
114145: 07/01/05: John_H: Re: Spartan3E minimum clock-to-output (hold time)
114143: 07/01/05: Lars: Re: Spartan3E minimum clock-to-output (hold time)
114146: 07/01/05: Nico Coesel: Re: Spartan3E minimum clock-to-output (hold time)
114171: 07/01/06: Nico Coesel: Re: Spartan3E minimum clock-to-output (hold time)
114149: 07/01/05: Peter Alfke: Re: Spartan3E minimum clock-to-output (hold time)
114150: 07/01/05: matteo: dynamically created blockRAM contents?
114189: 07/01/06: Jim Wu: Re: dynamically created blockRAM contents?
114199: 07/01/07: matteo: Re: dynamically created blockRAM contents?
114236: 07/01/08: Symon: Re: dynamically created blockRAM contents?
114247: 07/01/08: KJ: Re: dynamically created blockRAM contents?
114543: 07/01/18: matteo: Re: dynamically created blockRAM contents?
114152: 07/01/05: Peter Alfke: Re: Virtex 4 FIFO question
114154: 07/01/05: Frank: WANTED: FPGA Development Board w/ Virtex-4 LX160/200 and 2 10/100 Ethernet PHYs
114175: 07/01/06: Brian Drummond: Re: WANTED: FPGA Development Board w/ Virtex-4 LX160/200 and 2 10/100 Ethernet PHYs
114203: 07/01/07: John Adair: Re: WANTED: FPGA Development Board w/ Virtex-4 LX160/200 and 2 10/100 Ethernet PHYs
114157: 07/01/05: axr0284: timing constraints properly setup
114158: 07/01/05: David R Brooks: Anyone seen eASIC?
114161: 07/01/05: Austin Lesea: Re: Anyone seen eASIC?
114162: 07/01/05: PeteS: Re: Anyone seen eASIC?
114160: 07/01/05: rao: Problems with 7:1 LVDS Tx using OSEDES (Xilinx)
114164: 07/01/05: Brad Smallridge: Re: Problems with 7:1 LVDS Tx using OSEDES (Xilinx)
114169: 07/01/05: rao: Re: Problems with 7:1 LVDS Tx using OSEDES (Xilinx)
114177: 07/01/06: yttrium: Re: Problems with 7:1 LVDS Tx using OSEDES (Xilinx)
114163: 07/01/05: Pete Fraser: Xilinx 2-D DCT core (Where?).
114165: 07/01/05: jjlindula@hotmail.com: Help Implementing an 1000Base-T Ethernet on Stratix II GX
114181: 07/01/06: Ben Twijnstra: Re: Help Implementing an 1000Base-T Ethernet on Stratix II GX
114167: 07/01/05: marco: data transfer from fast APB clock domain.
114173: 07/01/06: Jon Beniston: Re: data transfer from fast APB clock domain.
114178: 07/01/06: marco: Re: data transfer from fast APB clock domain.
114219: 07/01/07: <kayrock66@yahoo.com>: Re: data transfer from fast APB clock domain.
114170: 07/01/05: premrajan: query
114183: 07/01/06: Mike Treseler: Re: query
114179: 07/01/06: Mounard Le Fougueux: Problem with unused pin on Spartan 2E
114180: 07/01/06: Mike Treseler: Re: Problem with unused pin on Spartan 2E
114182: 07/01/06: KJ: Re: Problem with unused pin on Spartan 2E
114184: 07/01/06: Mounard Le Fougueux: Re: Problem with unused pin on Spartan 2E
114185: 07/01/06: Mike Treseler: Re: Problem with unused pin on Spartan 2E
114211: 07/01/07: -jg: Re: Problem with unused pin on Spartan 2E
114218: 07/01/07: <kayrock66@yahoo.com>: Re: Problem with unused pin on Spartan 2E
114248: 07/01/08: Mounard Le Fougueux: Re: Problem with unused pin on Spartan 2E
114250: 07/01/08: John_H: Re: Problem with unused pin on Spartan 2E
114186: 07/01/06: fpgauser: email protection in the list
114187: 07/01/06: Sean Durkin: Re: email protection in the list
114188: 07/01/06: Mike Treseler: Re: email protection in the list
114275: 07/01/10: fpgauser: Re: email protection in the list
114190: 07/01/06: Jeff Cunningham: Does Modelsim XE support coreconnect BFM simulation?
114191: 07/01/06: John McCaskill: Re: Does Modelsim XE support coreconnect BFM simulation?
114333: 07/01/11: Jeff Cunningham: Re: Does Modelsim XE support coreconnect BFM simulation?
114193: 07/01/07: SunLei: Is there a simple complex magnitude algorithm in FPGA implementation?
114194: 07/01/07: Peppermint Pumpkin: Re: Is there a simple complex magnitude algorithm in FPGA implementation?
114195: 07/01/07: SunLei: Re: Is there a simple complex magnitude algorithm in FPGA implementation?
114197: 07/01/07: Jonathan Bromley: Re: Is there a simple complex magnitude algorithm in FPGA implementation?
114198: 07/01/07: cpope: Re: Is there a simple complex magnitude algorithm in FPGA implementation?
114208: 07/01/07: Ray Andraka: Re: Is there a simple complex magnitude algorithm in FPGA implementation?
114216: 07/01/08: SunLei: Re: Is there a simple complex magnitude algorithm in FPGA implementation?
114217: 07/01/07: <kayrock66@yahoo.com>: Re: Is there a simple complex magnitude algorithm in FPGA implementation?
114221: 07/01/07: Bob Perlman: Re: Is there a simple complex magnitude algorithm in FPGA implementation?
114242: 07/01/08: Ray Andraka: Re: Is there a simple complex magnitude algorithm in FPGA implementation?
114196: 07/01/07: CMOS: how do we connect internals signals(not ports) of submodules in the top level design to trigger ports of the ila core?
114215: 07/01/07: <kayrock66@yahoo.com>: Re: how do we connect internals signals(not ports) of submodules in the top level design to trigger ports of the ila core?
114235: 07/01/08: Symon: Re: how do we connect internals signals(not ports) of submodules in the top level design to trigger ports of the ila core?
114200: 07/01/07: <tryyourbestok@hotmail.com>: Basic questions about digital phase locked loop
114201: 07/01/07: Andrew Holme: Re: Basic questions about digital phase locked loop
114202: 07/01/07: Don Lancaster: Re: Basic questions about digital phase locked loop
114204: 07/01/07: Genome: Re: Basic questions about digital phase locked loop
114205: 07/01/07: Jim Thompson: Re: Basic questions about digital phase locked loop
114220: 07/01/07: Tim Wescott: Re: Basic questions about digital phase locked loop
114206: 07/01/07: John Adair: First Picture of Craignell Modules
114212: 07/01/07: -jg: Re: First Picture of Craignell Modules
114395: 07/01/14: Jonathan Bromley: Re: First Picture of Craignell Modules
114232: 07/01/08: Dave Pollum: Re: First Picture of Craignell Modules
114246: 07/01/08: -jg: Re: First Picture of Craignell Modules
114308: 07/01/11: John Adair: Re: First Picture of Craignell Modules
114400: 07/01/14: John Adair: Re: First Picture of Craignell Modules
114708: 07/01/23: <pbgbbrsh@ludd.invalid>: Re: First Picture of Craignell Modules
114718: 07/01/23: <pbFJKD@ludd.invalid>: Re: First Picture of Craignell Modules
114711: 07/01/23: Antti: Re: First Picture of Craignell Modules
114207: 07/01/08: Timo Schneider: Build an FPGA programmer cable
114224: 07/01/08: Pablo: Re: Build an FPGA programmer cable
114231: 07/01/08: Guenter: Re: Build an FPGA programmer cable
114240: 07/01/08: Timo Schneider: Re: Build an FPGA programmer cable
114241: 07/01/08: Antti: Re: Build an FPGA programmer cable
114243: 07/01/08: Vangelis: Re: Build an FPGA programmer cable
114245: 07/01/08: Timo Schneider: Re: Build an FPGA programmer cable
114210: 07/01/07: Davy: Use Multi-cycle Path or Pipeline?
114213: 07/01/07: <kayrock66@yahoo.com>: Re: Use Multi-cycle Path or Pipeline?
114214: 07/01/07: Mike Treseler: Re: Use Multi-cycle Path or Pipeline?
114226: 07/01/08: Hans: Re: Use Multi-cycle Path or Pipeline?
114237: 07/01/08: Mike Treseler: Re: Use Multi-cycle Path or Pipeline?
114230: 07/01/08: Jerome: Re: Use Multi-cycle Path or Pipeline?
114222: 07/01/08: SunLei: (-1)*xn operation in FPGA
114223: 07/01/07: Bob Perlman: Re: (-1)*xn operation in FPGA
114225: 07/01/08: Thomas Stanka: Re: (-1)*xn operation in FPGA
114229: 07/01/08: KJ: Re: (-1)*xn operation in FPGA
114228: 07/01/08: Pablo: CREATE FPGA-PC CONNECTION (LWIP, XILNET)
114233: 07/01/08: Peter Kampmann: Generate ACE File: *.elf does not contain start address
114238: 07/01/08: Peter Kampmann: Re: Generate ACE File: *.elf does not contain start address
114239: 07/01/08: John: Variable clock using Virtex 4?
114244: 07/01/08: Austin Lesea: Re: Variable clock using Virtex 4?
114252: 07/01/08: Peter Alfke: Re: Variable clock using Virtex 4?
114249: 07/01/08: <Wilhelm.Klink@gmail.com>: Quartus II 6.1 Remove Duplicate Logic option removed
114253: 07/01/08: <sheikh.m.farhan@gmail.com>: Accessing SATA hard disk for read/write IO through FPGA in an embedded environment
114264: 07/01/10: Mark McDougall: Re: Accessing SATA hard disk for read/write IO through FPGA in an
114254: 07/01/09: Perry: crash of xilinx fpga_editor
114255: 07/01/09: <jetmarc@hotmail.com>: V4FX PPC data cache behaviour?
114257: 07/01/09: John: Delaying signal
114258: 07/01/09: John: Re: Delaying signal
114268: 07/01/10: Thomas Stanka: Re: Delaying signal
114259: 07/01/09: Roberto Waltman: Re: Possibility of 80188 VHDL core
114284: 07/01/10: Roberto Waltman: Re: Possibility of 80188 VHDL core
114260: 07/01/09: Hans: Re: Possibility of 80188 VHDL core
114263: 07/01/09: Fred: PCI-Express TLP example
114281: 07/01/10: Colin Hankins: Re: PCI-Express TLP example
114292: 07/01/11: Fred: Re: PCI-Express TLP example
114294: 07/01/10: Colin Hankins: Re: PCI-Express TLP example
114266: 07/01/09: motty: Is the FSL a good approach for this...?
114267: 07/01/10: Göran Bilski: Re: Is the FSL a good approach for this...?
114269: 07/01/10: rajendra: ise8.1 and 8.2 difference for SIM_CLKIN_CYCLE_JITTER parameter
114270: 07/01/10: <zhongqiang.cheng@gmail.com>: Operate Flash S29GL-N from Spansion
114271: 07/01/10: Matthieu Cattin: crossing clock domain ??
114273: 07/01/10: John_H: Re: crossing clock domain ??
114276: 07/01/10: Matthieu Cattin: Re: crossing clock domain ??
114285: 07/01/10: Matthew Hicks: Re: crossing clock domain ??
114287: 07/01/10: John_H: Re: crossing clock domain ??
114295: 07/01/11: Rob: Re: crossing clock domain ??
114324: 07/01/11: Matthew Hicks: Re: crossing clock domain ??
114280: 07/01/10: Peter Alfke: Re: crossing clock domain ??
114290: 07/01/10: Peter Alfke: Re: crossing clock domain ??
114298: 07/01/10: Peter Alfke: Re: crossing clock domain ??
114327: 07/01/11: Craig Yarbrough: Re: crossing clock domain ??
114272: 07/01/10: Matthieu Cattin: P160 analog module ?
114296: 07/01/11: Rob: Re: P160 analog module ?
114274: 07/01/10: fpgauser: VHDL Model of a stepper motor
114302: 07/01/11: Jonathan Bromley: Re: VHDL Model of a stepper motor
114337: 07/01/12: backhus: Re: VHDL Model of a stepper motor
114484: 07/01/17: fpgauser: Re: VHDL Model of a stepper motor
114277: 07/01/10: Ved: Is this Multi-Cycle Path ?
114291: 07/01/10: Gabor: Re: Is this Multi-Cycle Path ?
114278: 07/01/10: Pablo: LWIP EXAMPLE??
114286: 07/01/10: Jon Beniston: Re: LWIP EXAMPLE??
114340: 07/01/12: David R Brooks: Re: LWIP EXAMPLE??
114339: 07/01/12: Pablo: Re: LWIP EXAMPLE??
114279: 07/01/10: Dale: Can I use 3.3V clock into the MGTCLK? MGT RocketIO
114283: 07/01/10: Austin Lesea: Re: Can I use 3.3V clock into the MGTCLK? MGT RocketIO
114489: 07/01/17: Austin Lesea: Re: Can I use 3.3V clock into the MGTCLK? MGT RocketIO
114563: 07/01/19: glen herrmannsfeldt: Re: Can I use 3.3V clock into the MGTCLK? MGT RocketIO
114486: 07/01/17: Kolja Sulimma: Re: Can I use 3.3V clock into the MGTCLK? MGT RocketIO
114282: 07/01/10: wallge: inserting text into a video stream (from a pre-existing video source)
114289: 07/01/10: MikeJ: Re: inserting text into a video stream (from a pre-existing video source)
114309: 07/01/11: Martin Thompson: Re: inserting text into a video stream (from a pre-existing video source)
114318: 07/01/11: Brad Smallridge: Re: inserting text into a video stream (from a pre-existing video source)
114332: 07/01/11: Brad Smallridge: Re: inserting text into a video stream (from a pre-existing video source)
114329: 07/01/11: wallge: Re: inserting text into a video stream (from a pre-existing video source)
114331: 07/01/11: Spehro Pefhany: Re: inserting text into a video stream (from a pre-existing video source)
114334: 07/01/11: -jg: Re: inserting text into a video stream (from a pre-existing video source)
114359: 07/01/12: wallge: Re: inserting text into a video stream (from a pre-existing video source)
114293: 07/01/10: Kevin Neilson: Transport Delays in Modelsim
114304: 07/01/11: Jonathan Bromley: Re: Transport Delays in Modelsim
114323: 07/01/11: Kevin Neilson: Re: Transport Delays in Modelsim
114325: 07/01/11: Jonathan Bromley: Re: Transport Delays in Modelsim
114360: 07/01/12: Kevin Neilson: Re: Transport Delays in Modelsim
114367: 07/01/12: Jonathan Bromley: Re: Transport Delays in Modelsim
114428: 07/01/15: Brian Drummond: Re: Transport Delays in Modelsim
114297: 07/01/10: jacko: Santa Clara Connector and LVTTL etc
114299: 07/01/10: jacko: altera MAX II dev kit LCD mountings??
114300: 07/01/10: quad: EDIF generation from C
114306: 07/01/11: Amit: Re: EDIF generation from C
114310: 07/01/11: acd: Re: EDIF generation from C
114316: 07/01/11: quad: Re: EDIF generation from C
114330: 07/01/12: Petter Gustad: Re: EDIF generation from C
114301: 07/01/11: PeteS: Quick question on Coolrunner II IO voltages
114305: 07/01/11: -jg: Re: Quick question on Coolrunner II IO voltages
114303: 07/01/11: Davy: Interlock and stall in CPU design?
114307: 07/01/11: Jon Beniston: Re: Interlock and stall in CPU design?
114311: 07/01/11: Ben Jones: Re: Interlock and stall in CPU design?
114312: 07/01/11: JoshforRefugee: Re: Interlock and stall in CPU design?
114313: 07/01/11: Yao Qi: Re: Interlock and stall in CPU design?
114314: 07/01/11: axr0284: picoblaze RS-232 using 62.5 MHz
114315: 07/01/11: John_H: Re: picoblaze RS-232 using 62.5 MHz
114363: 07/01/12: Eric Crabill: Re: picoblaze RS-232 using 62.5 MHz
114319: 07/01/11: axr0284: Re: picoblaze RS-232 using 62.5 MHz
114321: 07/01/11: axr0284: Re: picoblaze RS-232 using 62.5 MHz
114336: 07/01/11: -jg: Re: picoblaze RS-232 using 62.5 MHz
114317: 07/01/11: Brad Smallridge: Xilinx Synchronous FIFOs
114322: 07/01/11: Andrew Holme: Re: Xilinx Synchronous FIFOs
114320: 07/01/11: Dale: RocketIO, MGT documentation. Does MGT clcok have to be 50% duty cycle?
114362: 07/01/12: Ed McGettigan: Re: RocketIO, MGT documentation. Does MGT clcok have to be 50% duty
114456: 07/01/16: MM: Re: RocketIO, MGT documentation. Does MGT clcok have to be 50% duty cycle?
114326: 07/01/11: Craig Yarbrough: Xilinx Floorplanner 'Replace All With Placement' and still logic left over!
114351: 07/01/12: Brian Drummond: Re: Xilinx Floorplanner 'Replace All With Placement' and still logic left over!
114328: 07/01/11: maxascent: arbitrator
114335: 07/01/11: Derek Simmons: Re: arbitrator
114338: 07/01/11: Perry: user constraint file of slice based bus macro in virtex 4
114342: 07/01/12: <sheikh.m.farhan@gmail.com>: 16-bit DDR memory controller in EDK
114366: 07/01/12: cpope: Re: 16-bit DDR memory controller in EDK
114414: 07/01/15: cpope: Re: 16-bit DDR memory controller in EDK
114406: 07/01/15: <sheikh.m.farhan@gmail.com>: Re: 16-bit DDR memory controller in EDK
114436: 07/01/16: Guru: Re: 16-bit DDR memory controller in EDK
114480: 07/01/17: <sheikh.m.farhan@gmail.com>: Re: 16-bit DDR memory controller in EDK
114348: 07/01/12: Zara: XMD with Microblaze and EDK 8.2
114349: 07/01/12: Andrew Rogers: xc3sprog
114350: 07/01/12: Andrew Rogers: Re: xc3sprog
114365: 07/01/12: Eli Hughes: Re: xc3sprog
114368: 07/01/12: mmihai: Re: xc3sprog
114372: 07/01/13: Andrew Rogers: Re: xc3sprog
143068: 09/09/18: theom: Re: xc3sprog
143100: 09/09/20: Uwe Bonnes: Re: xc3sprog
143101: 09/09/20: Uwe Bonnes: Re: xc3sprog
114377: 07/01/13: mmihai: Re: xc3sprog
114379: 07/01/13: John Larkin: Re: xc3sprog
115294: 07/02/06: <dimtey@gmail.com>: Re: xc3sprog
115335: 07/02/07: mmihai: Re: xc3sprog
159439: 16/11/09: <atul.iagent@gmail.com>: Re: xc3sprog
114353: 07/01/12: Frai: Too many warnings in Modelsim?
114354: 07/01/12: <tgschwind@tiscalinet.ch>: Re: Too many warnings in Modelsim?
114355: 07/01/12: Frai: Re: Too many warnings in Modelsim?
114356: 07/01/12: Peter Y: Stratix RAM limitations
114358: 07/01/12: Hans: Re: Stratix RAM limitations
114361: 07/01/12: Peter Y: Re: Stratix RAM limitations
114371: 07/01/13: Rob: Re: Stratix RAM limitations
114357: 07/01/12: Matthieu Cattin: FIFO LogiCore with ISE 8.2 ??
114364: 07/01/12: Eric Brombaugh: XST bug inferring dynamic shift register
114369: 07/01/12: Weng Tianxiang: How to get correct initial values from Xilinx Vertex II single port distributed ram with ModelSim
114370: 07/01/12: Mike Treseler: Re: How to get correct initial values from Xilinx Vertex II single
114384: 07/01/13: Weng Tianxiang: Re: How to get correct initial values from Xilinx Vertex II single port distributed ram with ModelSim
114418: 07/01/15: Vangelis: Re: How to get correct initial values from Xilinx Vertex II single port distributed ram with ModelSim
114430: 07/01/15: Weng Tianxiang: Re: How to get correct initial values from Xilinx Vertex II single port distributed ram with ModelSim
114373: 07/01/13: <NickHolby@googlemail.com>: Will FPGAs suit my need?
114374: 07/01/13: Icky Thwacket: Re: Will FPGAs suit my need?
114375: 07/01/13: Austin: Re: Will FPGAs suit my need?
114380: 07/01/13: John Larkin: Re: Will FPGAs suit my need?
114381: 07/01/13: Ben Jackson: Re: Will FPGAs suit my need?
114391: 07/01/14: Nico Coesel: Re: Will FPGAs suit my need?
114393: 07/01/14: Icky Thwacket: Re: Will FPGAs suit my need?
114394: 07/01/14: Jonathan Bromley: Re: Will FPGAs suit my need?
114396: 07/01/14: Icky Thwacket: Re: Will FPGAs suit my need?
114412: 07/01/15: Symon: Re: Will FPGAs suit my need?
114398: 07/01/14: Nico Coesel: Re: Will FPGAs suit my need?
114383: 07/01/13: -jg: Re: Will FPGAs suit my need?
114389: 07/01/14: <NickHolby@googlemail.com>: Re: Will FPGAs suit my need?
114392: 07/01/14: <NickHolby@googlemail.com>: Re: Will FPGAs suit my need?
114429: 07/01/15: samiam: Re: Will FPGAs suit my need?
114382: 07/01/13: motty: IDELAY and whether pigs can fly...
114385: 07/01/13: Mike Treseler: Re: IDELAY and whether pigs can fly...
114386: 07/01/13: motty: Re: IDELAY and whether pigs can fly...
114387: 07/01/13: Peter Alfke: Re: IDELAY and whether pigs can fly...
114419: 07/01/15: motty: Re: IDELAY and whether pigs can fly...
114399: 07/01/14: Jason: SDK 8.2 error 127
114401: 07/01/15: Zara: Re: SDK 8.2 error 127
114408: 07/01/15: Jon Beniston: Re: SDK 8.2 error 127
114402: 07/01/15: Klaus Falser: Gigabit Ethernet UDP/IP
114403: 07/01/15: Ben Jackson: Re: Gigabit Ethernet UDP/IP
114404: 07/01/15: Klaus Falser: Re: Gigabit Ethernet UDP/IP
114405: 07/01/15: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: Gigabit Ethernet UDP/IP
114407: 07/01/15: Pablo: Re: Gigabit Ethernet UDP/IP
114424: 07/01/15: John McCaskill: Re: Gigabit Ethernet UDP/IP
114409: 07/01/15: subint: How to install xilinx ise8.2 in Madriva linux
114410: 07/01/15: Symon: Re: How to install xilinx ise8.2 in Madriva linux
114411: 07/01/15: Frai: How to ensure Select signal arrives after Input signals changed
114413: 07/01/15: Frai: Re: How to ensure Select signal arrives after Input signals changed
114415: 07/01/15: Mike Treseler: Re: How to ensure Select signal arrives after Input signals changed
114416: 07/01/15: Vangelis: PowerPC_DDR_controller
114470: 07/01/17: Peter Monta: Re: PowerPC_DDR_controller
114417: 07/01/15: El-Mehdi Taileb: ISE 9.1i and partial reconfiguration
114422: 07/01/15: Andy Peters: Re: ISE 9.1i and partial reconfiguration
114427: 07/01/15: -jg: Re: ISE 9.1i and partial reconfiguration
114550: 07/01/18: Julian Kain: Re: ISE 9.1i and partial reconfiguration
114626: 07/01/21: El-Mehdi Taileb: Re: ISE 9.1i and partial reconfiguration
114420: 07/01/15: <dhruvakshad@gmail.com>: benchmarks for vhdl
114423: 07/01/15: quad: EDIF format
114426: 07/01/15: Petter Gustad: Re: EDIF format
114431: 07/01/15: pete o.: Verifying a Bidirectional Data Bus
114432: 07/01/15: Ian: Registered?
114433: 07/01/15: Joel Kolstad: Re: Registered?
114473: 07/01/17: Ian: Re: Registered?
114434: 07/01/15: madair: Constraining Multiple clock design
114437: 07/01/16: Hans: Re: Constraining Multiple clock design
114435: 07/01/16: axalay: Digital Filter and external PLL (VCO)
114441: 07/01/16: <ray@desinformation.de>: Re: Digital Filter and external PLL (VCO)
114447: 07/01/16: axalay: Re: Digital Filter and external PLL (VCO)
114451: 07/01/16: Peter Alfke: Re: Digital Filter and external PLL (VCO)
114469: 07/01/17: axalay: Re: Digital Filter and external PLL (VCO)
114438: 07/01/16: skyworld: four phase clock using DCM with xilinx FPGA
114458: 07/01/16: motty: Re: four phase clock using DCM with xilinx FPGA
114462: 07/01/16: skyworld: Re: four phase clock using DCM with xilinx FPGA
114464: 07/01/16: motty: Re: four phase clock using DCM with xilinx FPGA
114466: 07/01/16: skyworld: Re: four phase clock using DCM with xilinx FPGA
114488: 07/01/17: motty: Re: four phase clock using DCM with xilinx FPGA
114500: 07/01/17: skyworld: Re: four phase clock using DCM with xilinx FPGA
115252: 07/02/05: <smackeron@gmail.com>: Re: four phase clock using DCM with xilinx FPGA
114439: 07/01/16: kron: Two newbie Chipscope questions
114442: 07/01/16: Ben Jones: Re: Two newbie Chipscope questions
114440: 07/01/16: axalay: about XAPP028
114443: 07/01/16: <jonas@mit.edu>: small, free simple state machine processor suggestions?
114445: 07/01/16: Sean Durkin: Re: small, free simple state machine processor suggestions?
114446: 07/01/16: <jonas@mit.edu>: Re: small, free simple state machine processor suggestions?
114448: 07/01/16: Herbert Kleebauer: Re: small, free simple state machine processor suggestions?
114449: 07/01/16: <jonas@mit.edu>: Re: small, free simple state machine processor suggestions?
114468: 07/01/16: Antti: Re: small, free simple state machine processor suggestions?
114444: 07/01/16: Brandon Jasionowski: Setup time path on V4 SX w/ IDELAY
114450: 07/01/16: Sean Durkin: Re: Setup time path on V4 SX w/ IDELAY
114452: 07/01/16: <john.windish@gmail.com>: Synchronizing four phase-offset clock domains
114453: 07/01/16: Jalen.Ong@gmail.com: microcode in verilog?
114454: 07/01/16: Mike Treseler: Re: microcode in verilog?
114463: 07/01/16: Derek Simmons: Re: microcode in verilog?
114467: 07/01/16: -jg: Re: microcode in verilog?
114492: 07/01/17: Andrew Holme: Re: microcode in verilog?
114497: 07/01/17: PeteS: Re: microcode in verilog?
114455: 07/01/16: yttrium: interesting article FPGA routing field programmable nanowire interconnect
114457: 07/01/16: Austin Lesea: Re: interesting article FPGA routing field programmable nanowire
114459: 07/01/16: Ray Andraka: Re: interesting article FPGA routing field programmable nanowire
114465: 07/01/16: -jg: Re: interesting article FPGA routing field programmable nanowire interconnect (FPNI)
114460: 07/01/16: <psgandhi@gmail.com>: Clock Frequency
114461: 07/01/16: Andrew FPGA: Re: Clock Frequency
114472: 07/01/17: axalay: Re: Clock Frequency
114471: 07/01/17: rbal: running applications from external memory
114496: 07/01/17: Jhlw: Re: running applications from external memory
114519: 07/01/18: Jeff Cunningham: Re: running applications from external memory
114503: 07/01/17: Jhlw: Re: running applications from external memory
114537: 07/01/18: Jhlw: Re: running applications from external memory
114538: 07/01/18: Jhlw: Re: running applications from external memory
114560: 07/01/19: rbal: Re: running applications from external memory
114474: 07/01/17: Al: Modelsim: Warning: (vsim-WLF-5000) Log file vsim.wlf currently in
114475: 07/01/17: Al: Re: Modelsim: Warning: (vsim-WLF-5000) Log file vsim.wlf currently
114476: 07/01/17: Al: Re: Modelsim: Warning: (vsim-WLF-5000) Log file vsim.wlf currently
114479: 07/01/17: Al: Re: Modelsim: Warning: (vsim-WLF-5000) Log file vsim.wlf currently
114478: 07/01/17: Jon Beniston: Re: Modelsim: Warning: (vsim-WLF-5000) Log file vsim.wlf currently in use
114481: 07/01/17: Surya: Ethernet Interface
114482: 07/01/17: Uwe Bonnes: Re: Ethernet Interface
114534: 07/01/18: davide: Re: Ethernet Interface
114674: 07/01/22: davide: Re: Ethernet Interface
114539: 07/01/18: <kayrock66@yahoo.com>: Re: Ethernet Interface
114549: 07/01/18: Surya: Re: Ethernet Interface
114483: 07/01/17: <sheikh.m.farhan@gmail.com>: PCI Card with FPGA
114485: 07/01/17: cpope: Re: PCI Card with FPGA
114516: 07/01/18: cpope: Re: PCI Card with FPGA
114487: 07/01/17: Symon: Re: PCI Card with FPGA
114501: 07/01/17: John Adair: Re: PCI Card with FPGA
114506: 07/01/17: <sheikh.m.farhan@gmail.com>: Re: PCI Card with FPGA
114525: 07/01/18: Quesito: Re: PCI Card with FPGA
114544: 07/01/19: Symon: Re: PCI Card with FPGA
114545: 07/01/18: davide: Re: PCI Card with FPGA
114542: 07/01/18: mike_la_jolla: Re: PCI Card with FPGA
114490: 07/01/17: anand: Considerations for FPGA Based Acceleration in Bio medical simulations/computational biology
114495: 07/01/17: Brad Smallridge: Re: Considerations for FPGA Based Acceleration in Bio medical simulations/computational biology
114564: 07/01/19: glen herrmannsfeldt: Re: Considerations for FPGA Based Acceleration in Bio medical simulations/computational
114583: 07/01/19: Will Dean: Re: Considerations for FPGA Based Acceleration in Bio medical simulations/computational biology
114673: 07/01/22: <pbgbbrsh@ludd.invalid>: Re: Considerations for FPGA Based Acceleration in Bio medical simulations/computational biology
114529: 07/01/18: anand: Re: Considerations for FPGA Based Acceleration in Bio medical simulations/computational biology
114577: 07/01/19: anand: Re: Considerations for FPGA Based Acceleration in Bio medical simulations/computational biology
114689: 07/01/22: <chris.hallahan@nuvation.com>: Re: Considerations for FPGA Based Acceleration in Bio medical simulations/computational biology
114491: 07/01/17: John: Process on both edges
114494: 07/01/17: Ralf Hildebrandt: Re: Process on both edges
114502: 07/01/17: Brad Smallridge: Re: Process on both edges
114508: 07/01/18: Matthew Hicks: Re: Process on both edges
114526: 07/01/18: Erik Widding: Re: Process on both edges
114493: 07/01/17: Neil Steiner: Behavior of REV input in Virtex2 flops?
114536: 07/01/18: Ed McGettigan: Re: Behavior of REV input in Virtex2 flops?
114499: 07/01/17: kelvins: ARM AHBA 1Kbyte boundary issue
114511: 07/01/18: Jon Beniston: Re: ARM AHBA 1Kbyte boundary issue
114517: 07/01/18: Charles, NG: Re: ARM AHBA 1Kbyte boundary issue
114521: 07/01/18: Joseph: Re: ARM AHBA 1Kbyte boundary issue
114531: 07/01/18: Joseph: Re: ARM AHBA 1Kbyte boundary issue
114504: 07/01/17: K. Sudheer Kumar: Generation of Divided-by-3 clock
114505: 07/01/17: Peter Alfke: Re: Generation of Divided-by-3 clock
114507: 07/01/17: gallen: Re: Generation of Divided-by-3 clock
114513: 07/01/18: Symon: Re: Generation of Divided-by-3 clock
114509: 07/01/17: sudheer: Re: Generation of Divided-by-3 clock
114510: 07/01/18: Antti: Re: Generation of Divided-by-3 clock
114524: 07/01/18: <topweaver@hotmail.com>: Re: Generation of Divided-by-3 clock
114530: 07/01/18: visiblepulse: Re: Generation of Divided-by-3 clock
114532: 07/01/18: Peter Alfke: Re: Generation of Divided-by-3 clock
114553: 07/01/18: sudheer: Re: Generation of Divided-by-3 clock
114568: 07/01/19: Ralf Hildebrandt: Re: Generation of Divided-by-3 clock
114512: 07/01/18: Antti: Xilinx website login problems
114515: 07/01/18: Christian Wiesner: Re: Xilinx website login problems
114518: 07/01/18: Zara: Re: Xilinx website login problems
114520: 07/01/18: Symon: Re: Xilinx website login problems
114522: 07/01/18: John Adair: Re: Xilinx website login problems
114523: 07/01/18: Antti: Re: Xilinx website login problems
114552: 07/01/19: El-Mehdi Taileb: Re: Xilinx website login problems
114624: 07/01/21: Thomas Feller: Re: Xilinx website login problems
114514: 07/01/18: Christian Wiesner: Source Synchronous LVDS Design - Phase Shift in the Timing Analysis?
114657: 07/01/22: Christian Wiesner: Re: Source Synchronous LVDS Design - Phase Shift in the Timing Analysis?
115250: 07/02/05: Christian Wiesner: Re: Source Synchronous LVDS Design - Phase Shift in the Timing Analysis?
114527: 07/01/18: Pablo: TESTAPP_PERIPHERAL FAILED IN ETHERNET
114528: 07/01/18: spectrallypure: Different Modelsim versions disagree in same backannotation!
114541: 07/01/18: Paul Jansen: Re: Different Modelsim versions disagree in same backannotation!
114643: 07/01/22: Kim Enkovaara: Re: Different Modelsim versions disagree in same backannotation!
114754: 07/01/23: Paul Jansen: Re: Different Modelsim versions disagree in same backannotation!
114555: 07/01/19: Kim Enkovaara: Re: Different Modelsim versions disagree in same backannotation!
114557: 07/01/19: Thomas Stanka: Re: Different Modelsim versions disagree in same backannotation!
114606: 07/01/20: spectrallypure: Re: Different Modelsim versions disagree in same backannotation!
114694: 07/01/23: Duth: Re: Different Modelsim versions disagree in same backannotation!
114533: 07/01/18: Antonio Di Bacco: ISE Simulator Error 222: SuSE 10.1 Linux
114554: 07/01/19: El-Mehdi Taileb: Re: ISE Simulator Error 222: SuSE 10.1 Linux
114596: 07/01/20: Antonio Di Bacco: Re: ISE Simulator Error 222: SuSE 10.1 Linux
114589: 07/01/20: Daniel O'Connor: Re: ISE Simulator Error 222: SuSE 10.1 Linux
114535: 07/01/18: James Wu: Beginner VHDL questions
114567: 07/01/19: Martin Thompson: Re: Beginner VHDL questions
114570: 07/01/19: Brian Drummond: Re: Beginner VHDL questions
114576: 07/01/19: jmoui: Re: Beginner VHDL questions
114578: 07/01/19: Ben Jones: Re: Beginner VHDL questions
114580: 07/01/19: Andy: Re: Beginner VHDL questions
114585: 07/01/19: James: Re: Beginner VHDL questions
114540: 07/01/18: Austin Lesea: "Gate" = ???
114546: 07/01/18: John_H: Re: "Gate" = ???
114561: 07/01/19: Andreas Ehliar: Re: "Gate" = ???
114547: 07/01/19: mk: Re: "Gate" = ???
114562: 07/01/19: glen herrmannsfeldt: Re: "Gate" = ???
114566: 07/01/19: backhus: Re: "Gate" = ???
114582: 07/01/19: Ray Andraka: Re: "Gate" = ???
114584: 07/01/19: Austin Lesea: Re: "Gate" = ???
114548: 07/01/18: motty: Timing Delay Definitions
114556: 07/01/19: Symon: Re: Timing Delay Definitions
114574: 07/01/19: motty: Re: Timing Delay Definitions
114551: 07/01/18: sindhu: FPGA implementation of UHF transmitter in airborne applications
114586: 07/01/19: Ray Andraka: Re: FPGA implementation of UHF transmitter in airborne applications
114588: 07/01/19: PeteS: Re: FPGA implementation of UHF transmitter in airborne applications
114558: 07/01/19: axalay: Phasse Detector
114573: 07/01/19: motty: Re: Phasse Detector
114575: 07/01/19: Tim: Re: Phasse Detector
114587: 07/01/19: -jg: Re: Phasse Detector
114590: 07/01/19: PeteS: Re: Phasse Detector
114595: 07/01/20: PeteS: Re: Phasse Detector
114611: 07/01/20: David R Brooks: Re: Phasse Detector
114617: 07/01/20: Austin: Re: frequency-Phase Detector?
114658: 07/01/22: Symon: Re: Phasse Detector
114592: 07/01/19: Peter Alfke: Re: Phasse Detector
114597: 07/01/20: axalay: Re: Phasse Detector
114602: 07/01/20: JustJohn: Re: Phasse Detector
114609: 07/01/20: -jg: Re: Phasse Detector
114641: 07/01/21: axalay: Re: frequency-Phase Detector?
114569: 07/01/19: <moogyd@yahoo.co.uk>: Series DCM's and total Lock Time
114571: 07/01/19: motty: Re: Series DCM's and total Lock Time
114572: 07/01/19: Symon: Re: Series DCM's and total Lock Time
114644: 07/01/21: <moogyd@yahoo.co.uk>: Re: Series DCM's and total Lock Time
114579: 07/01/19: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: NetBSD on Xilinx fpga (ported to ML403)
114581: 07/01/19: bm: SPARC V7 CORE
114598: 07/01/20: Hans: Re: SPARC V7 CORE
114604: 07/01/20: bm: Re: SPARC V7 CORE
114621: 07/01/21: Eric Smith: Re: SPARC V7 CORE
114599: 07/01/20: Uncle Noah: Re: SPARC V7 CORE
114591: 07/01/19: Dennis Yurichev: Altera EP2S60 rebooting itself
114593: 07/01/19: Gabor: Re: Altera EP2S60 rebooting itself
114603: 07/01/20: jai.dhar@gmail.com: Re: Altera EP2S60 rebooting itself
114600: 07/01/20: geschma: How can I make xst to infer BlockRAM instead of Distributed RAM
114605: 07/01/20: Andrew Holme: Re: How can I make xst to infer BlockRAM instead of Distributed RAM
114608: 07/01/20: Andrew Holme: Re: How can I make xst to infer BlockRAM instead of Distributed RAM
114620: 07/01/21: Ben Jackson: Re: How can I make xst to infer BlockRAM instead of Distributed RAM
114607: 07/01/20: Matthew Hicks: Re: How can I make xst to infer BlockRAM instead of Distributed RAM
114610: 07/01/20: stephen.craven@gmail.com: Re: How can I make xst to infer BlockRAM instead of Distributed RAM
114705: 07/01/23: Duth: Re: How can I make xst to infer BlockRAM instead of Distributed RAM
114601: 07/01/20: Dave Pollum: Re: Beginner VHDL questions
114612: 07/01/20: Neil Steiner: Correction for hwicap_v1_00_a code
114635: 07/01/22: John Williams: Re: Correction for hwicap_v1_00_a code
114670: 07/01/22: Neil Steiner: Re: Correction for hwicap_v1_00_a code
114613: 07/01/20: project help: suggest me the right fpga
114614: 07/01/21: Rob: Re: suggest me the right fpga
114615: 07/01/20: Peter Alfke: Re: suggest me the right fpga
114616: 07/01/20: Austin: Re: suggest me the right fpga
114625: 07/01/21: <pbgibbrish@ludd.invalid>: Re: suggest me the right fpga
114618: 07/01/20: Neil Steiner: Re: edif format
114646: 07/01/22: Petter Gustad: Re: edif format
114675: 07/01/22: Ed McGettigan: Re: edif format
114677: 07/01/22: Mike Treseler: Re: edif format
114683: 07/01/23: Petter Gustad: Re: edif format
114619: 07/01/21: Corer: digilent nexys vga glitches
114622: 07/01/21: Sylvain Munaut: Re: digilent nexys vga glitches
114633: 07/01/21: Corer: Re: digilent nexys vga glitches
114623: 07/01/21: Sylvain Munaut: Re: digilent nexys vga glitches
114632: 07/01/21: Ben Jackson: Re: digilent nexys vga glitches
114634: 07/01/21: Corer: Re: digilent nexys vga glitches
114655: 07/01/22: RedskullDC: Re: digilent nexys vga glitches
114682: 07/01/22: Corer: Re: digilent nexys vga glitches
114715: 07/01/23: RedskullDC: Re: digilent nexys vga glitches
114767: 07/01/24: Corer: Re: digilent nexys vga glitches
114627: 07/01/21: project help: project help
114628: 07/01/21: Peter Alfke: Re: project help
114630: 07/01/21: Josep Duran: Re: project help
114629: 07/01/21: <nbg2006@gmail.com>: system generator from Xilinx
114770: 07/01/24: MM: Re: system generator from Xilinx
114801: 07/01/24: Ben Jones: Re: system generator from Xilinx
114807: 07/01/24: MM: Re: system generator from Xilinx
114813: 07/01/24: Ben Jones: Re: system generator from Xilinx
114809: 07/01/24: Martin Thompson: Re: system generator from Xilinx
114631: 07/01/21: <shitsu>: When do I need reset and clear?
114636: 07/01/21: ZHI: how to use register to save data
114637: 07/01/21: ZHI: Re: how to use register to save data
114642: 07/01/22: backhus: Re: how to use register to save data
114691: 07/01/23: backhus: Re: how to use register to save data
114647: 07/01/22: ZHI: Re: how to use register to save data
114638: 07/01/21: Weng Tianxiang: How to exclude timing violations in Xilinx *.ucf file
114639: 07/01/21: <zwsdotcom@gmail.com>: Using demo IP libraries?
114640: 07/01/21: quad: Re: edif format
114645: 07/01/22: Sylvain Munaut <SomeOne@SomeDomain.com>: "Divide" a video line in two stripe
114648: 07/01/22: jbnote: Re: "Divide" a video line in two stripe
114650: 07/01/22: jbnote: Re: "Divide" a video line in two stripe
114651: 07/01/22: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: "Divide" a video line in two stripe
114652: 07/01/22: jbnote: Re: "Divide" a video line in two stripe
114654: 07/01/22: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: "Divide" a video line in two stripe
114687: 07/01/23: Rob: Re: "Divide" a video line in two stripe
114904: 07/01/26: Rob: Re: "Divide" a video line in two stripe
114756: 07/01/23: JustJohn: Re: "Divide" a video line in two stripe
114758: 07/01/23: Peter Alfke: Re: "Divide" a video line in two stripe
114762: 07/01/23: JustJohn: Re: "Divide" a video line in two stripe
114773: 07/01/24: jbnote: Re: "Divide" a video line in two stripe
114785: 07/01/24: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: "Divide" a video line in two stripe
114786: 07/01/24: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: "Divide" a video line in two stripe
114649: 07/01/22: backhus: what happened to modular design in ISE9
114656: 07/01/22: Dolphin: Re: what happened to modular design in ISE9
114661: 07/01/22: Tim Verstraete: Re: what happened to modular design in ISE9
114692: 07/01/23: backhus: Re: what happened to modular design in ISE9
114704: 07/01/23: Duth: Re: what happened to modular design in ISE9
114653: 07/01/22: skyworld: Clock constraints
114676: 07/01/22: Gabor: Re: Clock constraints
114686: 07/01/22: skyworld: Re: Clock constraints
114659: 07/01/22: Antti: Xilinx doing a re-entry in non-volatile FPGA arena!!!
114662: 07/01/22: jetq88: Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!
114663: 07/01/22: Nico Coesel: Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!
114665: 07/01/22: Benjamin Todd: Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!
114664: 07/01/22: Antti: Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!
114666: 07/01/22: Antti: Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!
114667: 07/01/22: <pbgbbrsh@ludd.invalid>: Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!
114668: 07/01/22: Austin Lesea: Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!
114672: 07/01/22: Austin Lesea: Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!
114669: 07/01/22: Antti: Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!
114678: 07/01/22: radarman: Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!
114679: 07/01/22: Antti: Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!
114680: 07/01/22: Antti: Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!
114681: 07/01/22: -jg: Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!
114712: 07/01/23: John Adair: Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!
114713: 07/01/23: Antti: Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!
114722: 07/01/23: John Adair: Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!
114660: 07/01/22: ALuPin@web.de: Scrambling for Lattice SC
114671: 07/01/22: bgshea: Xilinx ISE 8.2
114685: 07/01/22: Eric Smith: Re: Xilinx ISE 8.2
114707: 07/01/23: Martin Thompson: Re: Xilinx ISE 8.2
114714: 07/01/23: Daniel O'Connor: Re: Xilinx ISE 8.2
114777: 07/01/24: Martin Thompson: Re: Xilinx ISE 8.2
114856: 07/01/25: Daniel O'Connor: Re: Xilinx ISE 8.2
114918: 07/01/26: Martin Thompson: Re: Xilinx ISE 8.2
114953: 07/01/28: Daniel O'Connor: Re: Xilinx ISE 8.2
114818: 07/01/24: Eric Smith: Re: Xilinx ISE 8.2
114847: 07/01/25: Martin Thompson: Re: Xilinx ISE 8.2
114928: 07/01/26: Eric Smith: Re: Xilinx ISE 8.2
114998: 07/01/29: Martin Thompson: Re: Xilinx ISE 8.2
114727: 07/01/23: dscolson@rcn.com: Re: Xilinx ISE 8.2
114729: 07/01/23: Austin Lesea: Re: Xilinx ISE 8.2
114751: 07/01/23: doug: Re: Xilinx ISE 8.2
114766: 07/01/24: Sean Durkin: Re: Xilinx ISE 8.2
114768: 07/01/24: Sean Durkin: Re: Xilinx ISE 8.2
114779: 07/01/24: Martin Thompson: Re: Xilinx ISE 8.2
114784: 07/01/24: Sean Durkin: Re: Xilinx ISE 8.2
114795: 07/01/24: <ammonton@cc.full.stop.helsinki.fi>: Re: Xilinx ISE 8.2
114815: 07/01/24: <steve.lass@xilinx.com>: Re: Xilinx ISE 8.2
114846: 07/01/25: Sean Durkin: Re: Xilinx ISE 8.2
114934: 07/01/26: <steve.lass@xilinx.com>: Re: Xilinx ISE 8.2
114772: 07/01/24: jesse lackey: Re: Xilinx ISE 8.2
114778: 07/01/24: Martin Thompson: Re: Xilinx ISE 8.2
114814: 07/01/24: Austin Lesea: Re: Xilinx ISE 8.2
114816: 07/01/24: <steve.lass@xilinx.com>: Re: Xilinx ISE 8.2
114829: 07/01/24: doug: Re: Xilinx ISE 8.2
114832: 07/01/24: <steve.lass@xilinx.com>: Re: Xilinx ISE 8.2
114885: 07/01/25: <ammonton@cc.full.stop.helsinki.fi>: Re: Xilinx ISE 8.2
114911: 07/01/26: Ben Jones: Re: Xilinx ISE 8.2
114931: 07/01/26: doug: Re: Xilinx ISE 8.2
114887: 07/01/25: doug: Re: Xilinx ISE 8.2
114819: 07/01/24: doug: Re: Xilinx ISE 8.2
114843: 07/01/25: Andreas Ehliar: Re: Xilinx ISE 8.2
114747: 07/01/23: bgshea: Re: Xilinx ISE 8.2
114748: 07/01/23: jbnote: Re: Xilinx ISE 8.2
114759: 07/01/23: bgshea: Re: Xilinx ISE 8.2
114776: 07/01/24: Michal HUSEJKO: Re: Xilinx ISE 8.2
114817: 07/01/24: bgshea: Re: Xilinx ISE 8.2
114880: 07/01/25: Andy Peters: Re: Xilinx ISE 8.2
115604: 07/02/14: <dimtey@moc.liamg>: Re: Xilinx ISE 8.2
114688: 07/01/22: nagaraj: Difference between virtex 4 rocketio MGT and viretex 5 rocketio GTP
114695: 07/01/23: Symon: Re: Difference between virtex 4 rocketio MGT and viretex 5 rocketio GTP
114703: 07/01/23: Symon: Re: Difference between virtex 4 rocketio MGT and viretex 5 rocketio GTP
114697: 07/01/23: nagaraj: Re: Difference between virtex 4 rocketio MGT and viretex 5 rocketio GTP
114702: 07/01/23: Duth: Re: Difference between virtex 4 rocketio MGT and viretex 5 rocketio GTP
114706: 07/01/23: nagaraj: Re: Difference between virtex 4 rocketio MGT and viretex 5 rocketio GTP
114690: 07/01/22: vu_5421: low speed USB interface for FPGAs
114693: 07/01/23: Jon Beniston: Re: low speed USB interface for FPGAs
115297: 07/02/06: Antti Lukats: Re: low speed USB interface for FPGAs
114696: 07/01/23: Antti: Re: low speed USB interface for FPGAs
115283: 07/02/05: vu_5421: Re: low speed USB interface for FPGAs
114698: 07/01/23: skyworld: XdmHelpers:662
114699: 07/01/23: blisca: iMPACT dont shows erase write options with fpga
114700: 07/01/23: Sean Durkin: Re: iMPACT dont shows erase write options with fpga
114709: 07/01/23: blisca: R: iMPACT dont shows erase write options with fpga
114757: 07/01/23: Ben Jackson: Re: R: iMPACT dont shows erase write options with fpga
114765: 07/01/24: Sean Durkin: Re: R: iMPACT dont shows erase write options with fpga
114769: 07/01/24: Ben Jackson: Re: R: iMPACT dont shows erase write options with fpga
114710: 07/01/23: kunil: FPGA power supply design
114716: 07/01/23: PeteS: Re: FPGA power supply design
114720: 07/01/23: Symon: Re: FPGA power supply design
114725: 07/01/23: Symon: Re: FPGA power supply design
114724: 07/01/23: PeteS: Re: FPGA power supply design
114726: 07/01/23: Austin Lesea: Re: FPGA power supply design
114752: 07/01/23: PeteS: Re: FPGA power supply design
114753: 07/01/23: PeteS: Re: FPGA power supply design
114760: 07/01/23: kunil: Re: FPGA power supply design
114723: 07/01/23: Rune Dahl Jorgensen: Xilinx plb ipif read fifo
114728: 07/01/23: stephen.craven@gmail.com: FPGA damage from bad bitstream
114730: 07/01/23: Nico Coesel: Re: FPGA damage from bad bitstream
114732: 07/01/23: Austin Lesea: Re: FPGA damage from bad bitstream
114750: 07/01/23: Austin Lesea: Re: FPGA damage from bad bitstream
114803: 07/01/24: Austin Lesea: Re: FPGA damage from bad bitstream
114734: 07/01/23: Jon Elson: Re: FPGA damage from bad bitstream
114740: 07/01/23: Neil Steiner: Re: FPGA damage from bad bitstream
114741: 07/01/23: Neil Steiner: Re: FPGA damage from bad bitstream
114742: 07/01/23: Neil Steiner: Re: FPGA damage from bad bitstream
114743: 07/01/23: Neil Steiner: Re: FPGA damage from bad bitstream
114735: 07/01/23: comp.arch.fpga: Re: FPGA damage from bad bitstream
114746: 07/01/23: jbnote: Re: FPGA damage from bad bitstream
114755: 07/01/23: Ben Jackson: Re: FPGA damage from bad bitstream
114782: 07/01/24: <pbFJKD@ludd.invalid>: Re: FPGA damage from bad bitstream
114822: 07/01/24: Jon Elson: Re: FPGA damage from bad bitstream
114763: 07/01/24: Alex Colvin: Re: FPGA damage from bad bitstream
114775: 07/01/24: jbnote: Re: FPGA damage from bad bitstream
114780: 07/01/24: hema: Re: FPGA damage from bad bitstream
114799: 07/01/24: comp.arch.fpga: Re: FPGA damage from bad bitstream
114731: 07/01/23: wallge: Good hardware design code re-use strategies, reference book
114733: 07/01/23: John McCaskill: Re: Good hardware design code re-use strategies, reference book
114796: 07/01/24: Colin Paul Gloster: Re: Good hardware design code re-use strategies, reference book
114736: 07/01/23: Mike Treseler: Re: Good hardware design code re-use strategies, reference book
114761: 07/01/24: Symon: Re: Good hardware design code re-use strategies, reference book
114793: 07/01/24: <pbFJKD@ludd.invalid>: Re: Good hardware design code re-use strategies, reference book
114802: 07/01/24: Guenter: Re: Good hardware design code re-use strategies, reference book
114737: 07/01/23: Rob: NIOS II Application startup issues
114738: 07/01/23: Mike Treseler: Re: NIOS II Application startup issues
114749: 07/01/23: KJ: Re: NIOS II Application startup issues
114764: 07/01/23: CC: Xilinx Constraints Editor doesn't work anymore?
114781: 07/01/24: hema: ethernet MAC and switch
114792: 07/01/24: Guy_FPGA: Re: ethernet MAC and switch
114794: 07/01/24: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: ethernet MAC and switch
114787: 07/01/24: Lancer: uClinux on Spartan 3
114839: 07/01/25: John Williams: Re: uClinux on Spartan 3
114987: 07/01/29: John Williams: Re: uClinux on Spartan 3
115032: 07/01/30: John Williams: Re: uClinux on Spartan 3
115285: 07/02/06: John Williams: Re: uClinux on Spartan 3
114849: 07/01/25: Lancer: Re: uClinux on Spartan 3
115007: 07/01/29: Lancer: Re: uClinux on Spartan 3
115058: 07/01/30: Lancer: Re: uClinux on Spartan 3
114788: 07/01/24: Helmut: Platform Cable USB & Windows 2003 Server
114791: 07/01/24: Guy_FPGA: Re: Platform Cable USB & Windows 2003 Server
114798: 07/01/24: Helmut: Re: Platform Cable USB & Windows 2003 Server
114806: 07/01/24: Helmut: Re: Platform Cable USB & Windows 2003 Server
114789: 07/01/24: <anesserm>: How to make a clock delay?
114790: 07/01/24: KJ: Re: How to make a clock delay?
114797: 07/01/24: <anesserm>: Re: How to make a clock delay?
114844: 07/01/25: David R Brooks: Re: How to make a clock delay?
114800: 07/01/24: Guenter: book recommendation for self study in digital logic design
114808: 07/01/24: Matthew Hicks: Re: book recommendation for self study in digital logic design
114888: 07/01/25: Guenter: Re: book recommendation for self study in digital logic design
114900: 07/01/26: Matthew Hicks: Re: book recommendation for self study in digital logic design
114804: 07/01/24: Sylvain Munaut <SomeOne@SomeDomain.com>: FPGA clock gating ? Or how to avoid it in this case ?
114805: 07/01/24: Symon: Re: FPGA clock gating ? Or how to avoid it in this case ?
114812: 07/01/24: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: FPGA clock gating ? Or how to avoid it in this case ?
114826: 07/01/24: Ben Jackson: Re: FPGA clock gating ? Or how to avoid it in this case ?
114810: 07/01/24: <imity>: Does xiling cpld's need a power supply bypass cap?
114811: 07/01/24: Tim Wescott: Re: Does xiling cpld's need a power supply bypass cap?
114831: 07/01/24: <imity>: Re: Does xiling cpld's need a power supply bypass cap?
114932: 07/01/26: Jon Elson: Re: Does xiling cpld's need a power supply bypass cap?
114824: 07/01/24: Ben Jackson: Re: Does xiling cpld's need a power supply bypass cap?
114828: 07/01/24: bgshea: Re: Does xiling cpld's need a power supply bypass cap?
114833: 07/01/24: Peter Alfke: Re: Does xiling cpld's need a power supply bypass cap?
114835: 07/01/24: -jg: Re: Does xiling cpld's need a power supply bypass cap?
114820: 07/01/24: wallge: video buffering scheme, nonsequential access (no spatial locality)
114854: 07/01/25: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: video buffering scheme, nonsequential access (no spatial locality)
114859: 07/01/25: Gabor: Re: video buffering scheme, nonsequential access (no spatial locality)
114870: 07/01/25: Pete Fraser: Re: video buffering scheme, nonsequential access (no spatial locality)
114861: 07/01/25: jbnote: Re: video buffering scheme, nonsequential access (no spatial locality)
114867: 07/01/25: Martin Thompson: Re: video buffering scheme, nonsequential access (no spatial locality)
114868: 07/01/25: Mike Treseler: Re: video buffering scheme, nonsequential access (no spatial locality)
114872: 07/01/25: wallge: Re: video buffering scheme, nonsequential access (no spatial locality)
114873: 07/01/25: Pete Fraser: Re: video buffering scheme, nonsequential access (no spatial locality)
114890: 07/01/25: Pete Fraser: Re: video buffering scheme, nonsequential access (no spatial locality)
114897: 07/01/25: Pete Fraser: Re: video buffering scheme, nonsequential access (no spatial locality)
114999: 07/01/29: Martin Thompson: Re: video buffering scheme, nonsequential access (no spatial locality)
115065: 07/01/30: Marcus Harnisch: Re: video buffering scheme, nonsequential access (no spatial locality)
114881: 07/01/25: wallge: Re: video buffering scheme, nonsequential access (no spatial locality)
114892: 07/01/25: wallge: Re: video buffering scheme, nonsequential access (no spatial locality)
114907: 07/01/25: JustJohn: Re: video buffering scheme, nonsequential access (no spatial locality)
114933: 07/01/26: wallge: Re: video buffering scheme, nonsequential access (no spatial locality)
114936: 07/01/26: Gabor: Re: video buffering scheme, nonsequential access (no spatial locality)
114972: 07/01/28: Marlboro: Re: video buffering scheme, nonsequential access (no spatial locality)
115009: 07/01/29: wallge: Re: video buffering scheme, nonsequential access (no spatial locality)
115037: 07/01/29: Tommy Thorn: Re: video buffering scheme, nonsequential access (no spatial locality)
115041: 07/01/29: Tommy Thorn: Re: video buffering scheme, nonsequential access (no spatial locality)
115068: 07/01/30: Gabor: Re: video buffering scheme, nonsequential access (no spatial locality)
115070: 07/01/30: wallge: Re: video buffering scheme, nonsequential access (no spatial locality)
114821: 07/01/24: <gsosar@gmail.com>: ML403 board - VGA schematics - wrong pins
114830: 07/01/24: Gerhard Hoffmann: Re: ML403 board - VGA schematics - wrong pins
114863: 07/01/25: Brad Smallridge: Re: ML403 board - VGA schematics - wrong pins
114878: 07/01/25: <gsosar@gmail.com>: Re: ML403 board - VGA schematics - wrong pins
114883: 07/01/25: <gsosar@gmail.com>: Re: ML403 board - VGA schematics - wrong pins
158431: 15/11/23: <abirov@gmail.com>: Re: ML403 board - VGA schematics - wrong pins
158432: 15/11/23: Brian Drummond: Re: ML403 board - VGA schematics - wrong pins
158433: 15/11/23: <abirov@gmail.com>: Re: ML403 board - VGA schematics - wrong pins
114823: 07/01/24: Bill: Aligning data with clock
114827: 07/01/24: bgshea: Re: Aligning data with clock
114837: 07/01/24: Bill: Re: Aligning data with clock
114841: 07/01/25: John_H: Re: Aligning data with clock
114866: 07/01/25: Bill: Re: Aligning data with clock
114836: 07/01/24: Thomas Langċs: General Number Field Sieve in FPGA
114838: 07/01/25: Thomas Womack: Re: General Number Field Sieve in FPGA
114840: 07/01/24: Peter Alfke: Re: Aligning data with clock
114842: 07/01/24: yashu: virtex II pro development board(xupv2p) : maximum current driving strength from hirose connector
114845: 07/01/25: Pablo: CONDITION VARIABLES IN XILKERNEL
114848: 07/01/25: <jetmarc@hotmail.com>: On-chip randomness (V4FX)
114851: 07/01/25: Symon: Re: On-chip randomness (V4FX)
114855: 07/01/25: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: On-chip randomness (V4FX)
114857: 07/01/25: Thomas Stanka: Re: On-chip randomness (V4FX)
114893: 07/01/25: David R Brooks: Re: On-chip randomness (V4FX)
114964: 07/01/28: glen herrmannsfeldt: Re: On-chip randomness (V4FX)
114858: 07/01/25: Ray Andraka: Re: On-chip randomness (V4FX)
114864: 07/01/25: Austin Lesea: Re: On-chip randomness (V4FX)
114871: 07/01/25: Symon: Re: On-chip randomness (V4FX)
114874: 07/01/25: Peter Alfke: Re: On-chip randomness (V4FX)
114950: 07/01/27: H. Peter Anvin: Re: On-chip randomness (V4FX)
114951: 07/01/27: Georg Acher: Re: On-chip randomness (V4FX)
115002: 07/01/29: Symon: Re: On-chip randomness (V4FX)
115014: 07/01/29: Georg Acher: Re: On-chip randomness (V4FX)
114952: 07/01/27: Peter Alfke: Re: On-chip randomness (V4FX)
115004: 07/01/29: <jetmarc@hotmail.com>: Re: On-chip randomness (V4FX)
114850: 07/01/25: nagaraj: IP Protection
114853: 07/01/25: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: IP Protection
114852: 07/01/25: lbo_user: Any UK mirror for ISE 8.2i SP2?
114865: 07/01/25: John Adair: Re: Any UK mirror for ISE 8.2i SP2?
114884: 07/01/25: Jim Wu: Re: Any UK mirror for ISE 8.2i SP2?
114860: 07/01/25: <olive_dominguez@yahoo.fr>: EDK-Modelsim XE
115165: 07/02/01: <steve.lass@xilinx.com>: Re: EDK-Modelsim XE
114862: 07/01/25: Frai: Simulation of DCM with Xilinx 8.2 and Modelsim 6.1
114869: 07/01/25: Ludwig Lenz: xilinx 8.2 xps debug problems
114915: 07/01/26: Brian Drummond: Re: xilinx 8.2 xps debug problems
114941: 07/01/27: Thomas Feller: Re: xilinx 8.2 xps debug problems
114875: 07/01/25: Markus Fras: Xilinx USB download cable
114876: 07/01/25: Ed McGettigan: Re: Xilinx USB download cable
114877: 07/01/25: Markus Fras: Re: Xilinx USB download cable
114949: 07/01/27: <pbFJKD@ludd.invalid>: Re: Xilinx USB download cable
114882: 07/01/25: davide: Re: Xilinx USB download cable
114879: 07/01/25: Andy Peters: Re: Xilinx USB download cable
114886: 07/01/25: <george_granata@hotmail.com>: OrCAD symbol for the Xilinx V5LX50 FF676 device
114889: 07/01/25: Symon: Re: OrCAD symbol for the Xilinx V5LX50 FF676 device
114891: 07/01/25: davide: Re: OrCAD symbol for the Xilinx V5LX50 FF676 device
114901: 07/01/25: Jim Wu: Re: OrCAD symbol for the Xilinx V5LX50 FF676 device
114903: 07/01/25: schsym: Re: OrCAD symbol for the Xilinx V5LX50 FF676 device
114894: 07/01/25: sh3.m4y4: Porting MontaVista Linux on ML403
115161: 07/02/01: Peter Ryser: Re: Porting MontaVista Linux on ML403
114895: 07/01/25: sh3.m4y4: Porting MontaVista Linux on ML403
114899: 07/01/25: Ben Jackson: Re: Porting MontaVista Linux on ML403
114923: 07/01/26: sh3.m4y4: Re: Porting MontaVista Linux on ML403
114896: 07/01/25: Chris Carlen: Can't assign pins in Webpack 8.2i schematic design
115817: 07/02/21: brucejs777: Re: Can't assign pins in Webpack 8.2i schematic design
114898: 07/01/25: Brad Smallridge: ModelSim Leaf Instances
114910: 07/01/26: backhus: Re: ModelSim Leaf Instances
114919: 07/01/26: Duth: Re: ModelSim Leaf Instances
114902: 07/01/25: any2letters: Timing Diagram Tool
114905: 07/01/25: Bob Perlman: Re: Timing Diagram Tool
114913: 07/01/26: Koen Van Renterghem: Re: Timing Diagram Tool
114942: 07/01/27: Terry Brown: Re: Timing Diagram Tool
114929: 07/01/26: Patrick Dubois: Re: Timing Diagram Tool
114906: 07/01/25: Shenli: Datapath design problem?
114925: 07/01/26: JustJohn: Re: Datapath design problem?
114977: 07/01/28: Ray Andraka: Re: Datapath design problem?
114908: 07/01/25: Shenli: unsigned and signed data in Verilog?
114909: 07/01/25: aravind: how do you code this?
114912: 07/01/26: David R Brooks: Re: how do you code this?
114935: 07/01/26: David R Brooks: Re: how do you code this?
114946: 07/01/27: David R Brooks: Re: how do you code this?
114916: 07/01/26: Brian Drummond: Re: how do you code this?
114917: 07/01/26: aravind: Re: how do you code this?
114940: 07/01/27: aravind: Re: how do you code this?
114967: 07/01/28: Marlboro: Re: how do you code this?
114968: 07/01/28: aravind: Re: how do you code this?
114969: 07/01/28: Marlboro: Re: how do you code this?
114914: 07/01/26: anil: Inferring Xilinx RAM's with Byte enable options
114994: 07/01/28: Duth: Re: Inferring Xilinx RAM's with Byte enable options
114920: 07/01/26: skyworld: Timing analyzer with Virtex 4
114921: 07/01/26: Symon: Re: Timing analyzer with Virtex 4
114938: 07/01/27: Symon: Re: Timing analyzer with Virtex 4
115000: 07/01/29: Symon: Re: Timing analyzer with Virtex 4
114937: 07/01/26: skyworld: Re: Timing analyzer with Virtex 4
114957: 07/01/27: skyworld: Re: Timing analyzer with Virtex 4
114958: 07/01/27: motty: Re: Timing analyzer with Virtex 4
114991: 07/01/28: skyworld: Re: Timing analyzer with Virtex 4
115042: 07/01/29: skyworld: Re: Timing analyzer with Virtex 4
114922: 07/01/26: David: Forcing a LUT to not be optimized
114924: 07/01/26: JustJohn: Re: Forcing a LUT to not be optimized
114926: 07/01/26: salorankatu: Re: Forcing a LUT to not be optimized
114927: 07/01/26: Jim Wu: Re: Forcing a LUT to not be optimized
114944: 07/01/27: John_H: Re: Forcing a LUT to not be optimized
114945: 07/01/27: David: Re: Forcing a LUT to not be optimized
115003: 07/01/29: Martin Thompson: Re: Forcing a LUT to not be optimized
115388: 07/02/08: Ray Andraka: Re: Forcing a LUT to not be optimized
114930: 07/01/26: Jan Panteltje: Webpack-9.1 working on debian / grml
114939: 07/01/26: H. Peter Anvin: Anyone have a Lancelot card for sale?
114943: 07/01/27: M Ihsan Baig: Higher studies
114947: 07/01/27: Ben Twijnstra: Re: Higher studies
114966: 07/01/28: <lb.edc@telenet.be>: Re: Higher studies
114948: 07/01/27: comp.arch.fpga: Re: Higher studies
114954: 07/01/27: Marek Kraft: Rank order filtering - XAPP953 - what am I doing wrong?
114955: 07/01/28: <canest>: Minimal design for xilinx?
114959: 07/01/27: Ben Jackson: Re: Minimal design for xilinx?
114965: 07/01/28: <canest>: Re: Minimal design for xilinx?
114970: 07/01/28: Nico Coesel: Re: Minimal design for xilinx?
115025: 07/01/29: Jon Elson: Re: Minimal design for xilinx?
114993: 07/01/28: Ben Jackson: Re: Minimal design for xilinx?
114960: 07/01/27: Peter Alfke: Re: Minimal design for xilinx?
114961: 07/01/27: -jg: Re: Minimal design for xilinx?
114962: 07/01/27: -jg: Re: Minimal design for xilinx?
114963: 07/01/28: HT-Lab: Re: Minimal design for xilinx?
114971: 07/01/28: Peter Alfke: Re: Minimal design for xilinx?
114973: 07/01/28: Peter Wallace: Re: Minimal design for xilinx?
114975: 07/01/28: Leon: Re: Minimal design for xilinx?
114979: 07/01/28: Ray Andraka: Re: Minimal design for xilinx?
114982: 07/01/28: <canest>: Re: Minimal design for xilinx?
115098: 07/01/30: Ray Andraka: Re: Minimal design for xilinx?
115100: 07/01/30: glen herrmannsfeldt: Re: Minimal design for xilinx?
115015: 07/01/29: Benjamin Todd: Re: Minimal design for xilinx?
114974: 07/01/28: Weng Tianxiang: How to make an internal signal embedded deep in hierarchy to a gloal output signal
114976: 07/01/28: KJ: Re: How to make an internal signal embedded deep in hierarchy to a gloal output signal
114981: 07/01/28: Tim: Re: How to make an internal signal embedded deep in hierarchy to
114978: 07/01/28: Weng Tianxiang: Re: How to make an internal signal embedded deep in hierarchy to a gloal output signal
114980: 07/01/28: Andrew Holme: Re: How to make an internal signal embedded deep in hierarchy to a gloal output signal
115001: 07/01/29: Jonathan Bromley: Re: How to make an internal signal embedded deep in hierarchy to a gloal output signal
114985: 07/01/28: Weng Tianxiang: Re: How to make an internal signal embedded deep in hierarchy to a gloal output signal
114996: 07/01/29: ALuPin@web.de: Re: How to make an internal signal embedded deep in hierarchy to a gloal output signal
115010: 07/01/29: Nico Coesel: Re: How to make an internal signal embedded deep in hierarchy to a gloal output signal
115034: 07/01/29: Weng Tianxiang: Re: How to make an internal signal embedded deep in hierarchy to a gloal output signal
115050: 07/01/29: Neo: Re: How to make an internal signal embedded deep in hierarchy to a gloal output signal
114983: 07/01/28: hgs: Problem with pin assign using CASE
114984: 07/01/28: hgs: Problem with pin assign using CASE
114990: 07/01/29: Joseph Samson: Re: Problem with pin assign using CASE
114995: 07/01/28: hgs: Re: Problem with pin assign using CASE
114986: 07/01/28: <canest>: Problem with verilog program
114988: 07/01/28: motty: Re: Problem with verilog program
114992: 07/01/29: <canest>: Re: Problem with verilog program
115047: 07/01/29: glen herrmannsfeldt: Re: Problem with verilog program
115045: 07/01/29: glen herrmannsfeldt: Re: Problem with verilog program
114989: 07/01/29: Joseph Samson: Re: Problem with verilog program
115093: 07/01/30: motty: Re: Problem with verilog program
114997: 07/01/29: jack lee: virtex-II DCM phase shift problems
120758: 07/06/15: cutemonster: Re: virtex-II DCM phase shift problems
120762: 07/06/15: John_H: Re: virtex-II DCM phase shift problems
120763: 07/06/15: cutemonster: Re: virtex-II DCM phase shift problems
115005: 07/01/29: dan: bram can't store elf
115056: 07/01/30: Martin Thompson: Re: bram can't store elf
115103: 07/01/31: Martin Thompson: Re: bram can't store elf
115060: 07/01/30: dan: Re: bram can't store elf
115006: 07/01/29: kron: Conversion from Xilinx ISE 7 to 8 fails
115008: 07/01/29: cathy: question about DCM usage in virtex 5
115012: 07/01/29: Mike Treseler: Re: question about DCM usage in virtex 5
115021: 07/01/29: Mike Treseler: Re: question about DCM usage in virtex 5
115016: 07/01/29: cathy: Re: question about DCM usage in virtex 5
115011: 07/01/29: idp2: Global Clocks in Xilinx ISE
115024: 07/01/29: jesse lackey: Re: Global Clocks in Xilinx ISE
115036: 07/01/29: idp2: Re: Global Clocks in Xilinx ISE
115043: 07/01/29: Ben Jackson: Re: Global Clocks in Xilinx ISE
115071: 07/01/30: idp2: Re: Global Clocks in Xilinx ISE
115111: 07/01/31: Gabor: Re: Global Clocks in Xilinx ISE
115172: 07/02/01: idp2: Re: Global Clocks in Xilinx ISE
115013: 07/01/29: chriskoh: DCM instantiation in XPS7.1i and ISE7.1. Bug or error?
115017: 07/01/29: Uwe Bonnes: Installing Webpack 9.1 on "low-memory" machine (SUSE-10.2)
115018: 07/01/29: Jan Panteltje: Re: Installing Webpack 9.1 on "low-memory" machine (SUSE-10.2)
115019: 07/01/29: Jan Panteltje: Re: Installing Webpack 9.1 on "low-memory" machine (SUSE-10.2)
115026: 07/01/29: Uwe Bonnes: Re: Installing Webpack 9.1 on "low-memory" machine (SUSE-10.2)
115040: 07/01/29: Eric Smith: Re: Installing Webpack 9.1 on "low-memory" machine (SUSE-10.2)
115027: 07/01/29: Uwe Bonnes: Re: Installing Webpack 9.1 on "low-memory" machine (SUSE-10.2)
115020: 07/01/29: billu: USB 2.0 Streaming using FPGAs
115028: 07/01/29: <g.bernocchi@gmail.com>: Re: USB 2.0 Streaming using FPGAs
115038: 07/01/29: Nitro: Re: USB 2.0 Streaming using FPGAs
115097: 07/01/31: John Williams: Re: USB 2.0 Streaming using FPGAs
115044: 07/01/30: Georg Acher: Re: USB 2.0 Streaming using FPGAs
115057: 07/01/30: Will Dean: Re: USB 2.0 Streaming using FPGAs
115052: 07/01/30: Daniel O'Connor: Re: USB 2.0 Streaming using FPGAs
115030: 07/01/29: billu: Re: USB 2.0 Streaming using FPGAs
115048: 07/01/30: Andreas Ehliar: Re: USB 2.0 Streaming using FPGAs
115073: 07/01/30: Matthew Hicks: Re: USB 2.0 Streaming using FPGAs
115049: 07/01/29: billu: Re: USB 2.0 Streaming using FPGAs
115063: 07/01/30: <pbFJKD@ludd.invalid>: Re: USB 2.0 Streaming using FPGAs
115069: 07/01/30: Tim: Re: USB 2.0 Streaming using FPGAs
115155: 07/02/01: <pbFJKD@ludd.invalid>: Re: USB 2.0 Streaming using FPGAs
115075: 07/01/30: Will Dean: Re: USB 2.0 Streaming using FPGAs
115066: 07/01/30: johnp: Re: USB 2.0 Streaming using FPGAs
115077: 07/01/30: billu: Re: USB 2.0 Streaming using FPGAs
115112: 07/01/31: <cs_posting@hotmail.com>: Re: USB 2.0 Streaming using FPGAs
115113: 07/01/31: Dn38517: Re: USB 2.0 Streaming using FPGAs
115022: 07/01/29: <moogyd@yahoo.co.uk>: Xilinx Timing Constraints and failures
115023: 07/01/29: Phil: Change ROM contents, .bit file
115031: 07/01/29: davide: Re: Change ROM contents, .bit file
115046: 07/01/30: Andreas Ehliar: Re: Change ROM contents, .bit file
115029: 07/01/29: Bill: Linux on Virtex 4?
115033: 07/01/30: John Williams: Re: Linux on Virtex 4?
115035: 07/01/29: Bill: Re: Linux on Virtex 4?
115039: 07/01/29: Nitro: Re: Linux on Virtex 4?
115053: 07/01/30: Ricky: linuxppc on ML403
115054: 07/01/30: sudheer: Initialisation of two dimensional array to known non-zero values in verilog
115377: 07/02/08: Kevin Neilson: Re: Initialisation of two dimensional array to known non-zero values
117706: 07/04/07: Stephen Williams: Re: Initialisation of two dimensional array to known non-zero values
115055: 07/01/30: Geronimo Stempovski: 1 Gbps - state of the art?
115062: 07/01/30: Tim: Re: 1 Gbps - state of the art?
115074: 07/01/30: Joel Kolstad: Re: 1 Gbps - state of the art?
115108: 07/01/31: Frithiof Andreas Jensen: Re: 1 Gbps - state of the art?
115455: 07/02/11: Joel Kolstad: Re: 1 Gbps - state of the art?
115512: 07/02/12: glen herrmannsfeldt: Re: 1 Gbps - state of the art?
115078: 07/01/30: Austin Lesea: Re: 1 Gbps - state of the art?: PCIe is 2.5Gb/s, and PCIe V2.x will
115107: 07/01/31: <pbFJKD@ludd.invalid>: Re: 1 Gbps - state of the art?: PCIe is 2.5Gb/s, and PCIe V2.x will be 5.0 Gb/s!
115115: 07/01/31: Austin Lesea: Re: 1 Gbps - state of the art?: PCIe is 2.5Gb/s, and PCIe V2.x will
115080: 07/01/30: PeteS: Re: 1 Gbps - state of the art?
115082: 07/01/31: Jim Granville: Re: 1 Gbps - state of the art?
115087: 07/01/30: PeteS: Re: 1 Gbps - state of the art?
115059: 07/01/30: Thomas Reinemann: Differential pairs per Bank
115083: 07/01/30: Sean Durkin: Re: Differential pairs per Bank
115088: 07/01/30: Uwe Bonnes: Re: Differential pairs per Bank
115105: 07/01/31: Symon: Re: Differential pairs per Bank
115106: 07/01/31: Uwe Bonnes: Re: Differential pairs per Bank
115229: 07/02/04: Ben Popoola: Re: Differential pairs per Bank
115233: 07/02/04: John_H: Re: Differential pairs per Bank
115230: 07/02/04: Peter Alfke: Re: Differential pairs per Bank
115061: 07/01/30: Woutervh: XUP Virtex-II Pro
115064: 07/01/30: Sebastian Schüppel: help with Design Compiler -> Quartus
115084: 07/01/30: Ben Twijnstra: Re: help with Design Compiler -> Quartus
115253: 07/02/05: Sebastian Schüppel: Re: help with Design Compiler -> Quartus
115273: 07/02/05: Andy: Re: help with Design Compiler -> Quartus
115298: 07/02/06: Sebastian Schüppel: Re: help with Design Compiler -> Quartus
115300: 07/02/06: Mike Treseler: Re: help with Design Compiler -> Quartus
115067: 07/01/30: <boled>: How to use the test bench wave form simulator?
115072: 07/01/30: Mike Lewis: Re: How to use the test bench wave form simulator?
115086: 07/01/30: <boled>: Re: How to use the test bench wave form simulator?
115090: 07/01/30: Andy Peters: Re: How to use the test bench wave form simulator?
115094: 07/01/30: <boled>: Re: How to use the test bench wave form simulator?
115099: 07/01/30: Duth: Re: How to use the test bench wave form simulator?
115079: 07/01/30: CMOS: how does z-transforms (basically the mathematical techniques in designing digital systems) map with FPGA implementations
115081: 07/01/30: Derek: Re: how does z-transforms (basically the mathematical techniques in designing digital systems) map with FPGA implementations
115091: 07/01/30: glen herrmannsfeldt: Re: how does z-transforms (basically the mathematical techniques
115085: 07/01/30: fp: Help with Xilinx i/o constracint for ps/2 port
115089: 07/01/30: Andy Peters: Re: Help with Xilinx i/o constracint for ps/2 port
115092: 07/01/30: zlotawy: ahdl --> vhdl
115096: 07/01/30: Mike Treseler: Re: ahdl --> vhdl
115095: 07/01/30: Shant: UNKNOWN Processor Version (0) in XMD
115191: 07/02/02: Ashish: Re: UNKNOWN Processor Version (0) in XMD
115225: 07/02/03: Shant: Re: UNKNOWN Processor Version (0) in XMD
115245: 07/02/05: Zara: Re: UNKNOWN Processor Version (0) in XMD
115101: 07/01/31: Andreas Ehliar: Re: Graphics demo using FPGA?
115102: 07/01/31: Dennis Yurichev: Graphics demo using FPGA?
115104: 07/01/31: Matthias Alles: Re: Graphics demo using FPGA?
115152: 07/02/01: Martin Thompson: Re: Graphics demo using FPGA?
115153: 07/02/01: spartan3wiz: Re: Graphics demo using FPGA?
115179: 07/02/02: Mark McDougall: Re: Graphics demo using FPGA?
115255: 07/02/05: <pbFJKD@ludd.invalid>: Re: Graphics demo using FPGA?
115154: 07/02/01: DC: Re: Graphics demo using FPGA?
115187: 07/02/02: spartan3wiz: Re: Graphics demo using FPGA?
115257: 07/02/05: spartan3wiz: Re: Graphics demo using FPGA?
115110: 07/01/31: <carshie>: cpld version?
115114: 07/01/31: Uwe Bonnes: Re: cpld version?
115116: 07/01/31: Benjamin Todd: Re: cpld version?
115119: 07/01/31: <carshie>: Re: cpld version?
115122: 07/01/31: davide: Re: cpld version?
115126: 07/01/31: <carshie>: Re: cpld version?
115128: 07/01/31: John_H: Re: cpld version?
115135: 07/01/31: <carshie>: Re: cpld version?
115141: 07/01/31: John_H: Re: cpld version?
115145: 07/02/01: <carshie>: Re: cpld version?
115146: 07/01/31: Ben Jackson: Re: cpld version?
115156: 07/02/01: <carshie>: Re: cpld version?
115148: 07/02/01: John_H: Re: cpld version?
115157: 07/02/01: <carshie>: Re: cpld version?
115159: 07/02/01: John_H: Re: cpld version?
115160: 07/02/01: Rob: Re: cpld version?
115124: 07/01/31: Peter Alfke: Re: cpld version?
115147: 07/01/31: Peter Alfke: Re: cpld version?
115117: 07/01/31: Mounard Le Fougueux: DDR FPGA Design
115123: 07/01/31: Nico Coesel: Re: DDR FPGA Design
115133: 07/01/31: <pbFJKD@ludd.invalid>: Re: DDR FPGA Design
115137: 07/01/31: Nico Coesel: Re: DDR FPGA Design
115140: 07/01/31: John_H: Re: DDR FPGA Design
115136: 07/01/31: Nico Coesel: Re: DDR FPGA Design
115182: 07/02/01: Ray Andraka: Re: DDR FPGA Design
115284: 07/02/06: Joseph Samson: Re: DDR FPGA Design
115301: 07/02/06: Nico Coesel: Re: DDR FPGA Design
115125: 07/01/31: Tommy Thorn: Re: DDR FPGA Design
115131: 07/01/31: Peter Alfke: Re: DDR FPGA Design
115139: 07/01/31: Peter Alfke: Re: DDR FPGA Design
115270: 07/02/05: Peter Alfke: Re: DDR FPGA Design
115289: 07/02/05: Tommy Thorn: Re: DDR FPGA Design
115295: 07/02/06: <joerg@zilium.de>: Re: DDR FPGA Design
115118: 07/01/31: Manny: Synthesis of DSP algorithms
115120: 07/01/31: <carshie>: Where is help for schematic entry?
115121: 07/01/31: <carshie>: Re: Where is help for schematic entry?
115130: 07/01/31: Duane Clark: Re: Where is help for schematic entry?
115127: 07/01/31: <carshie>: Question about simple design
115129: 07/01/31: Gabor: Re: Question about simple design
115134: 07/01/31: <carshie>: Re: Question about simple design
115219: 07/02/03: Duth: Re: Question about simple design
115132: 07/01/31: matteo: virtex4 configuration via XCF32P Prom
115142: 07/01/31: davide: Re: virtex4 configuration via XCF32P Prom
115166: 07/02/01: davide: Re: virtex4 configuration via XCF32P Prom
115144: 07/01/31: matteo: Re: virtex4 configuration via XCF32P Prom
115138: 07/01/31: pallav: EDA course development
115143: 07/01/31: pallav: EDA course development
115150: 07/01/31: <pcvijay30@gmail.com>: Xc2v6000 package for ise
115167: 07/02/01: davide: Re: Xc2v6000 package for ise
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