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Hello everybody, today I tried to use an USB Xlinix Multilinx cable (DLC6) with ISE 9.1. To OS is Windows XP, SP2. Whenever I plug the device, Windows asks for a driver and iMPACT doesn't find any cables. I re-installed ISE 9.1 three times, with and without service pack 1. Finally, I tried the serial connector of the Multilinx, which also didn't work. Does anyone have an idea what is wrong? Thank You very much, Markus FrasArticle: 114876
Markus Fras wrote: > Hello everybody, > > today I tried to use an USB Xlinix Multilinx cable (DLC6) with ISE 9.1. > To OS is Windows XP, SP2. Whenever I plug the device, Windows asks for a > driver and iMPACT doesn't find any cables. I re-installed ISE 9.1 three > times, with and without service pack 1. > Finally, I tried the serial connector of the Multilinx, which also > didn't work. > Does anyone have an idea what is wrong? > The MultiLINX cable is not supported in ISE 9.1i as it has been discontinued. Ed McGettigan -- Xilinx Inc.Article: 114877
Hello Ed McGettigan, that's sad to hear; we have three of the devices around at our company. So what do we do with them, throw them in the bin and by new ones? Markus Fras Ed McGettigan schrieb: > Markus Fras wrote: >> Hello everybody, >> >> today I tried to use an USB Xlinix Multilinx cable (DLC6) with ISE >> 9.1. To OS is Windows XP, SP2. Whenever I plug the device, Windows >> asks for a driver and iMPACT doesn't find any cables. I re-installed >> ISE 9.1 three times, with and without service pack 1. >> Finally, I tried the serial connector of the Multilinx, which also >> didn't work. >> Does anyone have an idea what is wrong? >> > > The MultiLINX cable is not supported in ISE 9.1i as it has been > discontinued. > > Ed McGettigan > -- > Xilinx Inc.Article: 114878
Thanks por the advice, I'm going to modify my ADV7125 driver to work with HSYNC VSYNC and CLK signals only. Regards GerardoArticle: 114879
On Jan 25, 11:31 am, Markus Fras <f...@mppmu.mpg.de> wrote: > Hello Ed McGettigan, > > that's sad to hear; we have three of the devices around at our company. > So what do we do with them, throw them in the bin and by new ones? Call your rep and demand that they supply you with supported replacements, gratis. -aArticle: 114880
On Jan 24, 4:06 pm, <steve.l...@xilinx.com> wrote: > Doug, > > The case was created on December 6, 2006. We reproduced the problem in-house > and > created the CRs on December 13. This was after 9.1i was released. > > CR 430822 is a memory leak and has been scheduled to be fixed in 10.1 to > coincide with > an intiative we have to fix memory issues. We're going to try to fix CR > 430823 in 9.2. So a memory-leak bug that Doug tells us has been in the tools for like FIVE major releases is now "scheduled to be fixed in 10.1," which will ship ... when? -aArticle: 114881
I am not doing any image filtering. This is not a filtering operation. It is an interpolation operation typically bilinear or bicubic to do image transformations. On Jan 25, 1:00 pm, "Pete Fraser" <pfra...@covad.net> wrote: > "wallge" <wal...@gmail.com> wrote in messagenews:1169747314.537493.237140@l53g2000cwa.googlegroups.com... > > > > > Image pixels: > > N2 N3 N4 > > N1 P N5 > > N8 N7 N6Have you thought about what order of filtering you'll > need to use?Article: 114882
Markus, The Multilinx cable is not supported in this ISE release. This can be verified in the 9.1i software manual under iMPACT help. Check the search index for supported cables and you will see that Multilinx is not listed. I may be wrong about this, but I believe that support ended with 7.1i. Whichever the last release is that includes the needed drivers, you can download the WebPACK version and be able to use the cable for programming. On a side note, why Multilinx? It is obsolete for a reason (it was horribly slow and was very expensive). If you are limited by only having a USB port available, I would recommned using the latest Platform USB cable or the parallel port PC4 cable. -David "Markus Fras" <fras@mppmu.mpg.de> wrote in message news:eparib$2avf$1@gwdu112.gwdg.de... > Hello everybody, > > today I tried to use an USB Xlinix Multilinx cable (DLC6) with ISE 9.1. To > OS is Windows XP, SP2. Whenever I plug the device, Windows asks for a > driver and iMPACT doesn't find any cables. I re-installed ISE 9.1 three > times, with and without service pack 1. > Finally, I tried the serial connector of the Multilinx, which also didn't > work. > Does anyone have an idea what is wrong? > > Thank You very much, > > Markus FrasArticle: 114883
Thanks Brad...It's works!!! I removed the code for Blank and Sync lines and force the rgb channels to black in the front porch, sync pulse and back porch. In my original driver it's no matter the data in rgb channels, because Blank and sync lines force the blanking. Thank you very much for the advice, I solved in less than five minutes. Regards Gerardo SosaArticle: 114884
I don't have the answer to your question, but thought to point out that the latest service pack for 8.2 is service pack 3 so you don't have to go through the download progress again. Cheers, Jim http://home.comcast.net/~jimwu88/tools/ On Jan 25, 6:46 am, "lbo_user" <shareef.jal...@lightblueoptics.com> wrote: > The Xilinx server is taking forever to serve the latest service pack. > Does anyone know of a UK mirror for it or can anyone host it for me? > > Thanks.Article: 114885
doug <doug@doug> wrote: > Memory leaks are due to sloppy or incompetent programmers. Not fixing > them is due to poor management. Obviously I can't speak for Xilinx, but IME some leaks are due to design errors that can require whole subsystems to be rewritten to fix properly. That alone makes such fixes unsuitable for service packs, and when you additionally have to take into account how the fix affects other subsystems then postponing it to a future major release isn't as dumb as it seems. At work I have to deal with these types of issues all the time (very large, old codebase with new features continually being added and no documentation for the underlying design). -aArticle: 114886
Does anyone know where I can get the OrCAD symbol for the Xilinx V5LX50 FF676 device?Article: 114887
steve.lass@xilinx.com wrote: > Doug, > > The case was created on December 6, 2006. We reproduced the problem in-house > and > created the CRs on December 13. This was after 9.1i was released. > > CR 430822 is a memory leak and has been scheduled to be fixed in 10.1 to > coincide with > an intiative we have to fix memory issues. We're going to try to fix CR > 430823 in 9.2. > > Regarding spending an hour running Valgrind and finding all of the memory > leaks, that might > make sense for a smaller application, but isn't possible for a multi-million > line program that > has a large number of developers. We do use Valgrind and have spent at least > a man year > on this resulting in many of the issues found and fixed, but not all. > > Steve > > Thank you for your reply but it does leave me puzzled. I am not the only one to have experienced memory leak problems with ISE as shown by the warnings on your website. Xilinx has known about the memory leak problems for at least a year now. Xilinx does not plan to fix the memory leak problems for another year. That means you are shippin nonfunctional software for TWO YEARS. This is something that would do Microsoft proud and is a poweerful argument for open source software. Memory leaks are due to sloppy or incompetent programmers. Not fixing them is due to poor management. Things like scheduling bug fixes for releases is also odd. What are service packs for? Are there so many pressing bugs that you have a year's worth of bug fixes lined up? This is a scary thought. I hope it just means that the management puts little effort into bug fixes and only works on them when there is nothing else to do. Of course, that is scary as well. I realize that you and Austin and Peter are not personally responsible for these issues but you are the only ones we have to discuss the issues with. These comments are not out of anger but rather out of frustration. Thank you for taking the time.Article: 114888
On Jan 24, 5:13 pm, Matthew Hicks <mdhic...@uiuc.edu> wrote: > Those aren't digital logic books, those are computer architecture books. > For my first course in logic design I used "Fundamentals of Logic Design" > by Roth. For a mix of logic design and HDL, "Advanced Digital Design with > the Verilog HDL" by Ciletti is quite good, but more advanced. I personally > wanted to read "Digital Design: Principles and Practices" by Wakerly, which > got good reviews but may be on the advanced side of things. Mhh, the Ciletti book looks good. What I am struggling with is, once done with simple building blocks, how to put them together in a whole design. I found another book along that line: "Advanced Digital Logic Design Using Verilog, State Machines, and Synthesis for FPGA's" by Sunggu Lee http://www.amazon.com/Advanced-Digital-Verilog-Machines-Synthesis/dp/0534551610/sr=8-6/qid=1169760050/ref=sr_1_6/103-6992646-3335035?ie=UTF8&s=books http://www.engineering.thomsonlearning.com/products/productPage.aspx?isbn=0534551610 Will see whether I can find some more information about it. GuenterArticle: 114889
<george_granata@hotmail.com> wrote in message news:1169758971.659992.128940@j27g2000cwj.googlegroups.com... > Does anyone know where I can get the OrCAD symbol for the Xilinx V5LX50 > FF676 device? > http://www.fpga-faq.com/FAQ_Pages/0027_Creating_PCB_symbols_for_FPGAs_using_ORCAD.htm HTH, SymsArticle: 114890
"wallge" <wallge@gmail.com> wrote in message news:1169753051.309748.114380@q2g2000cwa.googlegroups.com... >I am not doing any image filtering. Yes you are. > This is not a filtering operation. Yes it is. > It is an interpolation operation > typically bilinear or bicubic > to do image transformations. And that's a filtering operation. So the maximum kernel size is 4 x 4, though you might use 2 x 2. The kernel size could have a substantail bearing on the traffic to/from on-chip RAM. I'm still not sure of your limitations on off-chip RAM. You have a buffer on the input or output (or both?) Do you have enough bandwidth to have an intermediate buffer for a two-pass operation?Article: 114891
George, Xilinx does not support package symbols for OrCAD, but there is a way to convert .pkg files to the .pin format. See Answer Record 10078 for more details on this. http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=10078 -David <george_granata@hotmail.com> wrote in message news:1169758971.659992.128940@j27g2000cwj.googlegroups.com... > Does anyone know where I can get the OrCAD symbol for the Xilinx V5LX50 > FF676 device? >Article: 114892
Can you write out the FIR filter coeffs for a bilinear interpolation "filter kernel"? How about a bicubic interpolator filter kernel what are its filter coeffs? arguing semantics was not the purpose of my post. I will probably wind up doing bilinear interpolation or "filtering". Which means I need 4 pixels of the input frame to determine 1 pixel of output warped frame. By the way what is the Freq response of the bilinear interpolation "filter"? On Jan 25, 5:16 pm, "Pete Fraser" <pfra...@covad.net> wrote: > "wallge" <wal...@gmail.com> wrote in messagenews:1169753051.309748.114380@q2g2000cwa.googlegroups.com... > > >I am not doing any image filtering.Yes you are. > > > This is not a filtering operation.Yes it is. > > > It is an interpolation operation > > typically bilinear or bicubic > > to do image transformations.And that's a filtering operation. > So the maximum kernel size is 4 x 4, though > you might use 2 x 2. The kernel size could have a substantail > bearing on the traffic to/from on-chip RAM. > > I'm still not sure of your limitations on off-chip RAM. > You have a buffer on the input or output (or both?) > Do you have enough bandwidth to have an > intermediate buffer for a two-pass operation?Article: 114893
Thomas Stanka wrote: > Hi, > > On 25 Jan., 11:15, jetm...@hotmail.com wrote: >> For example I'm thinking about an oscillating combinatorial loop, >> sampled during the regular clock events. I expect the output would vary >> (at least a little bit) with temperature, supply voltage and perhaps >> moon phase. >> >> What other V4FX resources could be (mis)used for this purpose? I'd like >> to use two or three unrelated methods. > > What about multiplying clock with the DCM as fast as possible and clock > a counter (designed to be as slow as possible) with that clock? Best > solutions should be achieved before the DCM is locked ;). This approach > wont give you true random numbers but the vary should be > nondeterministic enough to be useable as seed generator for a lfsr. > I would be careful using an un-locked PLL as a source. I tried that about 20 years ago, using discretes, & gave it up. It proved highly non-random. [Part of my Master's thesis: I was using a 74S124 VCO, with a sampling-type phase detector running from a sinusoidal reference. VCO frequency about 4MHz, reference 132kHz.]Article: 114894
Hi, I have been trying to port MontaVista Linux 3.1 to ML403 board. The source compilation was successful. I have set up the NFS and DHCP as well. However, when trying to run MV on ML403, the kernel hangs on : Freeing unused kernel memory: 60k init. Does anybody know how to solve this problem? Thanks. MayaArticle: 114895
Hi, I have been trying to port MontaVista Linux 3.1 to ML403 board. The source compilation was successful. I have set up the NFS and DHCP as well. However, when trying to run MV on ML403, the kernel hangs on : Freeing unused kernel memory: 60k init. Does anybody know how to solve this problem? Thanks. MayaArticle: 114896
Hi:
After further attempts to use Xilinx Webpack 8.2i for Coolrunner XPLA3 I
have discovered the following situation which makes it rather disappointing:
1. I have a very simple schematic design which uses logic library
elements such as "FDC" and basic logic gates.
2. The resulting Verilog file created from the schematic encapsulates
the FDC in a Verilog module wrapper at the top of the file, with my
design as a module following. (I have pasted an example text below of
the .v(f) file)
3. Because the FDC wrapper module appears first in the file, it appears
that the PACE tool thinks that it should assign package pins to the IOs
for the FDC rather than my design's IOs. Ie, PACE gives me the list of
FDC IOs: C, CLR, D, Q to which to assign package pins. This is clearly
not what is desired.
4. The Xilinx Constraints Editor no longer allows pin assignments,
because it interprets all location constraints as read-only.
It seems that if I create a .ucf file to assign pins by hand with the
"Edit Constraints (text)" then the resulting file will work to cause the
desired pin assignments when implementing the design.
But this is pretty strange. The inability of the Xilinx Constraints
Editor to assign location constraints to ports, and the inability to use
PACE make 8.2i an effective downgrade from the 5.2i I was using previously.
Is anyone else attempting to do schematic design with Webpack 8.2i and
seeing the same behavior?
Thanks for input.
----------------------------------------------------------------------
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 8.2i
// \ \ Application : sch2verilog
// / / Filename : pd3state.vf
// /___/ /\ Timestamp : 01/25/2007 15:28:18
// \ \ / \
// \___\/\___\
//
//Command: D:\Xilinx\bin\nt\sch2verilog.exe -intstyle ise -family xpla3
-w E:/xilinx/fast-shutter/WebPack8.2i/012507/pd3state.sch pd3state.vf
//Design Name: pd3state
//Device: xpla3
//Purpose:
// This verilog netlist is translated from an ECS schematic.It can be
// synthesized and simulated, but it should not be modified.
//
`timescale 1ns / 1ps
module FDC_MXILINX_pd3state(C,
CLR,
D,
Q);
input C;
input CLR;
input D;
output Q;
wire XLXN_5;
GND I_36_55 (.G(XLXN_5));
FDCP U0 (.C(C),
.CLR(CLR),
.D(D),
.PRE(XLXN_5),
.Q(Q));
endmodule
`timescale 1ns / 1ps
module pd3state(M1_REF_IN,
M1_SYNC_BUF,
M1_SYNC,
PFD1_QHI,
PFD1_QLO);
input M1_REF_IN;
input M1_SYNC_BUF;
output M1_SYNC;
output PFD1_QHI;
output PFD1_QLO;
wire XLXN_3;
wire XLXN_4;
wire XLXN_5;
FDC_MXILINX_pd3state XLXI_1 (.C(M1_SYNC),
.CLR(XLXN_3),
.D(XLXN_5),
.Q(PFD1_QLO));
// synthesis attribute HU_SET of XLXI_1 is "XLXI_1_0"
FDC_MXILINX_pd3state XLXI_2 (.C(M1_REF_IN),
.CLR(XLXN_3),
.D(XLXN_4),
.Q(PFD1_QHI));
// synthesis attribute HU_SET of XLXI_2 is "XLXI_2_1"
AND2 XLXI_3 (.I0(PFD1_QLO),
.I1(PFD1_QHI),
.O(XLXN_3));
VCC XLXI_5 (.P(XLXN_4));
VCC XLXI_6 (.P(XLXN_5));
IBUF XLXI_7 (.I(M1_SYNC_BUF),
.O(M1_SYNC));
endmodule
----------------------------------------------------------------------
--
Good day!
________________________________________
Christopher R. Carlen
Principal Laser&Electronics Technologist
Sandia National Laboratories CA USA
crcarleRemoveThis@BOGUSsandia.gov
NOTE, delete texts: "RemoveThis" and
"BOGUS" from email address to reply.
Article: 114897"wallge" <wallge@gmail.com> wrote in message news:1169766685.898182.155950@v45g2000cwv.googlegroups.com... > Can you write out the FIR filter coeffs for > a bilinear interpolation "filter kernel"? > How about a bicubic interpolator filter kernel > what are its filter coeffs? I'm happy to, but we're getting away from FPGA stuff, so let's do that off line. Let me know how many phases you need, and the coefficient format you'd like. I usually use a minor 4x4 variation on cubic, but it's all set up in Mathematica, so I could do cubic also. > > arguing semantics was not the purpose of my post. > > I will probably wind up doing bilinear interpolation or > "filtering". Which means I need 4 pixels of the input frame to > determine > 1 pixel of output warped frame. So you don't really need coefficient tables for this. You can just use the fractional phase directly. > > By the way what is the Freq response of the bilinear interpolation > "filter"? It depends on the position of output relative to input pixel, but for a central output pixel the frequency response would be Cosusoidal. Getting back to FPGA stuff though, what are your off-chip RAM bandwidth limitations, and could you consider a two-pass approach? >> I'm still not sure of your limitations on off-chip RAM. >> You have a buffer on the input or output (or both?) >> Do you have enough bandwidth to have an >> intermediate buffer for a two-pass operation? >Article: 114898
Hello group, I ran into an ugly ModelSim6 warning saying that I had too many "leaf instances" or lines of code, and that my performance was going to be severly affected. Sure was. A simulation that normally runs in about a minute now takes an hour. I traced the problem down to instantiated primitive FIFOs that I replaced with an inferred memory. Why does this work? Fewer instances to be sure, but not less hardware. This appears to be an arbitrary ceiling imposed by the marketing people at Mentor. Although I have a temporary fix, questions arise: 1) What is a "Leaf" instance? 2) How do I know when I'm running out of room? 3) What are the best practices to get the most out of the ModelSim XE starter? Thanks, Brad Smallridge AiVisionArticle: 114899
On 2007-01-25, sh3.m4y4 <sh3.m4y4@gmail.com> wrote: > Freeing unused kernel memory: 60k init. Does anybody know how to solve > this problem? Thanks. Make sure your on-chip peripheral (OCP) setup exactly matches what you have in your bitstream. There's no probing (and no way to probe) for most of these devices, so your kernel must exactly match your .bit. -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/
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