Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Threads Starting Sep 1996
4000: 96/09/01: AP: *** FREE INTERNET! *** Forever!
4011: 96/09/03: Tim Forcer: No such thing ....
4020: 96/09/03: Peter Alfke: Re: *** FREE INTERNET! *** Forever!
4002: 96/09/01: Andrew Metcalfe: Xilinx Foundation w/64Mb RAM
4027: 96/09/04: Rafiki Kim Hofmans: Re: Xilinx Foundation w/64Mb RAM
4003: 96/09/02: David Pellerin: Re: ANNOUNCE: $499 PeakVHDL Training Edition Simulator
4009: 96/09/02: Richard J. Auletta: Re: ANNOUNCE: $499 PeakVHDL Training Edition Simulator
4004: 96/09/02: muliani: Address of ALTERA & XILINX
4042: 96/09/05: Marc Baker: Re: Address of ALTERA & XILINX
4007: 96/09/02: Navneet S Yadav: Gate Count - Notion of Gate
4100: 96/09/10: Richard Vireday: Re: Gate Count - Notion of Gate
4123: 96/09/13: G. Herrmannsfeldt: Re: Gate Count - Notion of Gate
4008: 96/09/02: Mark Smotherman: query: C to FPGA?
4015: 96/09/03: Don Husby: Re: query: C to FPGA?
4016: 96/09/03: Ray Heasman: Re: query: C to FPGA?
4031: 96/09/04: Scott A. Hauck: Re: query: C to FPGA?
4013: 96/09/03: Jean Paul Heron -COD-RW: Xact 6000
4017: 96/09/03: fuseda: XACT STEP 6.0.1 SETUP PROBLEM
4023: 96/09/03: DTHIBAUL: Re: XACT STEP 6.0.1 SETUP PROBLEM
4045: 96/09/05: Hideki Itoh: Re: XACT STEP 6.0.1 SETUP PROBLEM
4018: 96/09/03: Scott A. Hauck: FPGA '97 CFP: Due date in less than a month
4026: 96/09/04: Alex Koegel: Synopsys Timing Analysis on Altera (flex10K) back-annotated design
4028: 96/09/04: Jae Cho: speed up Xilinx P & R
4030: 96/09/04: Philip Freidin: Re: speed up Xilinx P & R
4033: 96/09/04: David J. Matthews: Re: speed up Xilinx P & R
4044: 96/09/05: Andy Gulliver: Re: speed up Xilinx P & R
4047: 96/09/05: Wayne Turner: Re: speed up Xilinx P & R
4029: 96/09/04: muliani: What is the REAL address of XOILINX and ALTERA?
4037: 96/09/05: Wayne Turner: Re: What is the REAL address of XOILINX and ALTERA?
4046: 96/09/05: Philip Freidin: Re: What is the REAL address of XOILINX and ALTERA?
4035: 96/09/05: Lawrence Butcher: synopsys vs. xilinx floor-planning
4036: 96/09/05: Nabeel Robert Ibrahim: *** EE/CS Mother Site ***
4038: 96/09/05: apda: test
4039: 96/09/05: Stefan Ludwig: Help: Code for adder circuit in VHDL/Verilog
4040: 96/09/05: Quy Dinh: PCI Bus Protocal & FPGA vendors
4055: 96/09/06: Rafiki Kim Hofmans: Re: PCI Bus Protocal & FPGA vendors
4114: 96/09/12: Raymond Gaita: Re: PCI Bus Protocal & FPGA vendors
4120: 96/09/13: Raymond Gaita: Re: PCI Bus Protocal & FPGA vendors
4041: 96/09/05: gary crothers: DISTRIBUTORS
4043: 96/09/05: Tobias Schuele: PCI compliant FPGA / free P&R software
4048: 96/09/05: Patrick Jarry: Warp2 realease 4.0 ??
4050: 96/09/05: Rob Semenoff: Re: Warp2 realease 4.0 ??
4066: 96/09/06: Rob Semenoff: Re: Warp2 realease 4.0 ??
4122: 96/09/13: Robert Fuchs: Re: Warp2 realease 4.0 ??
4049: 96/09/06: Brad Wallace: FPGA design project
4064: 96/09/06: Ray Andraka: Re: FPGA design project
4084: 96/09/09: Alfred Fuchs: Re: FPGA design project
4091: 96/09/10: Andrew Phillips: Re: FPGA design project
4104: 96/09/10: Ray Andraka: Re: FPGA design project
4106: 96/09/10: Wen-King Su: Re: FPGA design project
4087: 96/09/09: Peter Alfke: Re: FPGA design project
4051: 96/09/06: Paul Donachy: XC6200 based image processing coprocessor
4052: 96/09/06: Richard Jozefowski: ORCA and Viewlogic - any good?
4067: 96/09/06: Don Husby: Re: ORCA and Viewlogic - any good?
4072: 96/09/08: Richard Jozefowski: Re: ORCA and Viewlogic - any good?
4079: 96/09/09: David Pashley: Re: ORCA and Viewlogic - any good?
4080: 96/09/09: Don Husby: Re: ORCA and Viewlogic - any good?
4090: 96/09/09: Peter: Re: ORCA and Viewlogic - any good?
4093: 96/09/10: Philip Freidin: Re: ORCA and Viewlogic - any good?
4094: 96/09/10: Don Husby: Re: ORCA and Viewlogic - any good?
4110: 96/09/11: Peter: Re: ORCA and Viewlogic - any good?
4111: 96/09/11: Alan Weir: Re: ORCA and Viewlogic - any good?
4112: 96/09/12: Philip Freidin: Re: ORCA and Viewlogic - any good?
4069: 96/09/07: Peter: Re: ORCA and Viewlogic - any good?
4076: 96/09/09: David Decker: Re: ORCA and Viewlogic - any good?
4083: 96/09/09: Tom Bowns: Re: ORCA and Viewlogic - any good?
4053: 96/09/06: alain arnaud: ViewSynthesis and Xilinx
4089: 96/09/09: Jean-Paul Smeets: Re: ViewSynthesis and Xilinx
4056: 96/09/06: Constantin Jean-Claude: EPROM Xilinx second source
4057: 96/09/06: Cecil Kaplinsky: Re: EPROM Xilinx second source
4081: 96/09/09: Don Husby: Re: EPROM Xilinx second source
4058: 96/09/06: B. Mitchell Loebel: The PARALLEL Processing Connection - What Is It?
4059: 96/09/06: B. Mitchell Loebel: The PARALLEL Processing Connection - September 9th Meeting Notice
4060: 96/09/06: B. Mitchell Loebel: PARALLEL Processing Connection - September 9th Meeting Notice
4061: 96/09/06: Rob Hurley: ANNOUNCE: New FREE Model of the Month - Sept
4062: 96/09/06: Rob Hurley: ANNOUNCE: New Tip of the Month - Sept
4063: 96/09/06: Tom Tooley: ..people NOT using Xilinx
4073: 96/09/08: Soren Kristensen: Re: ..people NOT using Xilinx
4099: 96/09/10: Peter Alfke: Re: ..people NOT using Xilinx
4065: 96/09/06: DTHIBAUL: Help with XACT 6.0 ProSim Problem
4070: 96/09/07: Rafiki Kim Hofmans: Re: Help with XACT 6.0 ProSim Problem
4075: 96/09/09: David Decker: Re: Help with XACT 6.0 ProSim Problem
4096: 96/09/10: David Pashley: Re: Help with XACT 6.0 ProSim Problem
4068: 96/09/06: <sbaker@best.com[Stan Baker]>: Re-usable cores & macros report
4071: 96/09/07: Peter Alfke: 256K EEPROM
4108: 96/09/11: Martin Mason: Re: 256K EEPROM
4154: 96/09/19: Mark Shand: Re: 256K EEPROM
4077: 96/09/09: David Decker: DSP capture tools
4088: 96/09/09: Jean-Paul Smeets: Xilinx ViewLogic package and simulating VHDL
4092: 96/09/10: Andrew Phillips: Which FPGA design tools do you use ??
4103: 96/09/10: Lance Gin: Re: Which FPGA design tools do you use ??
4095: 96/09/10: Paul Donachy: Feedback on Xilinx XC6200 image processing coprocessor
4097: 96/09/10: kevin: asic,fpga professional assoc.
4098: 96/09/10: John Cooley: ## Cadence: The Good, The Bad, & The Ugly ##
4101: 96/09/10: <hdhunter@usaor.net>: RE: FPGA DESIGNERS
4102: 96/09/10: Chris Humphres: Re: Quick and Easy Money (NOT A SCAM!)
4105: 96/09/11: Michael Covington: Re: Quick and Easy Money (NOT A SCAM!)
4107: 96/09/11: Rainer Scharnow: XChecker and WinNT or OS/2
4109: 96/09/11: Xiangdong Li: How to Begin with FPGA design?
4124: 96/09/13: Janos Szamosfalvi: Re: How to Begin with FPGA design?
4187: 96/09/23: Scott Schlachter: Re: How to Begin with FPGA design?
4201: 96/09/25: Peter Alfke: Re: How to Begin with FPGA design?
4208: 96/09/26: Len Harold: Re: How to Begin with FPGA design?
4113: 96/09/12: roger gook: ? C to FPGA
4132: 96/09/17: Ray Heasman: Re: ? C to FPGA
4115: 96/09/12: saroj rout: Need HELP!!!
4116: 96/09/12: <orachat@imap2.asu.edu>: Implement FPGA multiplier using VHDL synthesis
4121: 96/09/13: Benjamin D Klass: Re: Implement FPGA multiplier using VHDL synthesis
4126: 96/09/15: Kayvon Irani: Re: Implement FPGA multiplier using VHDL synthesis
4117: 96/09/13: Linda Boyd: COURSES: High Level Design Using Verilog, Beaverton, Oregon
4118: 96/09/13: Linda Boyd: COURSES: High Level Design Using VHDL, Beaverton, Oregon
4125: 96/09/16: <DGILL@priacc.com>: manchester clock recovery
4130: 96/09/17: Kirk Hobart: Re: manchester clock recovery
4140: 96/09/17: Herbert Kleebauer: Re: manchester clock recovery
4155: 96/09/19: Peter Alfke: Re: manchester clock recovery
4138: 96/09/17: Peter: Re: manchester clock recovery
4165: 96/09/20: Peter Alfke: Re: manchester clock recovery
4174: 96/09/21: Hal Murray: Re: manchester clock recovery
4175: 96/09/21: Hal Murray: Re: manchester clock recovery
4180: 96/09/22: Peter: Re: manchester clock recovery
4184: 96/09/23: Peter Alfke: Re: manchester clock recovery
4186: 96/09/23: Kenneth A. Becker: Re: manchester clock recovery
4193: 96/09/24: Ray Andraka: Re: manchester clock recovery
4142: 96/09/17: Peter Alfke: Re: manchester clock recovery
4127: 96/09/16: Scott A. Hauck: FPGA'97: Papers due on 9/27/96 (11 days away)
4128: 96/09/16: Rudi Cilibrasi: Good Starting points to learn FPGA for hobbyist?
4129: 96/09/16: Richard J. Auletta: Re: Good Starting points to learn FPGA for hobbyist?
4137: 96/09/17: Peter: Re: Good Starting points to learn FPGA for hobbyist?
4156: 96/09/19: David Van den Bout: Re: Good Starting points to learn FPGA for hobbyist?
4131: 96/09/17: <sjadam@trog.dra.hmg.gb>: Inaccrate Xilinx simulations ???
4133: 96/09/17: Scott Kroeger: Re: Inaccrate Xilinx simulations ???
4148: 96/09/18: Peter Alfke: Re: Inaccrate Xilinx simulations ???
4164: 96/09/20: Simon: Re: Inaccrate Xilinx simulations ???
4136: 96/09/17: bob elkind: Re: Inaccrate Xilinx simulations ???
4141: 96/09/17: <daveb@iinet.net.au>: Re: Inaccrate Xilinx simulations ???
4145: 96/09/18: David Pashley: Re: Inaccrate Xilinx simulations ???
4134: 96/09/17: Detlef Justen: How can I make my XILINX design faster?
4139: 96/09/17: Ray Andraka: Re: How can I make my XILINX design faster?
4135: 96/09/17: Scott A. Hauck: FPGA'97: New due date, papers to appear in special issue of TVLSI
4143: 96/09/18: Rensheng Horng: Wanted: Verilog, Synopsys, ASIC
4144: 96/09/18: M. Movahedin: A Survey on Design Errors
4146: 96/09/18: Luis Sanchez Fernandez: CHDL '97
4147: 96/09/18: Sam: Cypress FPGA/Warp2--Any Good?
4149: 96/09/18: Gray Creager: *** finding datasheets and chipmakers on the web ***
4183: 96/09/23: Frank Adlam: Re: *** finding datasheets and chipmakers on the web ***
4150: 96/09/18: Jason Crawford: OrCAD schematic based multiplier for XC4000 series
4160: 96/09/20: David Decker: Re: OrCAD schematic based multiplier for XC4000 series
4161: 96/09/20: David Decker: Re: OrCAD schematic based multiplier for XC4000 series
4151: 96/09/19: Ray Heasman: Are there any FPGA Starter Kits?
4152: 96/09/19: Uwe Bonnes: Re: Are there any FPGA Starter Kits?
4157: 96/09/19: David Van den Bout: Re: Are there any FPGA Starter Kits?
4177: 96/09/22: Richard Schwarz: Re: Are there any FPGA Starter Kits?
4153: 96/09/19: Ed Barrett: Re: Good starting point to learn FPGA for hobbyist?
4158: 96/09/19: Vincent Rowley: FPGAs design tools for PC
4162: 96/09/20: Tony Disanto: Re: FPGAs design tools for PC
4163: 96/09/20: John L. Smith: Re: FPGAs design tools for PC
4178: 96/09/22: Richard Schwarz: Re: FPGAs design tools for PC
4159: 96/09/20: Snowbin: Crosspoint FPGA
4166: 96/09/20: John Schewel: Starter Boards
4167: 96/09/21: Andre' DeHon: BRASS and Re: query: C to FPGA
4182: 96/09/23: Maya Gokhale: Re: query: C to FPGA
4168: 96/09/21: Michael Payne: Q: PLD vs. FPGA
4172: 96/09/21: David Decker: Re: Q: PLD vs. FPGA
4173: 96/09/21: David Decker: Re: Q: PLD vs. FPGA
4203: 96/09/25: Janos Szamosfalvi: Re: Q: PLD vs. FPGA
4211: 96/09/27: <granville@decus.org.nz>: Re: Q: PLD vs. FPGA
4169: 96/09/21: ISPD-97 Organization: CFP - Int. Symp. on Physical Design, Apr 14-16, CA
4170: 96/09/21: Michael Payne: What's the difference between PLD and FPGA?
4171: 96/09/21: Michael Payne: What's the difference between PLD and FPGA?
4176: 96/09/21: Workshop - Gabe Robins: ISPD-97 Call for Papers
4179: 96/09/22: Richard Schwarz: Inexpensive XILINX FPGA STARTER BOARDS
4181: 96/09/23: <smith@q.continuum.net>: test
4185: 96/09/23: Bill Seiler: Source for FPGA and PCI prototype board ???
4189: 96/09/24: Pak K. Chan: Re: Source for FPGA and PCI prototype board ???
4188: 96/09/23: K. S. Venkatraman: FIR filter using FPGAs??
4215: 96/09/28: Richard Schwarz: Re: FIR filter using FPGAs??
4190: 96/09/24: Vedran Maler RIP pa konst. Zagar: XilinX XC5200 address pointer based FIFO
4194: 96/09/24: Ray Andraka: Re: XilinX XC5200 address pointer based FIFO
4207: 96/09/26: Peter Alfke: Re: XilinX XC5200 address pointer based FIFO
4221: 96/10/01: Marc Baker: Re: XilinX XC5200 address pointer based FIFO
4191: 96/09/24: Eric Jay Crabill: FS: Data IO MESA-I
4192: 96/09/24: Kiran Kumar Bondalapati: FPGA Routing Question
4195: 96/09/25: Philip Freidin: Re: FPGA Routing Question
4196: 96/09/25: Wouter Suverkropp: Xilinx X-blox Bidir_IO padnames?
4197: 96/09/25: Andy Gulliver: Re: Xilinx X-blox Bidir_IO padnames?
4198: 96/09/25: Curt Schibonski: 4800 baud serial input to xc4000
4202: 96/09/25: Ray Andraka: Re: 4800 baud serial input to xc4000
4204: 96/09/25: John L. Smith: Re: 4800 baud serial input to xc4000
4209: 96/09/26: Peter Alfke: Re: 4800 baud serial input to xc4000
4199: 96/09/25: alain arnaud: XUMA #16
4200: 96/09/25: A. Spanias: CDMA DSP
4205: 96/09/26: Teppo Hemia: Partition tool for FPGAs?
4226: 96/10/02: David Pashley: Re: Partition tool for FPGAs?
4264: 96/10/07: Bill Seiler: Re: Partition tool for FPGAs?
4206: 96/09/26: Andreas Doering: hardware implementation of permutation multiplication
4212: 96/09/27: Herman Rubin: Re: hardware implementation of permutation multiplication
4210: 96/09/27: Jackie Meyer: CFP: Design and Test
4213: 96/09/27: Soren Kristensen: Source for 8259 PIC
4216: 96/09/29: Peter: Re: Source for 8259 PIC
4214: 96/09/28: 1997 International Symposium on Physical Design: CFP - 1997 Intl. Symp. on Physical Design, April 14-16, CA
4217: 96/09/30: Thomas Scherrer: Z8000 microprocessors, C cross-compiler and a PLZ/ASM assembler
4218: 96/09/30: Eric Page: money maker
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
