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Threads Starting Oct 1999
18112: 99/10/01: anup kumar raghavan: Are all SRAM based FPGAs -Reconfigurable devices.
18113: 99/09/30: Ray Andraka: Re: Are all SRAM based FPGAs -Reconfigurable devices.
18114: 99/10/01: senget: Evaluation/Development Board with SA-11XX Processor
18128: 99/10/02: Austin Franklin: Re: Evaluation/Development Board with SA-11XX Processor
18134: 99/10/02: senget: Re: Evaluation/Development Board with SA-11XX Processor
18115: 99/10/01: Rémi SEGLIE: ATM srambler
18145: 99/10/03: Ray Andraka: Re: ATM srambler
18156: 99/10/04: <rseglie@my-deja.com>: Re: ATM srambler
18158: 99/10/04: Ray Andraka: Re: ATM srambler
18187: 99/10/06: <rseglie@my-deja.com>: Re: ATM srambler
18191: 99/10/06: Ray Andraka: Re: ATM srambler
18247: 99/10/09: David Tang: Re: ATM srambler
18118: 99/10/01: <martin_at_deja@my-deja.com>: Slice (or CLB) count
18123: 99/10/01: <eml@riverside-machines.com.NOSPAM>: Re: Slice (or CLB) count
18125: 99/10/01: Ray Andraka: Re: Slice (or CLB) count
18162: 99/10/04: <martin_at_deja@my-deja.com>: Re: Slice (or CLB) count
18119: 99/10/01: <aaronburgess@ieee.org>: Implementing a LFSH in Xilinx XC9500 series
18121: 99/10/01: Edwin Naroska: Re: Implementing a LFSH in Xilinx XC9500 series
18124: 99/10/01: Peter Alfke: Re: Implementing a LFSH in Xilinx XC9500 series
18122: 99/10/01: Paul Barton: Moto 6809E
18126: 99/10/01: Tyrone Thompson: Producing 60/40 clock in vhdl
18130: 99/10/02: Wade D. Peterson: Re: Producing 60/40 clock in vhdl
18136: 99/10/02: Ray Andraka: Re: Producing 60/40 clock in vhdl
18138: 99/10/03: Ray Andraka: Re: Producing 60/40 clock in vhdl
18139: 99/10/03: Ray Andraka: Re: Producing 60/40 clock in vhdl
18147: 99/10/03: Alvin E. Toda: Re: Producing 60/40 clock in vhdl
18150: 99/10/03: Ray Andraka: Re: Producing 60/40 clock in vhdl
18181: 99/10/05: Tyrone Thompson: Re: Producing 60/40 clock in vhdl
18183: 99/10/05: Ray Andraka: Re: Producing 60/40 clock in vhdl
18135: 99/10/02: Ray Andraka: Re: Reconfigurable FPGAs-- A query on this..
18137: 99/10/02: Ray Andraka: Re: Reconfigurable FPGAs-- A query on this..
18140: 99/10/03: Ray Andraka: Re: Reconfigurable FPGAs-- A query on this..
18142: 99/10/03: Tim Tyler: Re: Reconfigurable FPGAs-- A query on this..
18148: 99/10/03: Peter Alfke: Re: Reconfigurable FPGAs-- A query on this..
18144: 99/10/03: Marcelo Enrique Moisan Naulin: A question
18149: 99/10/04: Damjan Lampret: SDRAM&PCI controller
18163: 99/10/04: Edwin Naroska: Re: SDRAM&PCI controller
18151: 99/10/04: Victor Levandovsky: Does anyone have a Altera BitBlaster shematic? (0)
18152: 99/10/04: Georg Diebel: Re: Does anyone have a Altera BitBlaster shematic? (0)
18153: 99/10/04: Leslie Yip (/ Loui): APEX device
18154: 99/10/04: Nicolas Matringe: Re: APEX device
18155: 99/10/04: Ilia Oussorov: Clock multiplexing in Virtex
18159: 99/10/04: Ray Andraka: Re: Clock multiplexing in Virtex
18160: 99/10/04: Andrew Bunsick: Contract Design Services
18161: 99/10/04: Bob Weber: ABEL for CPLD Design
18164: 99/10/04: Austin Franklin: Re: ABEL for CPLD Design
18166: 99/10/04: John Cain: Re: ABEL for CPLD Design
18169: 99/10/04: Ray Andraka: Re: ABEL for CPLD Design
18414: 99/10/23: Number Cruncher: Re: ABEL for CPLD Design
18165: 99/10/04: Herman Schmit: FPGA 2000: Paper Deadline Extension
18168: 99/10/04: Marcelo Moisan: I need a Link
18171: 99/10/04: Ray Andraka: Re: I need a Link
18172: 99/10/05: Dave Decker: Re: Multiplierless FIR filters in FPGAs
18178: 99/10/05: Dave Decker: Re: Multiplierless FIR filters in FPGAs
18185: 99/10/05: Ray Andraka: Re: Multiplierless FIR filters in FPGAs
18201: 99/10/07: <flavioas@my-deja.com>: Re: Multiplierless FIR filters in FPGAs
18174: 99/10/05: <flavioas@my-deja.com>: Multiplierless FIR filters in FPGAs
18175: 99/10/05: Ray Andraka: Re: Multiplierless FIR filters in FPGAs
18177: 99/10/05: Andy Peters: Re: Multiplierless FIR filters in FPGAs
18207: 99/10/07: jjlarkin: Re: Multiplierless FIR filters in FPGAs
18210: 99/10/07: Ray Andraka: Re: Multiplierless FIR filters in FPGAs
18176: 99/10/05: Margaret Dailey: Designers wanted
18179: 99/10/05: Ravi Singh: Board Designers required
18182: 99/10/06: Rick Filipkiewicz: Xilinx post route simulation
18186: 99/10/06: Austin Franklin: Re: Xilinx post route simulation
18190: 99/10/06: Utku Ozcan: Re: Xilinx post route simulation
18192: 99/10/06: Rick Filipkiewicz: Re: Xilinx post route simulation
18195: 99/10/06: Paulo Dutra: Re: Xilinx post route simulation
18197: 99/10/07: Austin Franklin: Re: Xilinx post route simulation
18184: 99/10/05: Dave Krueger: Altera 10K50V in-rush/temp problem...
18193: 99/10/06: jjlarkin: Re: Altera 10K50V in-rush/temp problem...
18199: 99/10/07: Dave Krueger: Re: Altera 10K50V in-rush/temp problem...
18202: 99/10/07: Allan Herriman: Re: Altera 10K50V in-rush/temp problem...
18213: 99/10/07: Dave Krueger: Re: Altera 10K50V in-rush/temp problem...
18227: 99/10/08: Bob Weber: Re: Altera 10K50V in-rush/temp problem...
18276: 99/10/11: Dave Krueger: Re: Altera 10K50V in-rush/temp problem...
18235: 99/10/08: Tom Burgess: Re: Altera 10K50V in-rush/temp problem...
18277: 99/10/11: Dave Krueger: Re: Altera 10K50V in-rush/temp problem...
18251: 99/10/10: jim granville: Re: Altera 10K50V in-rush/temp problem...
18278: 99/10/11: Dave Krueger: Re: Altera 10K50V in-rush/temp problem...
18264: 99/10/11: Allan Herriman: Re: Altera 10K50V in-rush/temp problem...
18279: 99/10/11: Dave Krueger: Re: Altera 10K50V in-rush/temp problem...
18188: 99/10/06: Tomasz Pinkiewicz: I/O Interface for Xilinx FPGA
18189: 99/10/06: Eduardo Augusto Bezerra: 1ST IEEE LATIN-AMERICAN TEST WORKSHOP
18194: 99/10/06: colin cook: will Xlilnx jtag cable work with as a replacement for Altara's BitBlaster
18196: 99/10/07: Roger Yau: HOT II PCI Development System
18214: 99/10/07: Jim McManus: Re: HOT II PCI Development System
18198: 99/10/07: <wq998@yahoo.com>: Virtex and PCI 5V?
18206: 99/10/07: Peter Alfke: Re: Virtex and PCI 5V?
18215: 99/10/07: Jim McManus: Re: Virtex and PCI 5V?
18200: 99/10/07: Moussa A. Ba: External Cloking of Altera MAX 7000S
18203: 99/10/07: Brad Ree: Re: External Cloking of Altera MAX 7000S
18209: 99/10/07: Andy Peters: Re: External Cloking of Altera MAX 7000S
18212: 99/10/07: Moussa Ba: Re: External Cloking of Altera MAX 7000S
18229: 99/10/08: Mike: Re: External Cloking of Altera MAX 7000S
18240: 99/10/08: Moussa Ba: Re: External Cloking of Altera MAX 7000S
18271: 99/10/11: Andy Peters: Re: External Cloking of Altera MAX 7000S
18390: 99/10/21: <davezz9472@my-deja.com>: Re: External Cloking of Altera MAX 7000S
18408: 99/10/23: Edward Moore: Re: External Cloking of Altera MAX 7000S
18204: 99/10/07: <jgais@ws.estec.esa.nl>: Free SPARC VHDL model available
18208: 99/10/07: TalentLab Inc.: FPGA ???
18211: 99/10/07: PJD: Token-Ring MAC in FPGA?
18280: 99/10/12: <achomyn@madge.com>: Re: Token-Ring MAC in FPGA?
18217: 99/10/08: Anthony Quigley: UK or Europe Des. Engs for California jobs
18233: 99/10/08: Jonathan Bromley: Re: UK or Europe Des. Engs for California jobs
18236: 99/10/08: Stuart Clubb: Re: UK or Europe Des. Engs for California jobs
18218: 99/10/08: Robert Larkin: RAM in xilinx FPGAs.
18219: 99/10/08: Rémi SEGLIE: Re: RAM in xilinx FPGAs.
18221: 99/10/08: Ray Andraka: Re: RAM in xilinx FPGAs.
18222: 99/10/08: Watts: Re: RAM in xilinx FPGAs.
18238: 99/10/09: Utku Ozcan: Re: RAM in xilinx FPGAs.
18244: 99/10/08: Ray Andraka: Re: RAM in xilinx FPGAs.
18239: 99/10/09: Utku Ozcan: Re: RAM in xilinx FPGAs.
18245: 99/10/09: Eduardo Augusto Bezerra: Re: RAM in xilinx FPGAs.
18220: 99/10/08: Daryl Bradley: Preconfigured pull ups
18223: 99/10/08: Mike: Can't detect Flex 10K Altera device through JTAG port
18225: 99/10/08: Armin Mueller: Re: Can't detect Flex 10K Altera device through JTAG port
18228: 99/10/08: Mike: Re: Can't detect Flex 10K Altera device through JTAG port
18255: 99/10/10: Armin Mueller: Re: Can't detect Flex 10K Altera device through JTAG port
18306: 99/10/13: Mike: Re: Can't detect Flex 10K Altera device through JTAG port
18256: 99/10/11: Darryl Jewiss: Re: Can't detect Flex 10K Altera device through JTAG port
18297: 99/10/13: <deroberts@my-deja.com>: Re: Can't detect Flex 10K Altera device through JTAG port
18246: 99/10/09: Steve Rencontre: Re: Can't detect Flex 10K Altera device through JTAG port
18283: 99/10/12: Mike: Re: Can't detect Flex 10K Altera device through JTAG port
18299: 99/10/13: Steve Rencontre: Re: Can't detect Flex 10K Altera device through JTAG port
18258: 99/10/11: Michael Stanton: Re: Can't detect Flex 10K Altera device through JTAG port
18224: 99/10/08: <lothar_brodbeck@my-deja.com>: Announcement: VHDL/FPGA Development Boards (up to 400.000 Gates)
18230: 99/10/08: Steven K. Knapp: Re: Announcement: VHDL/FPGA Development Boards (up to 400.000 Gates) (Corrected Links, More Boards)
18260: 99/10/11: <lothar_brodbeck@my-deja.com>: Re: Announcement: VHDL/FPGA Development Boards (up to 400.000 Gates) (Corrected Links, More Boards)
18302: 99/10/13: <mrauf@nova-eng.com>: Re: Announcement: VHDL/FPGA Development Boards (up to 400.000 Gates) (Corrected Links, More Boards)
18303: 99/10/13: James Birmingham: .cal .rbt file format
18226: 99/10/08: Stephen Charlwood: Capacity metrics for Virtex
18237: 99/10/08: muzo: Re: Capacity metrics for Virtex
18242: 99/10/08: James Yeh: Re: Capacity metrics for Virtex
18241: 99/10/08: Graeme Durant: Re: Capacity metrics for Virtex
18231: 99/10/08: Tom McLaughlin: DLL and programmable delay in Xilinx FPGA
18252: 99/10/10: <eml@riverside-machines.com.NOSPAM>: Re: DLL and programmable delay in Xilinx FPGA
18253: 99/10/10: Phil Hays: Re: DLL and programmable delay in Xilinx FPGA
18232: 99/10/08: Tom McLaughlin: Xchecker cable
18234: 99/10/08: Maximo H. Salinas: GSR on ORCA FPGAs
18261: 99/10/11: Rudolf Simburger: Re: GSR on ORCA FPGAs
18266: 99/10/11: Don Husby: Re: GSR on ORCA FPGAs
18272: 99/10/11: Maximo H. Salinas: Re: GSR on ORCA FPGAs
18284: 99/10/12: Don Husby: Re: GSR on ORCA FPGAs
18291: 99/10/12: Maximo H. Salinas: Re: GSR on ORCA FPGAs
18298: 99/10/13: Dave Storrar: Re: GSR on ORCA FPGAs
18294: 99/10/12: Brian Boorman: Re: GSR on ORCA FPGAs
18243: 99/10/09: John Cooley: Re: Mentor on a Laptop
18292: 99/10/12: Pete Danile: Re: Mentor on a Laptop
18248: 99/10/10: Shen Jiakan: FYI
18249: 99/10/09: John Larkin: test
18250: 99/10/10: X: Lattice 1016 replacement
18281: 99/10/12: <mark_harvey@my-deja.com>: Re: Lattice 1016 replacement
18254: 99/10/10: A person: 1.8V FPGA
18257: 99/10/10: <fidonews2@my-deja.com>: Altera Max+Plus II for sale $1000 (new)
18259: 99/10/11: Jamil Khaib: GNU License for Hardware
18263: 99/10/11: Arthur T. Murray: Re: GNU License for Hardware
18262: 99/10/11: Stephen Charlwood: Any ideas what Xilinx plans for Virtex are?
18286: 99/10/12: Steve: Re: Any ideas what Xilinx plans for Virtex are?
18267: 99/10/11: alfred fuchs: Pull plug quickly!
18350: 99/10/17: Gary Helbig (.): Re: Pull plug quickly!
18268: 99/10/11: Steve Gross: Xilinx Alliance 2.1i Virus
18275: 99/10/11: peter dudley: Re: Xilinx Alliance 2.1i Virus
18269: 99/10/11: Moussa Ba: CLOCK assignment in MAXPLUS2
18273: 99/10/11: Mike Treseler: Re: CLOCK assignment in MAXPLUS2
18270: 99/10/11: Moussa Ba: ALTERA design ---> XILINX
18285: 99/10/12: Steve: Re: ALTERA design ---> XILINX
18289: 99/10/12: Moussa A. Ba: Re: ALTERA design ---> XILINX
18295: 99/10/12: Brian Boorman: Re: ALTERA design ---> XILINX
18274: 99/10/11: <cvxxuq@heal.com>: HEAL YOURSELF 7754
18282: 99/10/12: Lawrence Chai: Wanted: HOTWORKS board
18497: 99/10/27: Wendy Lockhart: Re: Wanted: HOTWORKS board
18287: 99/10/12: John Cooley: SNUG'00 'Abstracts' Deadline Moved From Oct. 11th To Oct. 15th
18288: 99/10/12: Spiro Egarhos: FPGA Design Job
18290: 99/10/12: madQ: Download Ia.n.i.!!! It's free!
18293: 99/10/12: madQ: Download Ia.n.i.!!! It's free!
18296: 99/10/12: Masterbot: ISP-Cable again
18304: 99/10/13: Fuzesi Arnold: Re: ISP-Cable again
18300: 99/10/13: Espen Tislevoll: Interconnecting LUTs on a Virtex
18301: 99/10/13: Ray Andraka: Re: Interconnecting LUTs on a Virtex
18333: 99/10/16: <simon_bacon@my-deja.com>: Re: Interconnecting LUTs on a Virtex
18340: 99/10/16: Ken McElvain: Re: Interconnecting LUTs on a Virtex
18369: 99/10/20: <eml@riverside-machines.com.NOSPAM>: Re: Interconnecting LUTs on a Virtex
18372: 99/10/20: <eml@riverside-machines.com.NOSPAM>: Re: Interconnecting LUTs on a Virtex
18376: 99/10/20: <simon_bacon@my-deja.com>: Re: Interconnecting LUTs on a Virtex
18341: 99/10/16: Ray Andraka: Re: Interconnecting LUTs on a Virtex
18305: 99/10/13: Brad Smallridge: Part Time, Atmel 6K, Bay Area
18307: 99/10/13: Steven K. Knapp: ANN: The Industry's Largest Independent Information Source of FPGAs and CPLDs (www.optimagic.com)
18308: 99/10/14: Leslie Yip (/ Loui): APEX
18309: 99/10/13: Amir Farrahi: Great Lakes Symposium on VLSI: Submission deadline has been extended till October 22, 1999
18311: 99/10/13: Ray Andraka: Re: Xilinx FPGA Programmer
18312: 99/10/13: Sharad Kumar: Xilinx FPGA Programmer
18328: 99/10/15: Ulf Samuelsson: Re: Xilinx FPGA Programmer
18437: 99/10/24: peter dudley: Re: Xilinx FPGA Programmer
18313: 99/10/14: X: Reading a Lattice ispLSI 1016
18325: 99/10/14: Mikeandmax: Re: Reading a Lattice ispLSI 1016
18314: 99/10/14: Victor Levandovsky: Need info about a FAST adders. How built it? (0)
18321: 99/10/14: Ray Andraka: Re: Need info about a FAST adders. How built it? (0)
18315: 99/10/14: abdulqadir alaqeeli: Virtex Board
18316: 99/10/14: Harald Simmler: Re: Virtex Board
18320: 99/10/14: Ray Andraka: Re: Virtex Board
18323: 99/10/14: smart: Re: Virtex Board
18352: 99/10/18: <gregorstellpflug@my-deja.com>: Re: Virtex Board
18711: 99/11/09: Graham Millar: Re: Virtex Board
18716: 99/11/09: Steven K. Knapp: Re: Virtex Board
18317: 99/10/14: Ben: compiling vhdl code(help please)
18326: 99/10/15: Kai Troester: Re: compiling vhdl code(help please)
18327: 99/10/15: Matthieu LIGER: Re: compiling vhdl code(help please)
18318: 99/10/14: Also-Antal Csaba: test
18319: 99/10/14: Mahboob Ahmed: Virtex FPGA PCI select I/O Characteristics.
18322: 99/10/14: <thomas.hedler@fen.baynet.de>: Estimating Gates in FPGA
18496: 99/10/27: Wendy Lockhart: Re: Estimating Gates in FPGA
18324: 99/10/14: Don Husby: Need a Lucent chip in T100 package.
18329: 99/10/15: Ulf Samuelsson: SRAM FPGA with hardwired 40 MHz AVR RISC processor, memory and peripherals
18344: 99/10/16: <avms@my-deja.com>: Re: SRAM FPGA with hardwired 40 MHz AVR RISC processor, memory and peripherals
18346: 99/10/17: Ulf Samuelsson: Re: SRAM FPGA with hardwired 40 MHz AVR RISC processor, memory and peripherals
18767: 99/11/13: Richard Erlacher: Re: SRAM FPGA with hardwired 40 MHz AVR RISC processor, memory and peripherals
18347: 99/10/17: <simon_bacon@my-deja.com>: Re: SRAM FPGA with hardwired 40 MHz AVR RISC processor, memory and peripherals
18355: 99/10/18: David Brown: Re: SRAM FPGA with hardwired 40 MHz AVR RISC processor, memory and peripherals
18330: 99/10/15: <rajesh52@hotmail.com>: Verilog FAQ
18331: 99/10/15: Kenneth Prager: Xilinx PCI Bridge
18349: 99/10/17: Gary Helbig (.): Re: Xilinx PCI Bridge
18332: 99/10/16: <simon_bacon@my-deja.com>: Xilinx MAKE file
18334: 99/10/16: Alessandro Pinto: VITERBI
18335: 99/10/16: Magnus Homann: Re: VITERBI
18337: 99/10/16: Alessandro Pinto: Re: VITERBI
18339: 99/10/16: Hal Murray: Re: VITERBI
18342: 99/10/16: Ray Andraka: Re: VITERBI
18343: 99/10/16: Ray Andraka: Re: VITERBI
18336: 99/10/16: madQ: Download Ia.n.i.!!! It's free!
18338: 99/10/16: kalle Henriksson: Xilinx 4k and DPRAM for leonardo question
18345: 99/10/16: Magnus Homann: Re: Xilinx 4k and DPRAM for leonardo question
18348: 99/10/17: Alexey Ovchinnikov: Q
18351: 99/10/18: Mark Harvey: R: Reading a Lattice ispLSI 1016
18353: 99/10/18: <knowak@natlab.research.philips.com>: PREP benchmarks
18358: 99/10/18: Brad Ree: Re: PREP benchmarks
18498: 99/10/27: Wendy Lockhart: Re: PREP benchmarks
18592: 99/11/02: Brian Dipert: Re: PREP benchmarks
18354: 99/10/18: madQ: Download Ia.n.i.!!! It's free!
18356: 99/10/18: Jamil Khaib: free Online ASIC course
18383: 99/10/21: Hagen Ploog: Re: free Online ASIC course
18357: 99/10/18: Nicolas Matringe: Best FPGA for PCI ?
18381: 99/10/21: <smcc_adps@my-deja.com>: Re: Best FPGA for PCI ?
18394: 99/10/22: Anthony Ellis - LogicWorks: Re: Best FPGA for PCI ?
18359: 99/10/19: Hul Tytus: listing of discretes and list of wafer fabs in US
18360: 99/10/19: bruno: ANNOUNCE: FPGA Starter kit
18361: 99/10/19: <prastogi@my-deja.com>: Question on Jbits(Xilinx product) for Xc4000 series
18362: 99/10/19: Ray Andraka: Re: Question on Jbits(Xilinx product) for Xc4000 series
18363: 99/10/19: Gordon Hollingworth: Virtex Readback
18400: 99/10/22: Prasanna Sundararajan: Re: Virtex Readback
18404: 99/10/22: Prasanna Sundararajan: Re: Virtex Readback
18364: 99/10/19: Greg Vanslyke: New to FPGA
18365: 99/10/19: Steven K. Knapp: Re: New to FPGA
18366: 99/10/19: Dave Vanden Bout: Re: New to FPGA
18367: 99/10/20: John Larkin: Re: New to FPGA
18387: 99/10/21: G.S. Vigneault: Re: New to FPGA
18375: 99/10/20: Nikhil Krishna: Re: New to FPGA
18368: 99/10/20: G. Brandenburg: load VIRTEX via JTAG
18370: 99/10/20: Marek Ponca: Seeking for FPGA/CPLD (Starter) kit
18373: 99/10/20: Steven K. Knapp: Re: Seeking for FPGA/CPLD (Starter) kit
18374: 99/10/20: Steven K. Knapp: Re: Seeking for FPGA/CPLD (Starter) kit
18418: 99/10/23: peter dudley: Re: Seeking for FPGA/CPLD (Starter) kit
18419: 99/10/23: Ray Andraka: Re: Seeking for FPGA/CPLD (Starter) kit
18371: 99/10/20: Ops: Opportunities for HDL specialists NOW
18377: 99/10/20: Lorant: Interleaver
18403: 99/10/22: <pmolson@my-deja.com>: Re: Interleaver
18378: 99/10/21: <brian_m_davis@my-deja.com>: VHDL carry chain RPMs
18395: 99/10/21: Ken McElvain: Re: VHDL carry chain RPMs
18412: 99/10/23: Ray Andraka: Re: VHDL carry chain RPMs
18379: 99/10/21: Victor Levandovsky: Which synthesis tools (Verybest, Viewlogic, Mentor, etc.) more popular? (0)
18380: 99/10/21: Gordon Hollingworth: Virtex Partial Reconfiguration
18382: 99/10/21: jv: Xilinx Orientation Question
18388: 99/10/21: Ray Andraka: Re: Xilinx Orientation Question
18406: 99/10/22: Tom Burgess: Re: Xilinx Orientation Question
18528: 99/10/28: Andy Peters: Re: Xilinx Orientation Question
18391: 99/10/21: sarin mathen: Re: Xilinx Orientation Question
18392: 99/10/21: Ray Andraka: Re: Xilinx Orientation Question
18393: 99/10/22: Allan Herriman: Re: Xilinx Orientation Question
18397: 99/10/22: Tyrone Thompson: Re: Xilinx Orientation Question
18410: 99/10/23: Austin Franklin: Re: Xilinx Orientation Question
18413: 99/10/23: Ray Andraka: Re: Xilinx Orientation Question
18454: 99/10/25: Philip Freidin: Re: Xilinx Orientation Question
18517: 99/10/28: <eml@riverside-machines.com.NOSPAM>: Re: Xilinx Orientation Question
18415: 99/10/23: Philip Freidin: Re: Xilinx Orientation Question
18421: 99/10/23: Allan Herriman: Re: Xilinx Orientation Question
18426: 99/10/23: Hal Murray: Re: Xilinx Orientation Question
18384: 99/10/21: Khaled BENKRID: test`
18385: 99/10/21: Khaled BENKRID: test
18386: 99/10/21: Khaled BENKRID: test
18389: 99/10/21: Andreas Doering: XILINX: XDL - is this a secret?
18407: 99/10/22: Steve Casselman: Re: XILINX: XDL - is this a secret?
18453: 99/10/25: Rick Filipkiewicz: Re: XILINX: XDL - is this a secret?
18468: 99/10/26: Joni Dambre: Re: XILINX: XDL - is this a secret?
18485: 99/10/27: Jonas Thor: Re: XILINX: XDL - is this a secret?
18396: 99/10/22: Matthias Fuchs: xilinx foundation: bit_gen warning becasue of pullUps
18439: 99/10/24: Rickman: Re: xilinx foundation: bit_gen warning becasue of pullUps
18442: 99/10/24: Jan Gray: Re: xilinx foundation: bit_gen warning becasue of pullUps
18447: 99/10/25: Philip Freidin: Re: xilinx foundation: bit_gen warning becasue of pullUps
18398: 99/10/22: Joni Dambre: pin limitation
18399: 99/10/22: Bill Campbell: NT users wanted for £625 + palm pilot
18401: 99/10/22: Alex Manninger: Win NT
18402: 99/10/22: madQ: Download Ia.n.i.!!! It's free!
18405: 99/10/22: <brady00@my-deja.com>: Configuring a CPLD and Virtex, and programming a Flash
18409: 99/10/23: Khaled BENKRID: Foundation 1.5i Map fatal error
18424: 99/10/23: Utku Ozcan: Re: Foundation 1.5i Map fatal error
18427: 99/10/23: Khaled BENKRID: Re: Foundation 1.5i Map fatal error
18445: 99/10/25: Philip Freidin: Re: Foundation 1.5i Map fatal error
18411: 99/10/23: <brian_m_davis@my-deja.com>: Re: VHDL carry chain RPMs
18416: 99/10/23: Jonas Thor: Static power consumption
18420: 99/10/23: Ray Andraka: Re: Static power consumption
18434: 99/10/24: Peter: Re: Static power consumption
18425: 99/10/23: rk: Re: Static power consumption
18417: 99/10/23: peter dudley: floating point synthesis
18423: 99/10/23: Ray Andraka: Re: floating point synthesis
18429: 99/10/23: peter dudley: Re: floating point synthesis
18431: 99/10/23: Ray Andraka: Re: floating point synthesis
18422: 99/10/23: Haneef D. Mohammed: Announcing Free VHDL Simulator for Windows
18428: 99/10/23: G.S. Vigneault: Re: Announcing Free VHDL Simulator for Windows
18430: 99/10/23: Haneef D. Mohammed: Re: Announcing Free VHDL Simulator for Windows
18432: 99/10/24: David F. Skoll: Re: Announcing Free VHDL Simulator for Windows
18433: 99/10/23: Haneef D. Mohammed: Re: Announcing Free VHDL Simulator for Windows
18471: 99/10/26: Matthias Fuchs: Re: Announcing Free VHDL Simulator for Windows
18479: 99/10/26: Uwe Bonnes: Re: Announcing Free VHDL Simulator for Windows
18480: 99/10/26: Haneef D. Mohammed: Re: Announcing Free VHDL Simulator for Windows
18483: 99/10/27: Uwe Bonnes: Re: Announcing Free VHDL Simulator for Windows
18490: 99/10/27: Graham Seaman: Re: Announcing Free VHDL Simulator for Windows
18504: 99/10/28: Larry Doolittle: Re: Announcing Free VHDL Simulator for Windows
18484: 99/10/27: Allan Herriman: Re: Announcing Free VHDL Simulator for Windows
18487: 99/10/27: Haneef D. Mohammed: Re: Announcing Free VHDL Simulator for Windows
18564: 99/10/31: Haneef D. Mohammed: Re: Announcing Free VHDL Simulator for Windows
18571: 99/11/01: Allan Herriman: Re: Announcing Free VHDL Simulator for Windows
18435: 99/10/24: Child K.L. Sun: Delta-Sigma DAC
18461: 99/10/25: peter dudley: Re: Delta-Sigma DAC
18462: 99/10/26: Allan Herriman: Re: Delta-Sigma DAC
18465: 99/10/26: Child K.L. Sun: Re: Delta-Sigma DAC
18469: 99/10/26: Allan Herriman: Re: Delta-Sigma DAC
18436: 99/10/24: Ahren Hartman: FPGA Timing Problem
18448: 99/10/25: Kai Troester: Re: FPGA Timing Problem
18455: 99/10/25: Rick Filipkiewicz: Re: FPGA Timing Problem
18529: 99/10/28: Andy Peters: Re: FPGA Timing Problem
18536: 99/10/29: Peter (Peter): Re: FPGA Timing Problem
18438: 99/10/24: <tzcpes@thehaunting.com>: FAncY BlOwJoB
18440: 99/10/24: <nhddlo@thehaunting.com>: I Like The Way I DO
18441: 99/10/24: <cycfkh@theblairwitch.com>: Womens Wrestling!!!!!!!!!!!
18443: 99/10/24: Bill Bishop: Questions About the Altera PCIT1 Core
18444: 99/10/25: pengyun: Synplify / LPM?
18446: 99/10/25: Austin Franklin: Re: Synplify / LPM?
18449: 99/10/25: <qqulbu@aerosmith.net>: WALK THIS WAY TALK THIS WAY
18450: 99/10/25: Gerd Rausch: interface effort
18451: 99/10/25: Utku Ozcan: unknown in real life
18452: 99/10/25: Pat Hennessy: Altera newbie simulation problem
18456: 99/10/25: Alain Cloet: Basut-error in Foundation F1.5 / JTAG Programmer M.1.5.25
18457: 99/10/25: Khaled BENKRID: Problem solved?
18458: 99/10/25: Utku Ozcan: Re: Problem solved?
18459: 99/10/25: Utku Ozcan: Re: Problem solved?
18460: 99/10/25: Dave Vanden Bout: Xilinx WebPACK tutorial
18463: 99/10/26: Austin Franklin: Xilinx BGA pinout issue.....
18475: 99/10/26: Peter Alfke: Re: Xilinx BGA pinout issue.....
18481: 99/10/27: Austin Franklin: Re: Xilinx BGA pinout issue.....
18464: 99/10/26: Child K.L. Sun: Comparison between Altera and Xilinx
18513: 99/10/28: Ray Andraka: Re: Comparison between Altera and Xilinx
18522: 99/10/28: Philip Freidin: Re: Comparison between Altera and Xilinx
18526: 99/10/28: Ray Andraka: Re: Comparison between Altera and Xilinx
18550: 99/10/30: Child K.L. Sun: Re: Comparison between Altera and Xilinx
18551: 99/10/30: Ray Andraka: Re: Comparison between Altera and Xilinx
18556: 99/10/31: Hal Murray: Re: Comparison between Altera and Xilinx
18577: 99/11/01: katem: Re: Comparison between Altera and Xilinx
18583: 99/11/01: Ray Andraka: Re: Comparison between Altera and Xilinx
18587: 99/11/02: Hal Murray: Re: Comparison between Altera and Xilinx
18553: 99/10/30: <martin@the-thompsons.freeserve.co.uk>: Re: Comparison between Altera and Xilinx
18554: 99/10/30: Ray Andraka: Re: Comparison between Altera and Xilinx
18558: 99/10/31: <martin@the-thompsons.freeserve.co.uk>: Re: Comparison between Altera and Xilinx
18559: 99/10/31: <eml@riverside-machines.com.NOSPAM>: Re: Comparison between Altera and Xilinx
18579: 99/11/01: <martin@the-thompsons.freeserve.co.uk>: Re: Comparison between Altera and Xilinx
18561: 99/10/31: Ray Andraka: Re: Comparison between Altera and Xilinx
18580: 99/11/01: <martin@the-thompsons.freeserve.co.uk>: Re: Comparison between Altera and Xilinx
18563: 99/11/01: Hal Murray: Re: Comparison between Altera and Xilinx
18578: 99/11/01: <martin@the-thompsons.freeserve.co.uk>: Re: Comparison between Altera and Xilinx
18675: 99/11/07: <kayrock@my-deja.com>: Re: Comparison between Altera and Xilinx
18566: 99/11/01: Gary Cook: Altera Reset Strategy?
18581: 99/11/01: <martin@the-thompsons.freeserve.co.uk>: Re: Altera Reset Strategy?
18588: 99/11/02: Gary Cook: Re: Altera Reset Strategy?
18596: 99/11/02: bob elkind: Re: Altera Reset Strategy?
18466: 99/10/26: <qvhqlm@aerosmith.net>: WICKED WILD WILD WEST 8795
18467: 99/10/26: <holosapien@my-deja.com>: FPGA Starter Kit
18470: 99/10/26: Oh Sheau Pyng: Pc system requirment for Foundation Series
18488: 99/10/27: Eion Magen: Re: Pc system requirment for Foundation Series
18472: 99/10/26: Rafael Gadea Girones: BlockRAM of VIRTEX
18473: 99/10/26: Daryl Bradley: generating power on initialisation
18474: 99/10/26: Nicolas Matringe: Re: generating power on initialisation
18530: 99/10/28: Andy Peters: Re: generating power on initialisation
18476: 99/10/26: <fidonews2@my-deja.com>: FS: New Altera Max+Plus II $1000
18477: 99/10/26: <ada_sri@my-deja.com>: Looking for ASIC designers
18478: 99/10/26: <uynfdq@thecardigans.net>: I Am LOSING MY FAVORITE GAME
18482: 99/10/27: Alexander Krebs: Xilinx F1.5 VHDL Sim. Libs for Synopsys
18518: 99/10/28: Joerg RiTTer: Re: Xilinx F1.5 VHDL Sim. Libs for Synopsys
18535: 99/10/29: Alexander Krebs: Re: Xilinx F1.5 VHDL Sim. Libs for Synopsys
18541: 99/10/29: Brian Philofsky: Re: Xilinx F1.5 VHDL Sim. Libs for Synopsys
18486: 99/10/27: Juergen Buehler: Altera UNIX licence
18494: 99/10/27: Mike Treseler: Re: Altera UNIX licence
18495: 99/10/27: <ar679deja@my-deja.com>: Re: Altera UNIX licence
18489: 99/10/27: Ilia Oussorov: Timing & bidirectional buses
18505: 99/10/28: Davor Lukacic: Re: Timing & bidirectional buses
18491: 99/10/27: Andreas Kröpfl: FPGA
18492: 99/10/27: Steven K. Knapp: Re: FPGA
18514: 99/10/28: Ray Andraka: Re: FPGA
18524: 99/10/28: rk: Re: FPGA
18527: 99/10/28: Ray Andraka: Re: FPGA
18493: 99/10/27: Marcelo Moisan: XACT
18499: 99/10/27: rk: schematics ==> www
18500: 99/10/27: Mike Treseler: Re: schematics ==> www
18502: 99/10/27: Austin Franklin: Re: schematics ==> www
18503: 99/10/27: Rickman: Re: schematics ==> www
18511: 99/10/28: Austin Franklin: Re: schematics ==> www
18515: 99/10/28: Ray Andraka: Re: schematics ==> www
18532: 99/10/28: peter dudley: Re: schematics ==> www
18533: 99/10/28: Ray Andraka: Re: schematics ==> www
18516: 99/10/28: Ray Andraka: Re: schematics ==> www
18521: 99/10/28: Richard Erlacher: Re: schematics ==> www
18608: 99/11/03: Leon Heller: Re: schematics ==> www
18602: 99/11/02: Barry A. Brown: Re: schematics ==> www
18501: 99/10/27: Haneef D. Mohammed: Looking for exemplar_1164 package
18507: 99/10/28: Haneef D. Mohammed: Re: Looking for exemplar_1164 package
18508: 99/10/28: Brian Boorman: Re: Looking for exemplar_1164 package
18510: 99/10/28: Davor Lukacic: Re: Looking for exemplar_1164 package
18506: 99/10/28: Rick Filipkiewicz: Hold times for Xilinx FPGAs
18509: 99/10/28: Rickman: Re: Hold times for Xilinx FPGAs
18520: 99/10/28: Rick Filipkiewicz: Re: Hold times for Xilinx FPGAs
18534: 99/10/28: Rickman: Re: Hold times for Xilinx FPGAs
18531: 99/10/28: peter dudley: Re: Hold times for Xilinx FPGAs
18543: 99/10/29: Hernan Saab: Re: Hold times for Xilinx FPGAs
18512: 99/10/28: <omid@rocketmail.com>: Duty-cycle change in Virtex
18525: 99/10/28: Guy Eschemann: Re: Duty-cycle change in Virtex
18519: 99/10/28: Victor Levandovsky: Need shematic and documentation for in-system programming ALTERA devices with MCU (0)
18595: 99/11/02: bob elkind: Re: Need shematic and documentation for in-system programming ALTERA
18523: 99/10/28: <guy@mail.com>: You must read this! It's your chance.
18537: 99/10/29: project: DSP board for FPGA (I need general info)
18538: 99/10/29: <dulik@my-deja.com>: Altera - how to make probe to a routed chip ?
18540: 99/10/29: Nicolas Matringe: Re: Altera - how to make probe to a routed chip ?
18597: 99/11/02: bob elkind: Re: Altera - how to make probe to a routed chip ?
18539: 99/10/29: Klaus Falser: Problems with Xilinx CPLD's
18542: 99/10/29: Damjan Lampret: opencores.org announcement
18544: 99/10/29: Andy Peters: Xilinx TPSYNC constraint
18560: 99/10/31: Phil Hays: Re: Xilinx TPSYNC constraint
18572: 99/11/01: Andy Peters: Re: Xilinx TPSYNC constraint
18575: 99/11/01: Andy Peters: Re: Xilinx TPSYNC constraint
18562: 99/10/31: Rickman: Re: Xilinx TPSYNC constraint
18574: 99/11/01: Andy Peters: Re: Xilinx TPSYNC constraint
18570: 99/11/01: Andrey Ushenin: Re: Xilinx TPSYNC constraint
18545: 99/10/29: Arrigo Benedetti: need reference to first paper on FPGA
18552: 99/10/30: Tom Kean: Re: need reference to first paper on FPGA
18546: 99/10/29: James Yeh: StateCAD versus Viewdraw
18547: 99/10/29: Ray Andraka: Re: StateCAD versus Viewdraw
18548: 99/10/30: Austin Franklin: Re: StateCAD versus Viewdraw
18549: 99/10/30: James Yeh: Re: StateCAD versus Viewdraw
18576: 99/11/01: Mike Treseler: Re: StateCAD versus Viewdraw
18593: 99/11/02: Holger Venus: Re: StateCAD versus Viewdraw
18606: 99/11/02: Rickman: Re: StateCAD versus Viewdraw
18607: 99/11/03: Bob Perlman: Re: StateCAD versus Viewdraw
18555: 99/10/30: muzo: which Xilinx package for Virtex ?
18557: 99/10/31: G.S. Vigneault: VPR for FPGAs
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