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Xilinx data sheets refer to chip edges as top, bottom, left, and right, and to directions on the chip as horizontal ( 3-state Longlines ) and vertical ( carry ). This nomenclature is unambiguous with respect to the die, but it can be confusing for the user of these square packages. Where is up, and where is left and right? Here are some clues: Without exception, all Xilinx FPGA drawings in the data sheets agree with the orientation of the XACT and EPIC screens. Die orientation is depicted in one consistent way. No problem here. The user is, of course, more interested in the physical orientation of the die within the package. The dedicated pins can help identify the die orientation for ALL Xilinx FPGAs: TDI/TCK is always close to the upper left corner of the die TDO/TMS and CCLK are always close to the upper right corner of the die Mode pins are always close to the lower left corner of the die Done & PROG are always close to the lower right corner of the die Other hints: BG256, FG256 and FG456 are cavity-up packages, and their pin A1 connects to the upper left corner of the die. "Cavity-up" is the traditional, decades-old way of packaging ICs. If you could see through the marked side of the plastic, ceramic or metal, you would see the die as depicted in the data book and the EPIC screen. BG352, BG432, BG560 are cavity-down (thermally enhanced) packages, and their pin A1 connects to the upper right corner of the die. To see the die as depicted in the data book and the EPIC screen, you would have to look at it from the pc-board side, the bottom of the package. The back side of the die is attached to the inside top of the package, for lower thermal resistance and more effective external heatsinks. The die is the same, it is just mounted differently. Flipping the die obviously changes the relationship between top, left, and right. I will write an app note and an XCell article with pictures and additional details. Seems to be necessary. Sorry for the confusion. Peter Alfke, Xilinx ApplicationArticle: 18476
Hi, I'm selling a full Altera MAX+Plus II package, V9.01. It's new and still sealed (I never used it). This package is their "Magnum" product which supports full VHDL. Great for DSP design. Includes manual, CD-ROM and dongle. I can transfer registration to you upon purchase. Originally $7000, will sacrifice for $1000 including shipping. - Chris fidonews2@my-deja.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 18477
Hi All,
An Indian subsidiary(Hyderabad) of Santa Clara based Start-up is
looking for ASIC designers with knowledge in Verilog. The requirement
is immediate and we are looking for 1 - 6 years experienced people.
The company PortalPlayer Inc provides hardware and software
solutions for secure distribution of music over the Net. The company is
a memeber of Secure Digital Music Initiative(SDMI).
Every employee will entitled to get US Stock options. Interested
people can contact me at ' srinivas@w3.to ' for more information.
Take care,
Srinivas
Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 18478Ta Tan an High Speed http://huizen.dds.nl/~eik21 Route 666Article: 18479
In comp.arch.fpga Matthias Fuchs <matthias.fuchs@esd.h.uunet.de> wrote:
: "Haneef D. Mohammed" wrote:
:>
:> > Are you planning on a Linux release? How about source code -- that would
:> > really be no-strings-attached. :-)
:>
:> Linux release? Maybe, maybe soon (no promises).
:> Source-code? Maybe not :-)
: Linux would be very good ! My main OS is linux. If I have to do some
: fpga designing, I have to switch to bill's toys. So I am glad about any
: linux EDA tool that will be available.
Hallo,
as VHDLSimili is a Win32 console application, chances are good to get
it running with Wine (http://www.winehq.com). Appended output is with
my private wine source tree ( current CVS plus some own changes), but
according to the messages wine emits, I guess a plain current wine
should work. It requires an installed and successfull configured Wine
installation
1. Install it:
gauss:~/tmp/cae> wine -desktop 800x600 VHDLSimili.exe"
brings up some welcome screen with a choice to install or abort or....
Clicking install triggers some action which result with a messagebox
> Setup initialization error ... Error 111"
in the wine desktop and
> fixme:win32:PE_LoadImage FATAL: Need to relocate
> D:\WINDOWS\TEMP\_INS5176._MP, but no relocation records present
> (stripped during link). Try to run that file directly !
Don't panic now, read the error message (*1). But watch the first
desktop. It has a timeout and when the timeout triggers, the files in
the TEMP Directory are purged too. In that case start again and type
quicker.
So in another xterm I start
gauss:/dosd/windows/temp> wine -desktop 800x600 _INS5176._MP
(The name may vary for your setup)
Click through all question and choose an installation directory. When
the real files get installed, wine will emit a lot of messages. Ignore
them for now. If you have a win95 installation on your system, you
might run with
gauss:/dosd/windows/temp> wine -desktop 800x600 -dll shell,shell32,commctrl,comctl32,advapi32=n _INS5176._MP
and you will get less errors.
Now you may run the examples:
gauss:/dosd/cae/simili/Examples/Tlc> wine "../../Bin/VhdlP.exe Tlc.vhd Tlc_tb.vhd"
Symphony EDA (R) VHDL Compiler/Simulator Module VhdlP, Version 1.4, Build#10.
Copyright(C) Symphony EDA 1997-1999. All rights reserved.
Reading d:\cae\simili\bin\symphony.ini ...
Library 'ieee' ==> $SYMPHONY/Lib/Ieee/Ieee.sym
Library 'work' ==> work.sym
err:win32:DeleteCriticalSection Deleting owned critical section (0x40dd1e94)
Reading $SYMPHONY\Lib\Ieee\Ieee.sym\std_logic_1164\std_logic_1164.var
Parsing Entity:tlc @ line Tlc.vhd:30
Writing work.sym\tlc\tlc.var
err:win32:DeleteCriticalSection Deleting owned critical section (0x40df2934)
Parsing Architecture:tlc(arch) @ line Tlc.vhd:42
Writing work.sym\tlc\tlc(arch).var
err:win32:DeleteCriticalSection Deleting owned critical section (0x40df4f94)
err:win32:DeleteCriticalSection Deleting owned critical section (0x40de66b4)
Reading $SYMPHONY\Lib\Ieee\Ieee.sym\std_logic_textio\std_logic_textio.var
Parsing Entity:tlc_tb @ line Tlc_tb.vhd:34
Writing work.sym\tlc_tb\tlc_tb.var
err:win32:DeleteCriticalSection Deleting owned critical section (0x40dfa4a4)
Parsing Architecture:tlc_tb(arch) @ line Tlc_tb.vhd:38
Writing work.sym\tlc_tb\tlc_tb(arch).var
err:win32:DeleteCriticalSection Deleting owned critical section (0x40e02ea4)
err:win32:DeleteCriticalSection Deleting owned critical section (0x40df4d84)
Elapsed Time 00h:00m:00s:525ms
err:win32:DeleteCriticalSection Deleting owned critical section (0x40dd0314)
err:win32:DeleteCriticalSection Deleting owned critical section (0x40dd0374)
err:win32:DeleteCriticalSection Deleting owned critical section (0x40dd03d4)
This time I guess that the "err:" Message are not the fault of Wine,
but perhaps the result of sloppy coding of the executable. Perhaps the
author might have a look.
gauss:/dosd/cae/simili/Examples/Tlc> wine "../../Bin/VhdlE.exe -p tlc_tb"
Copyright(C) Symphony EDA 1997-1999. All rights reserved.
Reading d:\cae\simili\bin\symphony.ini ...
Library 'ieee' ==> $SYMPHONY/Lib/Ieee/Ieee.sym
Library 'work' ==> work.sym
err:win32:DeleteCriticalSection Deleting owned critical section (0x40dd1e94)
Reading work.sym\tlc_tb\tlc_tb.var
Reading $SYMPHONY\Lib\Ieee\Ieee.sym\std_logic_textio\std_logic_textio(body).var
Reading $SYMPHONY\Lib\Ieee\Ieee.sym\std_logic_1164\std_logic_1164(body).var
Reading work.sym\tlc_tb\tlc_tb(arch).var
Reading work.sym\tlc\tlc.var
Reading work.sym\tlc\tlc(arch).var
# of Signals = 18
# of Components = 1
# of Processes = 4
# of Drivers = 8
Design Load/Elaboration Elapsed Time: 00h:00m:01s:125ms
50 ns Cycle = 1 Car = 0 NSLights = 01 EWLights = 00
100 ns Cycle = 2 Car = 1 NSLights = 01 EWLights = 00
150 ns Cycle = 3 Car = 1 NSLights = 01 EWLights = 00
200 ns Cycle = 4 Car = 1 NSLights = 01 EWLights = 00
250 ns Cycle = 5 Car = 1 NSLights = 01 EWLights = 00
300 ns Cycle = 6 Car = 1 NSLights = 10 EWLights = 00
350 ns Cycle = 7 Car = 1 NSLights = 00 EWLights = 01
400 ns Cycle = 8 Car = 1 NSLights = 00 EWLights = 01
450 ns Cycle = 9 Car = 1 NSLights = 00 EWLights = 10
500 ns Cycle = 10 Car = 1 NSLights = 01 EWLights = 00
550 ns Cycle = 11 Car = 0 NSLights = 01 EWLights = 00
600 ns Cycle = 12 Car = 0 NSLights = 01 EWLights = 00
650 ns Cycle = 13 Car = 0 NSLights = 01 EWLights = 00
700 ns Cycle = 14 Car = 0 NSLights = 01 EWLights = 00
750 ns Cycle = 15 Car = 0 NSLights = 01 EWLights = 00
800 ns Cycle = 16 Car = 0 NSLights = 01 EWLights = 00
850 ns Cycle = 17 Car = 0 NSLights = 01 EWLights = 00
900 ns Cycle = 18 Car = 0 NSLights = 01 EWLights = 00
Simulation stopped at: 925 ns
Simulation Elapsed Time: 00h:00m:00s:000ms
err:win32:DeleteCriticalSection Deleting owned critical section (0x40dd0324)
err:win32:DeleteCriticalSection Deleting owned critical section (0x40dd0384)
err:win32:DeleteCriticalSection Deleting owned critical section (0x40dd03e4)
*1: At present wine can't use seperate adress spaces for different
processes. Executable are generated with relocation information, but
the default compiler setting is to strip those information...
(Sorry for the rather long posting)
Bye
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de
Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Article: 18480Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message news:7v57ke$j9p$1@sun27.hrz.tu-darmstadt.de... > In comp.arch.fpga Matthias Fuchs <matthias.fuchs@esd.h.uunet.de> wrote: > : "Haneef D. Mohammed" wrote: > err:win32:DeleteCriticalSection Deleting owned critical section (0x40dd0324) > err:win32:DeleteCriticalSection Deleting owned critical section (0x40dd0384) The VHDL Simili executables are multi-threaded and has numerous critical sections (mostly in libc, libc++). Does wine support multi-threading?Article: 18481
Thanks Peter. This little 'inconsistency' took me by surprise, and I luckily caught it. One problem I did see, is the Floor Planner appears to 'suggest' a direction of flow...bring it up, and turn on the internal 'stuff', and you will see what I mean. Regards, Austin Peter Alfke <peter@xilinx.com> wrote in article <3815ED59.E91CDB26@xilinx.com>... > Xilinx data sheets refer to chip edges as top, bottom, left, and right, and to > directions on the chip as horizontal ( 3-state Longlines ) and vertical ( > carry ). > This nomenclature is unambiguous with respect to the die, but it can be > confusing for the user of these square packages. Where is up, and where is > left and right? > > Here are some clues: > > Without exception, all Xilinx FPGA drawings in the data sheets agree with the > orientation of the XACT and EPIC screens. Die orientation is depicted in one > consistent way. No problem here. > > The user is, of course, more interested in the physical orientation of the die > within the package. The dedicated pins can help identify the die orientation > for ALL Xilinx FPGAs: > > TDI/TCK is always close to the upper left corner of the die > TDO/TMS and CCLK are always close to the upper right corner of the die > Mode pins are always close to the lower left corner of the die > Done & PROG are always close to the lower right corner of the die > > Other hints: > > BG256, FG256 and FG456 are cavity-up packages, and their pin A1 connects to > the upper left corner of the die. "Cavity-up" is the traditional, decades-old > way of packaging ICs. If you could see through the marked side of the plastic, > ceramic or metal, you would see the die as depicted in the data book and the > EPIC screen. > > BG352, BG432, BG560 are cavity-down (thermally enhanced) packages, and their > pin A1 connects to the upper right corner of the die. > To see the die as depicted in the data book and the EPIC screen, you would > have to look at it from the pc-board side, the bottom of the package. The back > side of the die is attached to the inside top of the package, for lower > thermal resistance and more effective external heatsinks. The die is the same, > it is just mounted differently. Flipping the die obviously changes the > relationship between top, left, and right. > > I will write an app note and an XCell article with pictures and additional > details. Seems to be necessary. Sorry for the confusion. > > Peter Alfke, Xilinx Application > > > > >Article: 18482
Hi, Does anybody know why Xilinx switched to not generating the object code for fast VSS simulation for all the simulation libraries? Until version 1.4 the call of the VHDL compiler in their analyze.csh files looked like vhdlan -c -optimize -w ... Starting with version 1.5 it is vhdlan -i -w ... I changed their scripts back to the "-c" version because it should give us much shorter simulation times. It seems to work. Are there any drawbacks? Thanx for your help in advance! Alex. -- _______________ | | |_|_|_|_| ALEXANDER KREBS |___|___|_|_|_|_| | | |_|_|_|_| Fraunhofer-Institut Integrierte Schaltungen |___|___|_|_|_|_| Aussenstelle EAS Dresden, Abteilung Synthese | _ | Zeunerstrasse 38, 01069 Dresden, Germany | | | (_` | Tel./Fax: +49 (0)351 4640-728/-703 | | | ._) | e-mail : krebs@eas.iis.fhg.de |_______________| www : http://www.eas.iis.fhg.deArticle: 18483
In comp.arch.fpga Haneef D. Mohammed <haneef@mindspring.com> wrote: : Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message : news:7v57ke$j9p$1@sun27.hrz.tu-darmstadt.de... :> In comp.arch.fpga Matthias Fuchs <matthias.fuchs@esd.h.uunet.de> wrote: :> : "Haneef D. Mohammed" wrote: :> err:win32:DeleteCriticalSection Deleting owned critical section : (0x40dd0324) :> err:win32:DeleteCriticalSection Deleting owned critical section : (0x40dd0384) : The VHDL Simili executables are multi-threaded and has numerous : critical sections (mostly in libc, libc++). Does wine support : multi-threading? Yes, wine does. And as I run the test on a Dual Celeron with SMP Linux, these threads ran on differing CPU's. Here is a log of the API calls around the first such message. If you find places where you doubt that wine is right, it will be helpfull to hear from you. wine -debugmsg +relay,+snoop "../../Bin/VhdlP.exe Tlc.vhd Tlc_tb.vhd">& /tmp/wine.debug 4136 Call KERNEL32.195: EnterCriticalSection(40e31aa4) ret=004a626f fs=0237 4137 Ret KERNEL32.195: EnterCriticalSection() retval=0847ec50 ret=004a626f fs=0237 4138 Call KERNEL32.195: EnterCriticalSection(40e31aa4) ret=004a626f fs=0237 4139 Ret KERNEL32.195: EnterCriticalSection() retval=0847ec50 ret=004a626f fs=0237 4140 Call KERNEL32.195: EnterCriticalSection(40d24430) ret=004b0da6 fs=0237 4141 Ret KERNEL32.195: EnterCriticalSection() retval=0847ec50 ret=004b0da6 fs=0237 4142 Call KERNEL32.137: CloseHandle(00000029) ret=004a9ec8 fs=0237 4143 Ret KERNEL32.137: CloseHandle() retval=00000001 ret=004a9ec8 fs=0237 4144 Call KERNEL32.494: LeaveCriticalSection(40d24430) ret=004b0dcb fs=0237 4145 Ret KERNEL32.494: LeaveCriticalSection() retval=ffffffff ret=004b0dcb fs=0237 4146 Call KERNEL32.494: LeaveCriticalSection(40e31aa4) ret=004a627a fs=0237 4147 Ret KERNEL32.494: LeaveCriticalSection() retval=00000000 ret=004a627a fs=0237 4148 Call KERNEL32.185: DeleteCriticalSection(40e31aa4) ret=004a6264 fs=0237 4149 err:win32:DeleteCriticalSection Deleting owned critical section (0x40e31aa4) 4150 Ret KERNEL32.185: DeleteCriticalSection() retval=00000001 ret=004a6264 fs=0237 -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 18484
On Sat, 23 Oct 1999 10:19:41 -0700, "Haneef D. Mohammed" <haneef@mindspring.com> wrote: >We are pleased to annouce the Beta release of "VHDL Simili" > > -- VERY FAST Compiler and Simulator > -- VHDL 93 > -- Vital/SDF support > -- Tested with Programmable Logic Vendor Libraries > -- Designed for the serious VHDL professional > -- Optimized for easy internet downloads > -- Much much more ... > >VHDL Simili is FREE with no gimmicks/strings attached and >without any limits on the number/size of your >VHDL files, simulation run time, etc. > >Please visit us at > > http://www.symphonyeda.com > >to find out more and download the software (2.2MB). > >Note that the "VHDL Simili" system currently has a >command line interface only (no waveform viewer) >and it is available only for the Windows (95/98/NT) x86 >platforms. If you are comfortable with test benches or >TextIO, this is the tool for you.... I tried it on an old project (which I had previously compiled with a few different tools), and it gave an internal error on the very first file I tried to compile. >vhdlp ..\src\ex_1164\ex_1164.vhd Symphony EDA (R) VHDL Compiler/Simulator Module VhdlP, Version 1.4, Build#10. Copyright(C) Symphony EDA 1997-1999. All rights reserved. Reading C:\Program Files\Symphony EDA\VHDL Simili\bin\symphony.ini ... Library 'ieee' ==> $SYMPHONY/Lib/Ieee/Ieee.sym Library 'work' ==> work.sym Reading $SYMPHONY\Lib\Ieee\Ieee.sym\std_logic_1164\std_logic_1164.var Parsing Package:exemplar_1164 @ line ..\src\ex_1164\ex_1164.vhd:31 Writing work.sym\exemplar_1164\exemplar_1164.var Parsing Package Body:exemplar_1164 @ line .\src\ex_1164\ex_1164.vhd:297 Internal Error: D:\home\proj\SimVHDL\VhdlExpr\CSTypeConversion.cpp: (line 79): E xpecting Aggregate here And the source around line 297 was: 290: signal q : out std_ulogic_vector); 291: 292:end exemplar_1164; 293: 294:library ieee ; 295:use ieee.std_logic_1164.all ; 296: 297:package body exemplar_1164 is 298: 299: --- Any idea what is wrong? Regards, Allan.Article: 18485
Hello, XDL is actually documented. If you installed the userware with Foundation or Alliance you will have some docs in: /userware/doc / Jonas ThorArticle: 18486
In our company we are using ALTERAs MAXPLUS II software (actual version 9.31) based on PC. Now we are looking for an UNIX network licence. Has anyone experience with the UNIX version of MAXPLUS II. I would be very delighted for any hint. Regards JürgenArticle: 18487
Sorry to hear this. Would it be possible for you to email me the vhdl file at haneef@symphonyeda.com. The internal error occured some where deep inside the body of the package. We should be able to pin-point and fix the problem quickly if we can have access to the file. The line 297 message was actually the last status message printed by the compiler (a status message is printed for each design unit encountered in the vhdl file). Regards Haneef Allan Herriman <allan.herriman.hates.spam@fujitsu.com.au> wrote in message news:3816b2cb.1582367@newshost.fujitsu.com.au... > Parsing Package Body:exemplar_1164 @ line > .\src\ex_1164\ex_1164.vhd:297 > Internal Error: D:\home\proj\SimVHDL\VhdlExpr\CSTypeConversion.cpp: > (line 79): E > xpecting Aggregate here > > And the source around line 297 was: > > 290: signal q : out std_ulogic_vector); > 291: > 292:end exemplar_1164; > 293: > 294:library ieee ; > 295:use ieee.std_logic_1164.all ; > 296: > 297:package body exemplar_1164 is > 298: > 299: --- > > > Any idea what is wrong? > > Regards, > Allan.Article: 18488
Hello Sheau! A multi-processor pc will not speed up the place and route procedure since the application does not support multi processing stations. Your 256M memory is large enough for 1000 clb design Eilon Magen Marconi communications Oh Sheau Pyng wrote: > hi, > > I have some question regarding the PC system that run the Xilinx > Foundation series. > > Will a multi-processor pc speed up the place and route process or > memory is more important? > Can the Xilinx foundation software benefit from multi-processor > environment? ( o/s most likely will have to be NT) > > from my own observation during PNR ( which take up the most time ), > CPU Utilitization is 100 % and memory usage is < 256 Mbytes. No much > swapping is occuring as the HardDisk LED is not flashing. > > The design is about 1000 CLB , going to about 3000 ~ 3500 when the > design is complete > clock = 40 MHz. > o/s = win 98 > ram = 196 Mbyte > swapdisk = 256 Mbyte > CPU = PII 400 > > Because we are looking into a upgrade of the PC system that run the > Xilinx Foundation s/w. > Ram : 512 Mbyte or 1 GByte of system ram > Processor : PIII 600 , single or multi-processors. > > > Any recommendation?? or where can I find the information ??? > > Thanks alot > > Sheau PyngArticle: 18489
This is a multi-part message in MIME format.
--------------C2AA79883086C2A5CAA81BC9
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Hi friends.
I use Virtex device and software Xilinx aliance2.1i and Leonardo.
I have bidirectional buses in my design (see figure). The control logic
of design never leave both T-buffers open. But if i try to implement the
design, xilinx place and route takes a very
long time. And than it says "timing constraints could not be met". I
think that the tool assume infinite loop in design. If I do 2
unidirectional buses the implementation takes a very short time. Is it
possible to
say to the tool to do not execute loops analyze?
How can I solve this problem?
I don't like to do 2 unidirectional buses from one bi-directional but I
can't wait 2 hours until the design will be implemented.
P.S. The design works after mentioned implementation also in hardware
properly
uc_dc(7 downto 0) <= uc_d(7 downto 0) when re = '1' else (others =>
'Z');
uc_d(7 downto 0) <= uc_dc(7 downto 0) when we = '1' else (others =>
'Z');
/-------<Tbuf------\
/ \
<>-----/------Tbuf>------------\------<>-----
Best regards,
--------------C2AA79883086C2A5CAA81BC9
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tel;work:+49-(0)-711-8117057
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--------------C2AA79883086C2A5CAA81BC9--
Article: 18490Matthias Fuchs (matthias.fuchs@esd.h.uunet.de) wrote: : "Haneef D. Mohammed" wrote: : > : > > Are you planning on a Linux release? How about source code -- that would : > > really be no-strings-attached. :-) : > : > Linux release? Maybe, maybe soon (no promises). : > Source-code? Maybe not :-) : Linux would be very good ! My main OS is linux. If I have to do some : fpga designing, I have to switch to bill's toys. So I am glad about any : linux EDA tool that will be available. : : Matthias If you want a working (but bare - no gui!) VHDL93 simulator for Linux (or any Unix, since its under LGPL and so comes with source) you could try Savant: http://www.ececs.uc.edu/~paw/savant/ There are rpm and deb packages. There's a longer list of open source design tools at http://collector.hscs.wmin.ac.uk Unfortunately, plenty for data entry and simulation, nothing for synthesis (yet...) Graham --Article: 18491
HI This are Andreas Kropfl kroepfl@iti.tu-graz.ac.at and Dieter Leiler leiler@sbox.tu-graz.ac.at. We are diplomand students at the technical university of Graz and search for literature concerning FPGAs Perhaps someone can help us in one of the following points. * MAIN PROBLEM : failure tollerance in reconfigurable FPGAs * introducing material concerning the development of FPGA ( summaries about the work on FPGAs ) * state-of-the-art articles ... a.s.o. It would rather be interesting to get more literature via email (.doc, .ps, ..) , some other email-adresses from people, who are working on the same topic. Finally some homepages for better understanding can be a great help. Thank you for your help ! Greatings from Graz ------------------------------------------------------------------------ ------ Dipl.-Ing. Andreas R. Kroepfl - research assistent Institut f. Technische Informatik - TU Graz Inffeldg. 16/1 8010 Graz Austria Tel.Nr.: +43 +316 873 6411 Fax.Nr.: +43 +316 873 6903 E-Mail: kroepfl@i.am Homepage: http://kroepfl.i.am ------------------------------------------------------------------------ ------ ------------------------------------------------------------------------ ------ Dieter Leiler - diploma student Institut f. Technische Informatik - TU Graz Inffeldg. 16/1 8010 Graz Austria Tel.Nr.: +43 +316 873 6411 Fax.Nr.: +43 +316 873 6903 E-Mail: leiler@iti.tu-graz.ac.at ------------------------------------------------------------------------ ------Article: 18492
One good place to start is The Programmable Logic Jump Station at http://www.optimagic.com. This web site has links to most topics on FPGAs and other forms of programmable logic. You may also be interested in various on-going research. The various research groups that we know about are listed at http://www.optimagic.com/research.html. -- ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- Andreas Kröpfl <kroepfl@iti.tu-graz.ac.at> wrote in message news:7v751a$5tm@fstgal00.tu-graz.ac.at... > HI > > This are Andreas Kropfl kroepfl@iti.tu-graz.ac.at and Dieter Leiler > leiler@sbox.tu-graz.ac.at. We are diplomand students at the technical > university of Graz and search for literature concerning FPGAs > > Perhaps someone can help us in one of the following points. > * MAIN PROBLEM : failure tollerance in reconfigurable FPGAs > * introducing material concerning the development of FPGA ( summaries about > the work on FPGAs ) > * state-of-the-art articles ... a.s.o. > > It would rather be interesting to get more literature via email (.doc, .ps, > ..) , some other email-adresses from people, who are working on the same > topic. Finally some homepages for better understanding can be a great help. > > Thank you for your help ! > Greatings from Graz > > ------------------------------------------------------------------------ > ------ > Dipl.-Ing. Andreas R. Kroepfl - research assistent > Institut f. Technische Informatik - TU Graz > Inffeldg. 16/1 > 8010 Graz > Austria > > Tel.Nr.: +43 +316 873 6411 > Fax.Nr.: +43 +316 873 6903 > E-Mail: kroepfl@i.am > Homepage: http://kroepfl.i.am > ------------------------------------------------------------------------ > ------ > > ------------------------------------------------------------------------ > ------ > Dieter Leiler - diploma student > Institut f. Technische Informatik - TU Graz > Inffeldg. 16/1 > 8010 Graz > Austria > > Tel.Nr.: +43 +316 873 6411 > Fax.Nr.: +43 +316 873 6903 > E-Mail: leiler@iti.tu-graz.ac.at > ------------------------------------------------------------------------ > ------ > >Article: 18493
Somebody can send me a link to obtain a shareware copy of the XACT support of whatever program to download the bitstream of a design onto a Xilinx XC4000 FPGA??? mmoisan@cvmail.clArticle: 18494
Juergen Buehler wrote:
>
> In our company we are using ALTERAs MAXPLUS II software (actual version
> 9.31) based on PC. Now we are looking for an UNIX network licence. Has
> anyone experience with the UNIX version of MAXPLUS II.
> I would be very delighted for any hint.
We have used max2win (GUI) and maxplus2 (command line)
on Solaris for over a year.
Getting the floating license server set up right is
a major pain, but once it is, it works fine.
Much better than borrowing dongles.
The solaris GUI version looks almost exactly the
same as the NT version.
Since there is no Linux version, I have to
xrlogin to a solaris host to run max2win.
Their new "Quartus" version is another matter.
It insists on running as root, which is a major no-no on our network.
We are still trying to come up with a solution to this one.
-Mike Treseler
Article: 18495In article <3816DDEF.2F389C21@thmulti.com>, Juergen Buehler <buehlerj@thmulti.com> wrote: > In our company we are using ALTERAs MAXPLUS II software (actual version > 9.31) based on PC. Now we are looking for an UNIX network licence. Has > anyone experience with the UNIX version of MAXPLUS II. > I would be very delighted for any hint. > I played with MaxPlus2 on various Sun workstations as an attempt to decrease my build times. Even on an Ultra, my fast PC would beat it hands down. Plus there were problems with the user interface. I can't remember the details. When I did my evaluation, we were running version 8.x. I havn't tried the newer software. Altera was good about sending us an 30 day evaluation license for free. If you have specific questions post them. Sent via Deja.com http://www.deja.com/ Before you buy.Article: 18496
This article gives you some guidelines on gate estimates in Xilinx http://www.xilinx.com/xbrf/xbrf011.pdf * Sent from RemarQ http://www.remarq.com The Internet's Discussion Network * The fastest and easiest way to search and participate in Usenet - Free!Article: 18497
If you are looking for a 6200 from Xilinx you are probably interested in reconfigurable FPGAs. Have you looked at the Atmel AT40K and AT6000 FPGA devices as an alternative as Xilinx is phasing out/killing the 6200 as far as I know. These devices are fully/partially reconfigurable on the fly. Let me know if you want more info. Wendy * Sent from RemarQ http://www.remarq.com The Internet's Discussion Network * The fastest and easiest way to search and participate in Usenet - Free!Article: 18498
You may want to have a look at a recent article in EDN by Brian Dipert. This was a "benchmark" of some FPGAs and general discussion on benchmarking. There is an associated website which includes all the example file, which are designed to conitain RAM state machines and FIFO, so a good general purpose design. Brian's benchmark is a little difficult because the vendors got to choose one part for the study. So you have a $1000 dollar Virtex device against a $40 AT40K from Atmel, so the results are not design specific enough to help you. The useful test is to take the FPGAs that would be competing for the same design like XC4000, Spartan At40K and maybe and Altera 10K/*K and benchmark those ones. You may be able to use these designs to generate your own more focussed benchmark. * Sent from RemarQ http://www.remarq.com The Internet's Discussion Network * The fastest and easiest way to search and participate in Usenet - Free!Article: 18499
hi, i wish to publish some schematics for people to view on the www. before i start on this project, i thought i'd solicit some suggestions. currently i have a viewlogic license but haven't had the greatest luck with doing much with that wrt sharing schematics; perhaps i need to fiddle with it more. i also have veribest but haven't really explored that at all so perhaps someone with some experience has some ideas or thoughts. i could do .hgl (hp graphics language) output but not sure how readable that would be. usually when i import an .hgl into word it makes a mess. likewise, printing to .pdf has been far from successful. so, what's a portable way to share schematics here, approaching 2000, in the so-called information age? :-) suggestions? rk
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