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Hi ! At work we have a Xilinx Virtex FPGA and a Texas Instruments TMS320C6202 DSP that are connected to each other. The DSP communicates with the FPGA using the built in EMIF interface in asynchronous mode. The clock frequency of the DSP is 200 MHz. The FPGA has a clock frequency of 30 MHz. In the FPGA we have designed a block that clocks in the data, address and control signals from the DSP with the clock freq. of 60 MHz. ( The signals are down-converted to 30MHz in using a number of registers working with 60 MHz to 'strech out' the control signals and finally these signals are clocked out to the rest of the FPGA using 30MHz registers. Is there a better way to connect an FPGA to a DSP ? Could any of you give me some pointers ? I tried to look for application notes on both Xilinx and TI's web sites but without result. Thanks in advance /L Horvath * Sent from RemarQ http://www.remarq.com The Internet's Discussion Network * The fastest and easiest way to search and participate in Usenet - Free!Article: 18626
Dear friends,
I have got following message. In the first part of the message.
How one can explane the message " Minimum period: 179.454ns
(Maximum frequency: 5.572MHz) " if the constraint 62 ns is met.
Which maximum frequensy does xilinx mean in this line ?
--------------------------------------------------------------------------------
Constraint | Requested | Actual |
Logic
| | |
Levels
--------------------------------------------------------------------------------
NET "ix1677/IBUFG" PERIOD = 62 nS HIGH | 62.000ns | 14.696ns |
4
31 nS | | |
--------------------------------------------------------------------------------
NET "ix1678/IBUFG" PERIOD = 250 nS HIG | 250.000ns | 87.431ns |
33
H 125 nS | | |
--------------------------------------------------------------------------------
NET "clk_1a" PERIOD = 250 nS HIGH 125 | 250.000ns | 179.454ns |
28
nS | | |
--------------------------------------------------------------------------------
All constraints were met.
Timing summary:
---------------
Timing errors: 0 Score: 0
Constraints cover 3279800145 paths, 0 nets, and 12397 connections (96.5%
coverage)
Design statistics:
Minimum period: 179.454ns (Maximum frequency: 5.572MHz)
with best regars,
Ilia Oussorov
* Sent from RemarQ http://www.remarq.com The Internet's Discussion Network *
The fastest and easiest way to search and participate in Usenet - Free!
Article: 18627In article <000b8d9b.56895679@usw-ex0102-016.remarq.com>, Ilia Oussorov <fliser6NOflSPAM@fli.sh.bosch.de.invalid> wrote: > Dear friends, > I have got following message. In the first part of the message. > How one can explane the message " Minimum period: 179.454ns > (Maximum frequency: 5.572MHz) " if the constraint 62 ns is met. > Which maximum frequensy does xilinx mean in this line ? > ------------------------------------------------------------------- > ------------- > Constraint | Requested | Actual > | > Logic > | | > | > Levels > ------------------------------------------------------------------- > ------------- > NET "ix1677/IBUFG" PERIOD = 62 nS HIGH | 62.000ns | > 14.696ns | > 4 > 31 nS | | > | > ------------------------------------------------------------------- > ------------- > NET "ix1678/IBUFG" PERIOD = 250 nS HIG | 250.000ns | > 87.431ns | > 33 > H 125 nS | | > | > ------------------------------------------------------------------- > ------------- > NET "clk_1a" PERIOD = 250 nS HIGH 125 | 250.000ns | > 179.454ns | > 28 > nS | | > | > ------------------------------------------------------------------- > ------------- > All constraints were met. > Timing summary: > --------------- > Timing errors: 0 Score: 0 > Constraints cover 3279800145 paths, 0 nets, and 12397 connections > (96.5% > coverage) > Design statistics: > Minimum period: 179.454ns (Maximum frequency: 5.572MHz) > with best regars, > Ilia Oussorov > * Sent from RemarQ http://www.remarq.com The Internet's Discussion > Network * > The fastest and easiest way to search and participate in Usenet - > Free! 00 * Sent from RemarQ http://www.remarq.com The Internet's Discussion Network * The fastest and easiest way to search and participate in Usenet - Free!Article: 18628
Hi, we would like to simulate an FPGA design after logic synthesis (for Xilinx XC4036) but before doing any place and route. I.e. we want to simulate the delays of the logic, but not of the wires. Is there a way to do this (with design compiler and vss)? I understand that we can write a vhdl netlist from design compiler after synthesis. But this netlist is not simulatable, e.g. it contains iob_4000 components for which we do not have simulation models. Any help on this would be appreciated, Joe -- Josef Fleischmann http://eda.ei.tum.de/~jsf Institute for Electronic Design Automation Technical University of Munich, 80290 Munich, GermanyArticle: 18629
> > we would like to simulate an FPGA design after logic synthesis (for > Xilinx XC4036) but before doing any place and route. I.e. we want to > simulate the delays of the logic, but not of the wires. > > Is there a way to do this (with design compiler and vss)? > > I understand that we can write a vhdl netlist from design compiler after > synthesis. But this netlist is not simulatable, e.g. it contains > iob_4000 components for which we do not have simulation models. Try to disabel the IO insertion at syntheses time. This will prevent IOB usage in the netlist. Unfortunately I am not an expert in synopsys. So I cant tell you what command will disabel the insertion. Harald SimmlerArticle: 18630
gallant@nm.hsd.utc.com wrote: > > Hello, > > I have a general FPGA design question. I have many asynchronous inputs > to my Actel 42MX device. Is the general practice to cascade 2 flip- > flops for each input in order to reduce the probability of > metastability? How can I calculate this probability? > > Where could I find more information about this subject (I searched the > Actel web site but couldn't find anything)? > > Thanks in advance, > > Josh Gallant This is a general rule if the input is being used in multiple destinations or runs through significant logic before being clocked into the next register. The way to resolve metastability is to provide a window of excess setup time. This allows the input FF to bring itself out of metastability before the next clock edge. The more time you allow, the less likely it is to be metastable near the clock edge. So you can save a FF (and a clock cycle of input time) if the signal is only going to a single register AND you allow some extra setup time to the next register. The amount of extra setup time required is dependant on the clock frequency the input signal rate and a constant which characterizes the FFs in your device. If you can't do this with a single input register then you need two with little delay between them. The notes that Peter Alfke mentioned are all very good. You should read them all. -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 18631
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>Current FPGAs are capable of 155Mbit/sec performance if you are careful with the >design. With the information shown here, this should be an easy fit to an >FPGA. Depending on the complexity of the encoder, you may even get away with a >slower speed grade part. > Thanks!! Then, can I use the chip family of XC4000 (or even lower grade) other than Virtex from Xilinx? ChildArticle: 18633
On Wed, 3 Nov 1999 20:16:14 +0100, "giuseppe giachella" <il_templare@hotmail.com> wrote: >I'm trying to synthetize a design on an Altera Flex 10KA250 . I've tried to >use two >different tools > >1)Leonardo Spectrum (on a WinNT4.0 PC Pentium II, 128 MB Ram) >2)Fpga Compiler II Altera Edition (on a Solaris 2.5.1, 512 MB Ram) > >Leonardo crashed after a few hours. Fpga Compiler created an >"implementation" >Any suggestion about possible workarounds ? If Leonardo took a few hours ... check if it was swapping. (Always keep Task Manager open when running synthesis and look at CPU utilisation. If it drops from 100% to 8% you're swapping) Sounds like it to me. If so, add memory. I'd say 256MB is the minimum for a large-ish design, the upgrade will set you back at least $100. Given the price of Leonardo it's kinda silly not to... Also try "preserve hierarchy" instead of "flatten". I've found Leonardo runs MUCH faster on a complex design because each module is relatively simple and the synth can do a better job on it than it can on one humongous module - funnily enough it sometimes produces a smaller and faster result! (of course I've only tried targetting Xilinx) - BrianArticle: 18634
I'm in my first steps with a PCI Pamette boad and when I try to run the
sample executables I get the message :
"PamRT error: configuration error: Init did not go high, LCA 0 1 2 3"
The same happens when I try to download my own design, although I can
read the boards configuration :
PCI Pamette V1R2, Firmware 1.11, Serial Number 19
Configuration: 4044XL 4044XL 4044XL 4044XL
I'm very much afraid that something is wrong with my Pamette card.
Does enyone know what this error message means ??
Stamatis Kavadias
Article: 18635Josef Fleischmann wrote in message <3821850B.B092D2CE@regent.e-technik.tu-muenchen.de>... >Hi, > >we would like to simulate an FPGA design after logic synthesis (for >Xilinx XC4036) but before doing any place and route. I.e. we want to >simulate the delays of the logic, but not of the wires. > >Is there a way to do this (with design compiler and vss)? > >I understand that we can write a vhdl netlist from design compiler after >synthesis. But this netlist is not simulatable, e.g. it contains >iob_4000 components for which we do not have simulation models. I know that FPGA Express can spit out a post-synthesis VHDL model. -- ----------------------------------------- Andy Peters Sr Electrical Engineer National Optical Astronomy Observatories 950 N Cherry Ave Tucson, AZ 85719 apeters (at) noao \dot\ edu "Creation Science" is oxymoronic.Article: 18636
Ilia Oussorov wrote in message <000b8d9b.56895679@usw-ex0102-016.remarq.com>... > >Dear friends, >I have got following message. In the first part of the message. >How one can explane the message " Minimum period: 179.454ns >(Maximum frequency: 5.572MHz) " if the constraint 62 ns is met. >Which maximum frequensy does xilinx mean in this line ? > > > >--------------------------------------------------------------------------- ----- > Constraint | Requested | Actual | >Logic > | | | >Levels >--------------------------------------------------------------------------- ----- > NET "ix1677/IBUFG" PERIOD = 62 nS HIGH | 62.000ns | 14.696ns | >4 > 31 nS | | | >--------------------------------------------------------------------------- ----- > NET "ix1678/IBUFG" PERIOD = 250 nS HIG | 250.000ns | 87.431ns | >33 > H 125 nS | | | >--------------------------------------------------------------------------- ----- > NET "clk_1a" PERIOD = 250 nS HIGH 125 | 250.000ns | 179.454ns | >28 > nS | | | >--------------------------------------------------------------------------- ----- The maximum frequency reported for the design is always the *slowest.* It seems as if you have three period constraints, which might not be what you intended. Recheck your constraints. -- a ----------------------------------------- Andy Peters Sr Electrical Engineer National Optical Astronomy Observatories 950 N Cherry Ave Tucson, AZ 85719 apeters (at) noao \dot\ edu "Creation Science" is oxymoronic.Article: 18637
Where can I find an address with FPGA prices? Or what is aproximately the prize of an FPGA? Thanks * Sent from AltaVista http://www.altavista.com Where you can also find related Web Pages, Images, Audios, Videos, News, and Shopping. Smart is BeautifulArticle: 18638
In article <3820EB95.E91133E2@ids.net>, Ray Andraka <randraka@ids.net> wrote: > Also, you should keep the route between the resynchronizers as short as > possible (measured in time) because the propagation delay eats into your > metastability resolution window. > Right. We create a FROM:TO timing specification for synchronization registers, which is shorter than the clock period specification. We calculate the magnitude of the time spec reduction to provide us with the required margin for acceptable reduced metastability probability. This allows us to use automatic place and route. -- Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 18639
In article <38218CCC.851ED115@yahoo.com>, Rickman <spamgoeshere4@yahoo.com> wrote: <snip> > The way to resolve metastability is to provide a > window of excess setup time. <snip> If you can guarantee setup time, then the input isn't asynchronous, and the flip-flop will not be subject to metastability. Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 18640
This is a multi-part message in MIME format. --------------543AB0208BB11F553216FA5C Content-Type: multipart/alternative; boundary="------------5C2B1F13B008223E2546BBEE" --------------5C2B1F13B008223E2546BBEE Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit If you wish to simulate the design with logic level delays but not wire delays, this is possible if you run the synthesized netlist through the Xilinx M1 tools to the Map stage. Run the ncd file that Map outputs through ngdanno and then run the nga file from ngdanno through ngd2vhdl. The command sequence will look like: ngdbuild <design_netlist> map -o logic_sim.ncd <design>.ngd ngdanno logic_sim.ncd ngd2vhdl logic_sim.nga The output of ngd2vhdl will be a structual VHDL file and an SDF file containing only logic delays. This is described a few places in our documentation. One place that comes to mind is chapter 5 of the Synthesis and Simulation Guide, http://www.xilinx.com/support/sw_manuals/2_1i/download/gensim.pdf Hope this helps. -- Brian Josef Fleischmann wrote: > Hi, > > we would like to simulate an FPGA design after logic synthesis (for > Xilinx XC4036) but before doing any place and route. I.e. we want to > simulate the delays of the logic, but not of the wires. > > Is there a way to do this (with design compiler and vss)? > > I understand that we can write a vhdl netlist from design compiler after > synthesis. But this netlist is not simulatable, e.g. it contains > iob_4000 components for which we do not have simulation models. > > Any help on this would be appreciated, > > Joe > > -- > Josef Fleischmann http://eda.ei.tum.de/~jsf > Institute for Electronic Design Automation > Technical University of Munich, 80290 Munich, Germany -- ------------------------------------------------------------------- / 7\'7 Brian Philofsky (brian.philofsky@xilinx.com) \ \ ` Xilinx Design Engineer hotline@xilinx.com / / 2100 Logic Drive 1-800-255-7778 \_\/.\ San Jose, California 95124-3450 1-408-879-5199 ------------------------------------------------------------------- --------------5C2B1F13B008223E2546BBEE Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> <br> <p>If you wish to simulate the design with logic level delays but not wire delays, this is possible if you run the synthesized netlist through the Xilinx M1 tools to the Map stage. Run the ncd file that Map outputs through ngdanno and then run the nga file from ngdanno through ngd2vhdl. The command sequence will look like: <p>ngdbuild <design_netlist> <br>map -o logic_sim.ncd <design>.ngd <br>ngdanno logic_sim.ncd <br>ngd2vhdl logic_sim.nga <br> <p>The output of ngd2vhdl will be a structual VHDL file and an SDF file containing only logic delays. <p>This is described a few places in our documentation. One place that comes to mind is chapter 5 of the Synthesis and Simulation Guide, <A HREF="http://www.xilinx.com/support/sw_manuals/2_1i/download/gensim.pdf">http://www.xilinx.com/support/sw_manuals/2_1i/download/gensim.pdf</A> <p>Hope this helps. <br> <p>-- Brian <br> <br> <p>Josef Fleischmann wrote: <blockquote TYPE=CITE>Hi, <p>we would like to simulate an FPGA design after logic synthesis (for <br>Xilinx XC4036) but before doing any place and route. I.e. we want to <br>simulate the delays of the logic, but not of the wires. <p>Is there a way to do this (with design compiler and vss)? <p>I understand that we can write a vhdl netlist from design compiler after <br>synthesis. But this netlist is not simulatable, e.g. it contains <br>iob_4000 components for which we do not have simulation models. <p>Any help on this would be appreciated, <p>Joe <p>-- <br>Josef Fleischmann <a href="http://eda.ei.tum.de/~jsf">http://eda.ei.tum.de/~jsf</a> <br>Institute for Electronic Design Automation <br>Technical University of Munich, 80290 Munich, Germany</blockquote> <pre>-- ------------------------------------------------------------------- / 7\'7 Brian Philofsky (brian.philofsky@xilinx.com) \ \ ` Xilinx Design Engineer hotline@xilinx.com / / 2100 Logic Drive 1-800-255-7778 \_\/.\ San Jose, California 95124-3450 1-408-879-5199 -------------------------------------------------------------------</pre> </html> --------------5C2B1F13B008223E2546BBEE-- --------------543AB0208BB11F553216FA5C Content-Type: text/x-vcard; charset=us-ascii; name="brianp.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Brian Philofsky Content-Disposition: attachment; filename="brianp.vcf" begin:vcard n:Philofsky;Brian tel;fax:(408) 879-4442 tel;work:1-800-255-7778 x-mozilla-html:TRUE org:<BR><H1 ALIGN="CENTER"><img src="http://www.xilinx.com/images/xlogoc.gif" alt="Xilinx" ALIGN="CENTER"> Design Center version:2.1 email;internet:brianp@xilinx.com title:<H3 ALIGN="CENTER"><img src="http://bennyhills.fortunecity.com/deadparrot/108/homer.gif" alt="Homer" align="center"> Design Engineer adr;quoted-printable:;;2100 Logic Drive=0D=0ADept. 2510;San Jose;CA;95124-3450;USA x-mozilla-cpt:;25776 fn:<H3 ALIGN="CENTER">Brian Philofsky end:vcard --------------543AB0208BB11F553216FA5C--Article: 18641
Besides Virtex and Virtex-E, you can use XC4000XL, XC4000XLA, or SpartanXL. XC4000XLA is the fastest of the three by a very small margin. I would try SpartanXL. Peter Alfke, Xilinx Applications ================================= "Child K.L. Sun" wrote: > >Current FPGAs are capable of 155Mbit/sec performance if you are careful with the > >design. With the information shown here, this should be an easy fit to an > >FPGA. Depending on the complexity of the encoder, you may even get away with a > >slower speed grade part. > > > > Thanks!! > Then, can I use the chip family of XC4000 (or even lower grade) other than > Virtex from Xilinx? > > ChildArticle: 18642
Hi - On Thu, 04 Nov 1999 17:42:37 GMT, Greg Neff <gregneff@my-deja.com> wrote: >In article <38218CCC.851ED115@yahoo.com>, > Rickman <spamgoeshere4@yahoo.com> wrote: > ><snip> >> The way to resolve metastability is to provide a >> window of excess setup time. ><snip> > >If you can guarantee setup time, then the input isn't asynchronous, and >the flip-flop will not be subject to metastability. The excess setup time Rick is referring to here is for the flip-flop(s) being driven by the synchronizing flip-flop. Suppose, for example, that a synchronizing FF is driving the enables of each of eight flip-flops in, say, a counter; both the counter FFs and the synchroizing FF are driven by the same clock. If there's sufficient excess setup time at each of those eight enables, a second level of synchronizing FF would not be necessary. If folks want to always use two synchronizing flip-flops in series, that's fine with me, because it's infinitely superior to doing nothing, and it works. But if there's sufficient time for a single synchronizing flip-flop to settle (sufficient = acceptably high MTBF), a second rank isn't necessarily mandatory. Bob Perlman ----------------------------------------------------- Bob Perlman Cambrian Design Works Digital Design, Signal Integrity http://www.best.com/~bobperl/cdw.htm Send e-mail replies to best<dot>com, username bobperl -----------------------------------------------------Article: 18643
For cost/performance, I'd look at using a SpartanXL. It has enough performance that you shouldn't have any problem with your design. The fastest speed grade of that part is even capable of parallel arithmetic at 155MS/s if you are careful with the design and layout. Child K.L. Sun wrote: > Thanks!! > Then, can I use the chip family of XC4000 (or even lower grade) other than > Virtex from Xilinx? > > Child -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18644
Hamilton Avnet has single piece pricing on their website. I don't have the URL immediately available, so you'll have to do a search. It is in their product availability section. project wrote: > Where can I find an address with FPGA prices? Or what is > aproximately the prize of an FPGA? > Thanks > > * Sent from AltaVista http://www.altavista.com Where you can also find related Web Pages, Images, Audios, Videos, News, and Shopping. Smart is Beautiful -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18645
hi,
the "eating" is sort of non-linear ... the reliability gets better
exponentially with more settling time.
as for actelian metastability numbers, they have published them for the old
act 1 versions ... don't have that reference handy but i can look it up ...
and haven't seen any (despite requests) to publish them since. for the 42mx,
there would be three cases (4 if you count ram cells for the models that have
it)
1) latches in the i/o ring
2) "hard-wired" flip-flops in the s-modules
3) "routed" flip-flops made out of c-modules.
the performance of the case 3 ones may be dependent on the actual macro used
in general and the loading on it in particular, as the feedback goes through
the regular routing network.
rk
==========================================
Ray Andraka wrote:
> Also, you should keep the route between the resynchronizers as short as
> possible (measured in time) because the propagation delay eats into your
> metastability resolution window.
>
> Greg Neff wrote:
>
> > In article <7vmc8l$ju8$1@nnrp1.deja.com>,
> > gallant@nm.hsd.utc.com wrote:
> > > Hello,
> > >
> > > I have a general FPGA design question. I have many asynchronous
> > inputs
> > > to my Actel 42MX device. Is the general practice to cascade 2 flip-
> > > flops for each input in order to reduce the probability of
> > > metastability? How can I calculate this probability?
> > >
> > > Where could I find more information about this subject (I searched the
> > > Actel web site but couldn't find anything)?
> > >
> > > Thanks in advance,
> > >
> > > Josh Gallant
> > >
> > > Sent via Deja.com http://www.deja.com/
> > > Before you buy.
> > >
> >
> > We work with Xilinx parts, but I can offer some advice that will
> > probably apply to Actel parts as well:
> >
> > 1) Standard practice is to use two registers to reduce the probability
> > of metastability. To quantify the probability, you need to get
> > characterization data from Actel. Once you have this, and the clock
> > frequency, then you can work out the probability. Contact an Actel
> > applications engineer to find out how to do this. Since Actel plays in
> > the hi-rel arena, I am sure that they will have this information.
> >
> > 2) Don't use standard routing resources for your register clocks! This
> > is a mistake that I have seen more times than I care to count. You
> > won't reduce the probability of metastability if you have a hold time
> > violation between registers. Low skew global clock nets are a must for
> > multi-stage registers of any kind, including counters, state machines,
> > pipelines, etc.
> >
> > --
> > Greg Neff
> > VP Engineering
> > *Microsym* Computers Inc.
> > greg@guesswhichwordgoeshere.com
> >
> > Sent via Deja.com http://www.deja.com/
> > Before you buy.
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930 Fax 401/884-7950
> email randraka@ids.net
> http://users.ids.net/~randraka
Article: 18646Hi Team, We have Study Room 27 in the Bus Lib at the normal time. -SteveArticle: 18647
Anyone else have problems installing this on an NT box? A bunch of DLLs were forgotten and things just wouldn't work. -a ----------------------------------------- Andy Peters Sr Electrical Engineer National Optical Astronomy Observatories 950 N Cherry Ave Tucson, AZ 85719 apeters (at) noao \dot\ edu "Creation Science" is oxymoronic.Article: 18648
Hi All, Has anybody experience with TRAC020 chip from http://www.fas.co.uk/silicon.htm? Their data sheet does not mention possibility of any programming for resistors and capacitors in the matrix. Is that just specification omission? Thanks, Alex SherstukArticle: 18649
Peter C <peterc@hmgcc.gov.uk> wrote in message
news:38200B8D.5DF@hmgcc.gov.uk...
> Yes (at least for those families that have 5-input CLBs).
But when I compile some 5-input functions such as the
following sample code, the FPGA compiler maps the function into
2 or 3 CLBs.
Do I need to convert the true-table into Boolean function first?
--sample code
entity FIVE_INPUT is
port (DIN: in std_logic_vector(4 downto 0);
DOUT: out std_logic);
end FIVE_INPUT;
architecture BEHAV of FIVE_INPUT is
begin
process (DIN)
begin
case DIN is
when "00000"=> DOUT <='1';
.......
when "11111"=>DOUT<'1';
when others=>DOUT<='X';
end case;
end process;
end BEHAV;
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