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Phil Hays wrote in message <381C922B.3603C633@sprynet.com>... >Andy Peters wrote: > >> I'm using an XC4KE part, I have a 32-bit bidirectional bus that comes out to >> the pins and I'd like to constrain the tristate enable so that it's faster. >> ... I have a signal called dataoe, which is a flip-flop output, and >> that signal is used as the tri-state enable for the outputs, which are >> called ramdata[31:0]. > >I have usually not had very good luck getting the Xilinx tools to improve timing >in a case like this by adding timing constraints. What I would suggest is that >you floorplan the dataoe flip-flop to the middle of the tristate bus. If that's >not fast enough, you might duplicate the dataoe flip-flop and floorplan the >copies. Another way would be to add a gclk buffer, floorplan it the buffer that >gives the best drive to the data bus pins and floorplan the dataoe flip-flop to >be in that corner of the die. Oh yeah, too late for this project, but the XLA parts have a flop in the IOB that drives the tristate enable. The only thing is that the p+r tools don't know how to deal with it, and you have to jump through hoops to use it. blech. -- ----------------------------------------- Andy Peters Sr Electrical Engineer National Optical Astronomy Observatories 950 N Cherry Ave Tucson, AZ 85719 apeters (at) noao \dot\ edu "Creation Science" is oxymoronic.Article: 18576
James Yeh wrote:
>
> I was wondering if somebody could tell me the trade offs of using one
> over the other.
>
> I have a design in Viewdraw currently (a SDRAM controller with a fairly
> complex FSM, which I have implemented by hand).
>
> The issues I have are
>
> a) I'm positive that StateCAD will do a better job in optimizing my FSM
> (speed or space) and I know I can put gates and components down from the
> Xilinx library.
StateCAD is a step above deriving your own state equations
and fitting them to primitive gates.
However for complex state machine design and maintenance
I would recommend a text based approach (VHDL, Verilog or Abel).
Draw the circles in your notebook, write the code and let the
computer handle the details. You can always use an .edf viewer
if you want to check the schematic.
> But what about its simulation environment? I
> incorporate a Micron VHDL model in my viewdraw design for simulation,
> and I was wondering if StateCAD does a good job of taking VHDL and
> allowing it to interact with real Schematics.
This is another advantage to a text-based approach.
Once you know the language, a simulation testbench is a quick
and clean solution.
> b) I was wondering if there were a lot of people who used StateCAD
> because, granted I've only been doing stuff with FPGA's for about a
> year, I just don't hear that much about the software (that actually
> could be a good thing :) )
I found that getting the circles and arrows right took longer than
just entering the code myself. I didn't always like the style
of the generated code. Diagrams over 16 states were not all that
easy to understand.
> c) Reliability. I have Service Pack 5, and well Viewdraw and what not
> is not the most stable software in the world, and was wondering if
> Statecad was any better at not crashing (I'm guessing not...blame it all
> on Bill anyway.....).
Text-based compilers might even crash less often.
-Mike Treseler
Article: 18577Hal, Xilinx just announced a Design Reuse Methodology and new tools. (http://www.xilinx.com/ipcenter/designreuse/index.htm) Along with the announcement is the new Xilinx Design Reuse Methodology for ASIC and FPGA Designers manual Xilinx (http://www.xilinx.com/ipcenter/designreuse/docs/Xilinx_Design_Reuse_Methodology.pdf). The last chapter talks about coding tips. I agree with most everything in the manual except the high fanout. The Virtex architecture handles high fanout very well. In my experience, synthesis design with a default fanout limit of 1000 run faster than synthesizing the same design with a global fanout of 100. This is opposite of the 4k families and derivatives (4k, 4ke, 4kxla, 4kxv, Spartan and Spartanxl) which don't handle high fanout very well at all. As far as the Altera vs Xilinx of course Xilinx is better! (Then again I am a little biased as a Xilinx FAE :-) ) But I will say the Xilinx tools and the Altera tools work differently. One difference is timing-driven vs non timing driven place and route. >From what I have seen there is little difference in performance between Altera's timing driven and non timing driven place and route. There usually is a difference between Xilinx's timing driven and non timing driven place and route. To determine how fast a design will run in a Virtex part, all clocks need to have a time constraint. This is very easy to do using our Constraints Editor. A good starting point for maximum performance is half of the frequency met after mapping the device but before place and route. This can be done by creating a Logic Level Timing Report where only logic delays are calculated. In a typical design, half of the period is in logic delay and half in routing. (Virtex logic is very fast so sometimes it is 40% logic and 60% routing.) For example, if the Logic Level Timing reports says the design can run at 150mhz, I would set the clock frequency at 75 mhz and use timing driven place and route. If you set the frequency at 30mhz, PAR will stop working as soon at 30mhz is reached even though the design can run much faster. And as somebody else pointed out, all Synopsys FPGA Express (and Xilinx Foundation Express) users should be using Express ver 3.3. Synopsys has many improvements especially for Virtex in Ver 3.3. Xilinx users should be on M2.1i Service Pack 2. Sorry for such a long book..... Kate Xilinx FAEArticle: 18578
On 1 Nov 1999 01:01:54 GMT, murray@pa.dec.com (Hal Murray) wrote: > >[snip bit-serial suggestions] > >> My point was that smaller/cheaper is not the issue for me at the >> moment, once smaller/cheaper becomes important, we'll be in ASIC >> territory anyway. > >Won't the same techniques help you get a smaller/cheaper ASIC? > Bit-serial will, but floorplanning an FPGA won't, so yes and no :) Martin >-- >These are my opinions, not necessarily my employers. Martin Thompson martin@the-thompsons.freeserve.co.uk http://www.the-thompsons.freeserve.co.uk/Article: 18579
On Sun, 31 Oct 1999 17:19:36 GMT, eml@riverside-machines.com.NOSPAM wrote: >On Sun, 31 Oct 1999 14:00:33 GMT, martin@the-thompsons.freeserve.co.uk >wrote: > >>My other problem is that I'm not au fait enough with either the Altera >>10K's or the Xilinx devices to really know how far I could push my >>example design if I put the effort in (without actually doing it, >>which will involve a significant investment in terms of time and >>needing to buy Xilinx tools we may not need). > >does this mean that you haven't got any xilinx tools? if so, how are >you doing your performance comparisons - are you relying on figures >reported by FPGA express? if you are: > I am... I'll borrow someone else's Xilinx license maybe and see what it reckons. Thanks for the info. Martin Martin Thompson martin@the-thompsons.freeserve.co.uk http://www.the-thompsons.freeserve.co.uk/Article: 18580
On Sun, 31 Oct 1999 15:30:12 -0500, Ray Andraka <randraka@ids.net> wrote: > > >martin@the-thompsons.freeserve.co.uk wrote: > >> >> My point was that smaller/cheaper is not the issue for me at the >> moment, once smaller/cheaper becomes important, we'll be in ASIC >> territory anyway. > >At the prices of the spartan devices, I think you may be pleasantly surprised as >to the cost compared with an ASIC. At under $10 in quantity, it requires a fairly >large production run with an ASIC to break even. Nice thing with an FPGA solution >is that is a lot easier and cheaper to make changes later if you need/want to. > OK, I hadn't realised they were quite that cheap! The application is automotive, so potential volumes are easily 100k+ per annum, but I know even less about ASIC's and their pricing, so I don't know what that means. Its still early days though, so plenty of time to study these things if I get in early enough :) <snip more useful info I shall keep for reference later!> >> >For low data rate stuff, I would prefer to use a smaller device and go with a >> >bit serial or digit serial design to keep unit costs down. The exception is >> >where the higher clock rates might cause you problems. The extra design >> >effort required for that type of architectural optimization is pretty small. >> > >> >> Again, units costs aren't really the issue, although if I can get an >> order of magnitude difference in price ... :) >> > >I think you're close to an order of magnitude in required area. The pricing at >the lower end is a little compressed, but I think you'll still see a half a >magnitude price reduction. Again, we're not talking an absolutely tailored design >here, just a change from a bit-parallel to a bit serial solution. > Sounds like I should look into this in some depth. >> I have to say that I am torn, in that we already use Altera devices >> (7K's) for a number of applications, but everything I read here >> implies that we need to look at Xilinx for these new applications. >> Most of our applications so far have been glue-logic type things >> rather than arithmetic based work. > >Ownership and familiarity of a particular vendor's tool set is a compelling reason >to stay with that vendor. Unless you find yourself hitting the wall because of >architectural differences, I'd probably stick with the Altera if I were in your >shoes (without knowing much about your design). On the other hand, you should at >least be aware of what can be done in other architectures so that you have an idea >of how much the altera solution is costing you in your system context. Also, it >might be worth comparing the cost of ownership of the Xilinx Spartan chips with an >Asic for your application. > I think I'm going to have to do some comparison work. I do have access to the Xilinx toolset within another part of the organisation, which will enable a more complete investigation. Thanks again for the info. Martin Martin Thompson martin@the-thompsons.freeserve.co.uk http://www.the-thompsons.freeserve.co.uk/Article: 18581
On Mon, 01 Nov 1999 09:38:31 +0000, Gary Cook <gc@sonyoxford.co.uk> wrote: >Hi, > >Using a Flex10K and have some code which has a bunch >of FF's that reset, and a few that preset. Now I understand >that the Flex will power up it's FF's in a low state, and it's >up to a reset input to perform a functional reset once the >device has configured. > >I also have a processor connected to the device and want to >hold it in reset until the FPGA has configured. I have looked >at using either INIT_DONE or CONF_DONE, but one >de-actives before the end of config, and the other is >inactive for a period at the start of config. I could also >set a pin on the FPGA permanently high in the verilog, >and us a pull-down externally so that during configuration >it goes low, and when the user i/o is enabled, it gets >driven high ... this could be my processor reset. I then >connect a separate reset line from the processor to the >fpga as the functional reset .... > >... sounds abit clunky though ... is there a more elegant >way of doing this? > >Thanks, > >Gary Cook, >Sony Oxford, UK. > > Hi Gary, I've used the INIT_DONE output as a global reset on a Flex6K successfully. There was a thread about this a while ago on this group. You may able to find it Deja News somewhere. Failing that give me a shout and I'll find my design. Cheers, Martin Martin Thompson martin@the-thompsons.freeserve.co.uk http://www.the-thompsons.freeserve.co.uk/Article: 18582
Does anyone have or know where I can get a few more Xilinx XC7372-12PC84C? Thanks, Charles Smith CHARLESSMITH@numa-inc.com cmsmith1@msn.comArticle: 18583
katem wrote: > Hal, > > Xilinx just announced a Design Reuse Methodology and new tools. > (http://www.xilinx.com/ipcenter/designreuse/index.htm) Along with the > announcement is the new Xilinx Design Reuse Methodology for ASIC and > FPGA Designers manual Xilinx > (http://www.xilinx.com/ipcenter/designreuse/docs/Xilinx_Design_Reuse_Methodology.pdf). > The last chapter talks about coding tips. > > I agree with most everything in the manual except the high fanout. The > Virtex architecture handles high fanout very well. In my experience, > synthesis design with a default fanout limit of 1000 run faster than > synthesizing the same design with a global fanout of 100. This is > opposite of the 4k families and derivatives (4k, 4ke, 4kxla, 4kxv, > Spartan and Spartanxl) which don't handle high fanout very well at all. > I'm not sure I'd call it handling it very well. You do still get a significant degradation of the routing delay as the number of loads is increased unless you get onto one of the limited number of global routing structures. Of course, if you are shooting for a 20 MHz or 30 MHz system clock, then this is not a problem as the devices are capable of 150+ MHz operation. > As far as the Altera vs Xilinx of course Xilinx is better! (Then again > I am a little biased as a Xilinx FAE :-) ) Depends on the application. I've seen my fair share of designs that map better to Altera than xilinx too. However, in my line of work (DSP FPGA designs), the xilinx devices do generally fare better for the reasons I've previously cited. > But I will say the Xilinx tools and the Altera tools work differently. > They sure do. Altera has pretty much just the big green compile button and little in the way of controls that influence the implementation. The lack of expert controls can be frustrating when you know what you want the tool to do. Xilinx provides links for the expert to control nearly every aspect of the design, including features not directly supported in the tools. Xilinx has a much steeper learning curve for one to become an expert, but their GUI is getting good enough for the novice to pick up the tools and start producing prtty quickly. A better combination for a one size fits all tool IMHO. > One difference is timing-driven vs non timing driven place and route. > From what I have seen there is little difference in performance between > Altera's timing driven and non timing driven place and route. There > usually is a difference between Xilinx's timing driven and non timing > driven place and route. This is due more to the routing architecture than the tools. Altera's routing is more or less global and the delay is constant for any connections in the same row/column. That's good for place and route and for consistent results. That's not so good for high performance since you drive all that capacitance even for local connections. Placement in Altera is therefore not very critical. You will find however that as the device gets close to full, the incomplete routing (not every LE can drive every other LE) starts to bite - so you start getting indirect routes or no route solution. That kills performance and causes the familiar pin-locking problems in full Altera devices. Xilinx, on the otherhand has a more segmented routing structure (yes, even in Virtex). That means, the routing delay increases with the distance from the driver, although a somewhat hierarchical routing scheme does help some here. As a result, the xilinx devices are much more sensitive to placement than the Altera devices. Despite what Xilinx implies, Virtex designs generally can benefit greatly from floorplanning. If you can keep the routing local though, the performance can be very high, and with proper floorplanning, it is rare to have pinlocking problems after incremental design changes. > To determine how fast a design will run in a > Virtex part, all clocks need to have a time constraint. This is very > easy to do using our Constraints Editor. A good starting point for > maximum performance is half of the frequency met after mapping the > device but before place and route. This can be done by creating a Logic > Level Timing Report where only logic delays are calculated. In a > typical design, half of the period is in logic delay and half in > routing. (Virtex logic is very fast so sometimes it is 40% logic and > 60% routing.) For example, if the Logic Level Timing reports says the > design can run at 150mhz, I would set the clock frequency at 75 mhz and > use timing driven place and route. If you set the frequency at 30mhz, > PAR will stop working as soon at 30mhz is reached even though the design > can run much faster. > As a first cut, allow 50% for logic, 50% for routing. The constraints seem to have the most effect in placement. A well placed design (ie floorplanned) often sees only small performance changes due to timing constraint changes. 30 MHz designs are generally a very easy target for Virtex, as the devices are capable of so much more. > And as somebody else pointed out, all Synopsys FPGA Express (and Xilinx > Foundation Express) users should be using Express ver 3.3. Synopsys has > many improvements especially for Virtex in Ver 3.3. > > Xilinx users should be on M2.1i Service Pack 2. > > Sorry for such a long book..... > > Kate > Xilinx FAE -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18584
This is a multi-part message in MIME format. --------------D7096778CB92F07723BACF22 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit I am new to using FPGAs in designs. I have a few doubts . I am using Xilinx FPGAs for my design. I need to understand about the XNF file formats and EDIF file formats. How these files translates the design into the hardware...can I read the files and make out how the mapping is done? Thanks for your effort. Cheers Anup --------------D7096778CB92F07723BACF22 Content-Type: text/x-vcard; charset=us-ascii; name="anup.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for anup kumar raghavan Content-Disposition: attachment; filename="anup.vcf" begin:vcard n:Anup Kumar;Raghavan tel;home:0061-7-38761962 tel;work:0061-7-33658849 x-mozilla-html:FALSE url:www.csee.uq.edu.au org:University of Queensland;Computer Science and Electrical Engineering adr:;;;;;;Australia version:2.1 email;internet:anup@elec.uq.edu.au fn:Anup Kumar end:vcard --------------D7096778CB92F07723BACF22--Article: 18585
XNF and EDIF files are netlists for your design (xnf is the old xilinx format, edif is an industry standard which is accepted by the new xilinx tools). The xilinx tools read one of these files to obtain your design, from there the tools perform a translation to an internal netlist, which is then mapped into FPGA resources, placed, routed and turned into a bitstream by the xilinx foundation or alliance tools. You need the xilinx tools to convert your edif or xnf netlists to hardware. anup kumar raghavan wrote: > I am new to using FPGAs in designs. I have a few doubts . > I am using Xilinx FPGAs for my design. I need to understand about the > XNF file formats and EDIF file formats. How these files translates the > design into the hardware...can I read the files and make out how the > mapping is done? > > Thanks for your effort. > > Cheers > Anup > > ------------------------------------------------------------------------ > > Anup Kumar <anup@elec.uq.edu.au> > University of Queensland > Computer Science and Electrical Engineering > > Anup Kumar > University of Queensland <anup@elec.uq.edu.au> > Computer Science and Electrical Engineering > Australia Home: 0061-7-38761962 > Work: 0061-7-33658849 > Additional Information: > Last Name Anup Kumar > First Name Raghavan > Version 2.1 -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18586
Maybe, you build an adder not a counter ?! roman Luigi Funes wrote: > I have a problem with Lattice ispExpert 7.1. > I wrote this very simple 16 bit counter in ABEL-HDL > > MODULE counter16 > count0..count15 pin istype 'reg'; > countck pin; > EQUATIONS > [count0..count15].clk = countck; > [count0..count15] := [count0..count15] + 1; > END > > Someone can explain me why it requires 18 macrocells instead 16? > I have to set some option in the compiler? > Besides, if I write > [count0..count15] := [count0..count15] + extpin; > where extpin is a input pin assuming 0 or 1 values, this requires > only 17 macrocells!!! > Thanks in advance. > > LuigiArticle: 18587
> The lack of expert controls can be frustrating when you know what you want > the tool to do. Xilinx provides links for the expert to control nearly every > aspect of the design... I'd like to add my vote for the bit tweezers too. You need all the other stuff, but as far as I'm concerned, a tool set is no good until it includes the magnifying glass so you can see/understand what's really going on and the tweezers so you can fix/build what you really want. I'm willing to work pretty hard to tell the system what I want it to do (say hand routing/placing), but I'm a lot happier if it can remember what I did for the next run so I don't have to do it again. And I get really frustrated when I can see what I want to do but can't figure out how to get it done. This goes for all levels of CAD tools, not just FPGAs. Hand routing a few key signals on PCBs is another good example. I still remember getting burned by the preliminary software for the Xilinx 9500 chips. I had a design that was right on the edge. I had some logic that was big enough that it needed to borrow a few terms from an adjacent block. It also had some terms that were right at the edge of the timing. The chip had enough main terms for the logic that needed to go fast but there wasn't any way to get the software to assign terms to fast vs borrow. I gave up and did something else. It would have been a nice fit if the software had a way to do what I needed. I would have happily spend a half-hour telling it which terms had to go fast. (I spent much more than that trying to.) I'm not trying to dump on Xilinx here. It was early software and I understand that some things may have had higher priorities. -- These are my opinions, not necessarily my employers.Article: 18588
> > > Hi Gary, > I've used the INIT_DONE output as a global reset on a Flex6K > successfully. There was a thread about this a while ago on this > group. You may able to find it Deja News somewhere. Failing that > give me a shout and I'll find my design. > Martin, doh! deja is usually the first thing I look at ... ! I got your thread .... presumably the INIT_DONE staying low during initialization is enough to reset/preset the internal registers if it is connected to the functional reset input? Thanks for the info, Gary.Article: 18589
Hello, I have a general FPGA design question. I have many asynchronous inputs to my Actel 42MX device. Is the general practice to cascade 2 flip- flops for each input in order to reduce the probability of metastability? How can I calculate this probability? Where could I find more information about this subject (I searched the Actel web site but couldn't find anything)? Thanks in advance, Josh Gallant Sent via Deja.com http://www.deja.com/ Before you buy.Article: 18590
One of the report files out of the lattice tools describes the logic in each macro cell. Look in there to see what got implemented. My first guess is that it put some of the wider gates (upper bits) in two levels of logic to reduce fan-in. The carry structure implemented by the elaborator is not a ripple carry structure, which means bit 15's logic has 16 inputs. The carry structure is smaller but a lot slower. Luigi Funes wrote: > I have a problem with Lattice ispExpert 7.1. > I wrote this very simple 16 bit counter in ABEL-HDL > > MODULE counter16 > count0..count15 pin istype 'reg'; > countck pin; > EQUATIONS > [count0..count15].clk = countck; > [count0..count15] := [count0..count15] + 1; > END > > Someone can explain me why it requires 18 macrocells instead 16? > I have to set some option in the compiler? > Besides, if I write > [count0..count15] := [count0..count15] + extpin; > where extpin is a input pin assuming 0 or 1 values, this requires > only 17 macrocells!!! > Thanks in advance. > > Luigi -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18591
Hi! Is there anybody who can explain me how a HDL-Design is mapped on logic level and what algorithms are used to optimize and map it on a FPGA? It must be a top secret because nobody knows anything about it (this statement depends on the people I have already asked). ThomasArticle: 18592
Thanks for the advertisement, Wendy ;-), and valid feedback. FYI others, it's in EDN's May 27, 1999 issue, and the design is based on the one I used for last year's HDL benchmarking study. Feedback, as always, appreciated >You may want to have a look at a recent article in EDN by Brian Dipert. >This was a "benchmark" of some FPGAs and general discussion on >benchmarking. There is an associated website which includes all the >example file, which are designed to conitain RAM state machines and >FIFO, so a good general purpose design. >Brian's benchmark is a little difficult because the vendors got to >choose one part for the study. So you have a $1000 dollar Virtex device >against a $40 AT40K from Atmel, so the results are not design specific >enough to help you. The useful test is to take the FPGAs that would be >competing for the same design like XC4000, Spartan At40K and maybe and >Altera 10K/*K and benchmark those ones. >You may be able to use these designs to generate your own more focussed >benchmark. > > > >* Sent from RemarQ http://www.remarq.com The Internet's Discussion Network * >The fastest and easiest way to search and participate in Usenet - Free! Brian Dipert Technical Editor: Memory, Multimedia and Programmable Logic EDN Magazine: The Design Magazine Of The Electronics Industry http://www.ednmag.com 1864 52nd Street Sacramento, CA 95819 (916) 454-5242 (voice), (916) 454-5101 (fax) ***REMOVE 'NOSPAM.' FROM EMAIL ADDRESS TO REPLY*** mailto:bdipert@NOSPAM.pacbell.net Visit me at http://members.aol.com/bdipertArticle: 18593
Hi all, StateCad simulation: There will be available a very comfortable state entry if the summit/viewlogic merger is finished. There, you can simulate graphically through your states. I am using WVO 7.53 with StateCad5.0 on a NT. (including all updates!) It is true that for small or very systematic state machines a written VHDL or even a schematic entry can produce an almost optimal design. If you have to design some 10 or 100 or 1000 K gates, you have to use a higher level of abstraction. A graphically control flow is quicker read then 1000 lines of HDL code (except for some very systematic state machines.) I use enumerate encoding at least for the functional system simulation. (other coding for synthesis) Your can display the state vector(s) (sreg) in the VWAVE trace window and you will get the enumerated name of the state (e.g. IDLE, GET_DATA;WAIT_FOR_READY,..). This is very useful if you analyze large parts of the design in detail and you only need the status of the state machines (e.g. the PCI bus controller state machine, but your focus is on the back end local bus analysis ). I did it for some system simulations based on the PCB schematics. Some devices have a VHDL design in the background (FPGA`s, partly StateCad VHDL sources), some devices have only VHDL simulation models and some devices have the built in gate simulation model (e.g. MSI logic, buffer,..). You can ignore the error messages for non devices without a simulation model (e.g. capacitor, connector,..). I do not have greater WVO stability problems than other tools (MS-Office,..). Holger DLR Institute of Space Sensor Technology and Planetary Exploration James Yeh schrieb: > I was wondering if somebody could tell me the trade offs of using one > over the other. > > I have a design in Viewdraw currently (a SDRAM controller with a fairly > complex FSM, which I have implemented by hand). > > The issues I have are > > a) I'm positive that StateCAD will do a better job in optimizing my FSM > (speed or space) and I know I can put gates and components down from the > Xilinx library. But what about its simulation environment? I > incorporate a Micron VHDL model in my viewdraw design for simulation, > and I was wondering if StateCAD does a good job of taking VHDL and > allowing it to interact with real Schematics. > > b) I was wondering if there were a lot of people who used StateCAD > because, granted I've only been doing stuff with FPGA's for about a > year, I just don't hear that much about the software (that actually > could be a good thing :) ) > > c) Reliability. I have Service Pack 5, and well Viewdraw and what not > is not the most stable software in the world, and was wondering if > Statecad was any better at not crashing (I'm guessing not...blame it all > on Bill anyway.....).Article: 18594
hi, step 1: hdl->gate level netlist first all hdl statements are mapped to operation macros, like adders, subers, multipliers, muxes, and so on. this step also called resource allocation. second all resources are scheduled such that some goal (area - timing - power) is achieved. For example, if you have 2 multiplier operations, to save area, only 1 multiplier is needed by sharing. third, each operation macros are mapped to library gates. each macro may have a number of libarary gate realization with different area-gate tradeoff. If a macro is already a library gate, then no need. the step1 is architecture independent. step 2: gate level netlist -> logic blocks first, the gate level netlist is mapped to LUTs/FFs; it can be timing driven or area driven; usually, it is a tradeoff. second, the LUTs and FFs are packed into logic blocks, since in real FPGA, a logic block has multiple LUTs/FFs. this step is architetcure dependent. the problems in the above steps mostly are NP-hard, so there are bunch of approx. algorithms used. wenyi Thomas Hedler wrote: > > Hi! > > Is there anybody who can explain me how > a HDL-Design is mapped on logic level and > what algorithms are used to optimize and map > it on a FPGA? > > It must be a top secret because nobody > knows anything about it (this statement depends > on the people I have already asked). > > ThomasArticle: 18595
This is available on the altera website www.altera.com All in downloadable .PDF docs... =:-) -- Bob Elkind Victor Levandovsky wrote: > > :)Article: 18596
Gary, Flex10K parts will configure with FFs in either SET or RESET state on power-up, individually configurable. The default is RESET, of course, but by invoking the .PRN (using the AHDL construct) pin, you can establish the default state on power up. The simulator will confirm that you've done the right thing. In many applications, I simply add a small state machine to generate a power-on set/reset signal. Of course, this consumes on-chip resources... -- Bob Elkind Gary Cook wrote: > > Hi, > > Using a Flex10K and have some code which has a bunch > of FF's that reset, and a few that preset. Now I understand > that the Flex will power up it's FF's in a low state, and it's > up to a reset input to perform a functional reset once the > device has configured. > > I also have a processor connected to the device and want to > hold it in reset until the FPGA has configured. I have looked > at using either INIT_DONE or CONF_DONE, but one > de-actives before the end of config, and the other is > inactive for a period at the start of config. I could also > set a pin on the FPGA permanently high in the verilog, > and us a pull-down externally so that during configuration > it goes low, and when the user i/o is enabled, it gets > driven high ... this could be my processor reset. I then > connect a separate reset line from the processor to the > fpga as the functional reset .... > > ... sounds abit clunky though ... is there a more elegant > way of doing this? > > Thanks, > > Gary Cook, > Sony Oxford, UK.Article: 18597
To avoid a complete place/route cycle, here are some "tools": 1. When you're happy with a design enough to call it a "baseline" design, use the asssign/back-annotate command to "save" the baseline cell placement. 2. In assign/ignore_project_assignments, make sure all boxes are unchecked. This forces the mapper to use the saved baseline placement as a template, which removes most/all randomness in the "compile" process. 3. Before hitting the "start" button on the compiler, make sure the "smart recompile" setting is checked in the Processing menu. This should give you the best "incremental re-compile" times. Also, make sure you have enough physical system memory available. In NT, Task Manager (or the hard disk activity LED) will tell you when you're paging excessively! Good luck. -- Bob Elkind dulik@my-deja.com wrote: > > Hello, > I'm a Xilinx user who just made his first (quite complex) design with > Altera. I have a problem with debugging it, because I miss the comfort > of EPIC chip editor in the Max+plus II (v. 9.3) software. So my > question is: > How to make a probe to a routed chip ? I mean: > How to put a signal from inside the chip to an unused I/O pin without > drawing it into the schematics and routing it all again (which takes > cca 20 min on Celeron 366MHz) ? > > Thanks in advance, > Tomas Dulik > > Sent via Deja.com http://www.deja.com/ > Before you buy.Article: 18598
--------------B23EA9FB1A2EA4FD28D74B07 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit gallant@nm.hsd.utc.com wrote: > Hello, > > I have a general FPGA design question. I have many asynchronous inputs > to my Actel 42MX device. Is the general practice to cascade 2 flip- > flops for each input in order to reduce the probability of > metastability? How can I calculate this probability? > > Where could I find more information about this subject Use one of the general-purpose search engines ( I like www.google.com ) One good description of metastability is in the Xilinx data book, page 14-46. I like it, because I wrote it :-) TI has some app notes also. Tom Chaney at Washington University is generally considered the head guru of metastability. tom@arl.wustl.edu The Altera app note AN042 is beautifully written, but when they copied my old 1988 test circuit, they got it all backwards. Their test circuit ( figure 4 ) is silly. Whatever it tests, it does NOT test metastability, therefore I do not believe their results. Pretty lay-out though, and nice print job, if only the information were meaningful... Peter Alfke, Xilinx Applications --------------B23EA9FB1A2EA4FD28D74B07 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> <p>gallant@nm.hsd.utc.com wrote: <blockquote TYPE=CITE>Hello, <p>I have a general FPGA design question. I have many asynchronous inputs <br>to my Actel 42MX device. Is the general practice to cascade 2 flip- <br>flops for each input in order to reduce the probability of <br>metastability? How can I calculate this probability? <p>Where could I find more information about this subject</blockquote> Use one of the general-purpose search engines ( I like www.google.com ) <p>One good description of metastability is in the Xilinx data book, page 14-46. I like it, because I wrote it :-) <br>TI has some app notes also. <br>Tom Chaney at Washington University is generally considered the head guru of metastability. <u>tom@arl.wustl.edu</u><u></u> <p>The Altera app note AN042 is beautifully written, but when they copied my old 1988 test circuit, they got it all backwards. Their test circuit ( figure 4 ) is silly. Whatever it tests, it does NOT test metastability, therefore I do not believe their results. Pretty lay-out though, and nice print job, if only the information were meaningful... <p>Peter Alfke, Xilinx Applications</html> --------------B23EA9FB1A2EA4FD28D74B07--Article: 18599
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