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Does anyone know how to the time between two consecutive events on a signals for reporting in a testbench? (I basically need to check & report a pulse width) Thanks in advance, Mark Harvey. Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 18001
Hi,
Mark Harvey wrote:
> Does anyone know how to the time between two consecutive events on a signals
> for reporting in a testbench?
> (I basically need to check & report a pulse width)
>
This depends on the HDL language you are using. For VHDL'93 you may try:
signal sig : ...
watch: process (sig)
variable last : time;
variable first_run : boolean := true;
begin
if not first_run then
report "pulse duration = " & time'image(now - last);
end if;
last := now;
first_run := false;
end process;
--
Edwin
Article: 18002
In article <37E5DFED.7402@mazsola.iit.uni-miskolc.hu>, Drotos Daniel <drdani@mazsola.iit.uni-miskolc.hu> writes:
|> Hi,
|>
|> I'm trying to configure a Spartan chip (XCS20XL-PQ208) and it doesn't
|> work. I'm using slave mode, generating 640ns wide CCLK pulses and
|> about 16usec between them. I've checked DOUT, it is OK.
|>
|> The problem is, that INIT goes low after the first frame which means
|> that frame error is detected. If I turn off the CRC checking when
|> generating the bitstream, then the chip accepts the first frame and
|> pulls INIT low after the second frame.
|>
|> I've tried to download the configuration via the xchecker cable
|> using JTAG programmer of the Foundation 1.51i. It downloads the
|> bitstream via the boundary scan interface and everything looks
|> OK (DONE goes high for example) but the chip doesn't operate.
|> When I try to verify, it says "to many mismatches".
|>
|> Does somebody have any idea what can be wrong?
Maybe it's as simple as that:
If you generate the bitstream by hand (ie. not using designmgr but makefile etc),
make sure you use the right partnumber. ppr swallows all combinations of part
numbers, but mostly interpretes them as a non-xl device, thus generating a
bitstream that is too short. For a 10XL in a VQ100, speed grade -4 ONLY the
type s10xlVQ100-4 works. Other types (like XCS10XL, printed on the chip) are
converted to non-XL.
I've searched a long time to find this...
--
Bye
Georg Acher, acher@in.tum.de
http://www.in.tum.de/~acher/
"Oh no, not again !" The bowl of petunias
Article: 18003Three simple questions that I couldn't figure out from the online data sheet: Can the carry chain be routed through both slices of a CLB, or is it more efficient to run it to the next CLB? Do both slices of a CLB share a common clock and CE, or are there separate pins for each slice? How are CLB outputs routed to the TBUFs? Do all CLB outputs have access to both TBUFs or are there some restrictions? -- Don Husby <husby@fnal.gov> http://www-ese.fnal.gov/people/husby Fermi National Accelerator Lab Phone: 630-840-3668 Batavia, IL 60510 Fax: 630-840-5406Article: 18004
Don Husby wrote: > Three simple questions that I couldn't figure out from the online data sheet: > > Can the carry chain be routed through both slices of a CLB, or is it more > efficient to run it to the next CLB? > There are two carry chains in the CLB, each runs through a slice and then connects to the next slice vertically. The carry chain connection doesn't go horizontally (to the adjacent slice). You can get a connection from slice to slice by going out the YB or XB and in to the carry in on the other slice, but that connection is slow compared to the dedicated carry chain connections (the carry chain connections go directly to the slices while the other connections generally go through the omux and imux. > Do both slices of a CLB share a common clock and CE, or are there separate > pins for each slice? > Each slice has separate connections for CE, clk and SR input multiplexer in the CLB. > How are CLB outputs routed to the TBUFs? Do all CLB outputs have access to > both TBUFs or are there some restrictions? > Looking at the Omux and Imux in epic, it appears that any of the outputs can get to any of the TBUFs. I haven't tried all combinations here, so I'm not sure. > -- > Don Husby <husby@fnal.gov> http://www-ese.fnal.gov/people/husby > Fermi National Accelerator Lab Phone: 630-840-3668 > Batavia, IL 60510 Fax: 630-840-5406 -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18005
I have seen the pdf file on how to build an inexpensive in-circuit programming link to the parallel port of a PC. Suppose I would like to have an inexpensive way to program chips that is not an in-circuit method. Perhaps something that connects to the parallel port of the same PC that I am using to generate source and object code for these chips...I burn the chips, and stick them into sockets on my breadboard....Of course I must be careful about static electricity. Any suggestions would be appreciated. Can I get something for a couple hundred bucks? I prefer Altera and Lattice chips. Thanks, JohnArticle: 18006
Hi, I am a new Altera user, have a long background in Xilinx and now trying to understand the logic behind the Global reset on Altera FPGAs. I have a lot of code there I reset the signals when the reset_n signal is '0', that works very well for simulation and then I thought that Altera mapper should take care of it too, but it seems that Altera does not have a global RESET signal and I can not assign a pin to act as one either! Is it true? Because I think it is SICK, how on earth can a user deal without a global RESET? I know that I can assign my signals to a value when I declare them, but then I will receive hundreds of warnings when I synthisize the code (which I absolutely will not do!). Can anyone help me? Because the only way for me to solve this problem was to hard code that signal on my top level, and assign it to '1' to be able to use my synthesized code! TIA, Farhad A. -- -------------------------------------------- |Farhad Abdolian, Tellabs Operations Inc. | |farhad.abdolian@tellabs.com, +1-914-593-4346| --------------------------------------------Article: 18007
In article <37E5DFED.7402@mazsola.iit.uni-miskolc.hu>, Drotos Daniel <drdani@mazsola.iit.uni-miskolc.hu> wrote: > Hi, > > I'm trying to configure a Spartan chip (XCS20XL-PQ208) and it doesn't > work. I'm using slave mode, generating 640ns wide CCLK pulses and > about 16usec between them. I've checked DOUT, it is OK. > > The problem is, that INIT goes low after the first frame which means > that frame error is detected. If I turn off the CRC checking when > generating the bitstream, then the chip accepts the first frame and > pulls INIT low after the second frame. > > I've tried to download the configuration via the xchecker cable > using JTAG programmer of the Foundation 1.51i. It downloads the > bitstream via the boundary scan interface and everything looks > OK (DONE goes high for example) but the chip doesn't operate. > When I try to verify, it says "to many mismatches". > > Does somebody have any idea what can be wrong? > > Daniel > I had the same problem, and found the answer on the Xilinx web site. Don't use the verify option, and simply check the DONE pin. Leon -- Leon Heller, G1HSM Tel (Mobile): 079 9098 1221 (Work): 01327 357824 Email: leon_heller@hotmail.com Web: http://www.geocities.com/SiliconValley/Code/1835 Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 18008
Which Altera devices? The devices I've used (MAX7000 and FLEX10K) most certainly do have global reset! Go look up 'global' in Max+Plus II help. On Wed, 22 Sep 1999 15:23:30 -0400, in <37E92CB2.5715C232@tellabs.com> Farhad Abdolian <farhad.abdolian@tellabs.com> wrote: >Hi, >I am a new Altera user, have a long background in Xilinx and now trying >to understand the logic behind the Global reset on Altera FPGAs. > >I have a lot of code there I reset the signals when the reset_n signal >is '0', that works very well for simulation and then I thought that >Altera mapper should take care of it too, but it seems that Altera does >not have a global RESET signal and I can not assign a pin to act as one >either! > >Is it true? Because I think it is SICK, how on earth can a user deal >without a global RESET? I know that I can assign my signals to a value >when I declare them, but then I will receive hundreds of warnings when I >synthisize the code (which I absolutely will not do!). > >Can anyone help me? Because the only way for me to solve this problem >was to hard code that signal on my top level, and assign it to >'1' to be able to use my synthesized code! > >TIA, >Farhad A. -- Steve Rencontre, Design Consultant http://www.rsn-tech.demon.co.uk/ -- remember to despam return addressArticle: 18009
In article <37E92CB2.5715C232@tellabs.com>, Farhad Abdolian <farhad.abdolian@tellabs.com> wrote: > Hi, > I am a new Altera user, have a long background in Xilinx and now trying > to understand the logic behind the Global reset on Altera FPGAs. > > I have a lot of code there I reset the signals when the reset_n signal > is '0', that works very well for simulation and then I thought that > Altera mapper should take care of it too, but it seems that Altera does > not have a global RESET signal and I can not assign a pin to act as one > either! > > Is it true? Because I think it is SICK, how on earth can a user deal > without a global RESET? I know that I can assign my signals to a value > when I declare them, but then I will receive hundreds of warnings when I > synthisize the code (which I absolutely will not do!). > > Can anyone help me? Because the only way for me to solve this problem > was to hard code that signal on my top level, and assign it to > '1' to be able to use my synthesized code! > Altera's handling of reset is perhaps not ideal, but is not as bad as you make out. If you are using Verilog, then simply pass your global reset signal through a "global" module i.e. input nRESET; wire gnRESET; global myreset ( .in( nRESET ), .out( gnRESET ) ); The compiler will spot this and allocate your global reset to one of the global nets on the device. Depending on the device there are between roughly 2 and 6 of these (check your Altera data sheet). Alternatively, if you go into the Assign/Global project logic synthesis settings, then there's an auto global switch; however I have known this not to allocate a global line if the reset line is used in a non-global way at all. Finally, most devices have a dedicated global reset (DEV_CLRn) which can be enabled from the Assign/Global project device options menu. The drawback of using this however is that (so far as I can tell) is that the compiler won't automatically recognise this from your Verilog code and so all your explicitly defined reset signals will get synthesised as well. I prefer using the global module approach. I can testify that it works fine and it gives you control of what's going on without having to write anything too Altera specific in your code. Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 18010
I am using the Altera Baseline Max+Plus software, version 9.3, as recently downloaded from Altera. I have designed a few state machines, and I would like to simulate their performance. I have created an .scf file using the Waveform Editor, and I configured it so that my waveform simulation would show several input and output signals, as found in the project .snf file (I used Node menu, Enter Nodes from SNF). So far, so good. I notice that the span of time covered during the simulation is 1 us (i.e., microsecond). I would like to change this span to me much longer, perhaps 1 second. I can't figure out how to do this. Could anyone please tell me what to do? ********************** I have read some of the HELP available, and it has told me to find a "Processing menu in the Compiler." I haven't been able to find any such "Processing Menu" anywhere. Can anyone tell me where to look? Or is such menu available only in other software than what I am using? Thanks, John BecichArticle: 18011
Hello. Sorry, this is not entirely FPGA related. Has anybody used a 0.8mm pitch BGA on their board? I am using the CS280 package from Xilinx and have some questions. What trace/via/pad and clearances were used on the PCB? Any links to guidelines on using these devices would be nice. My layout guy hasn't found anything on these devices yet. Thanks for your time.Article: 18012
In article <7s8iqa$20ae$1@thoth.cts.com>, "Steve Kinkead" <stevek@cts.com> wrote: > I am using the Select I/O feature in a Xilinx Vertex device to configure > my outputs to 3.3v PCI. In my .ucf constraint file I specify each I/O > to be PCI using the following: > > NET "nFrame" IOSTANDARD = PCI33_3; > > But, the place and route software seems to ignore the contraint and sets > all the I/O to be LVTTL. > > I created the design using Verilog and have not hand-instantiated any I/O > cells > except for the clock buffers in the clock dlls. A Xilinx app note says > that > if you hand-instantiate any I/O cells you must hand-instantiate all of them > due to a limitation with FPGA Express. > > Anyone found a work-around? > -- > ============================================== > Steve Kinkead 5951 Seacrest View Rd > Infinite Logic, LLC San Diego, CA 92121 > Hardware Design Consulting (858) 638-1457 > stevek@cts.com (858) 638-0998 : FAX > > I'm using FPGA Express with VHDL and in the "constraints" windows and in "Ports" you can specify the default I/O type. By default, it's LVT, 12mA, slow but you can change it ! all the best.. Rémi SEGLIE Company : CELOGIC www : http://www.celogic.com/ Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 18013
In article <7s8iqa$20ae$1@thoth.cts.com>, "Steve Kinkead" <stevek@cts.com> wrote: > I am using the Select I/O feature in a Xilinx Vertex device to configure > my outputs to 3.3v PCI. In my .ucf constraint file I specify each I/O > to be PCI using the following: > > NET "nFrame" IOSTANDARD = PCI33_3; > > But, the place and route software seems to ignore the contraint and sets > all the I/O to be LVTTL. > > I created the design using Verilog and have not hand-instantiated any I/O > cells > except for the clock buffers in the clock dlls. A Xilinx app note says > that > if you hand-instantiate any I/O cells you must hand-instantiate all of them > due to a limitation with FPGA Express. > > Anyone found a work-around? > -- > ============================================== > Steve Kinkead 5951 Seacrest View Rd > Infinite Logic, LLC San Diego, CA 92121 > Hardware Design Consulting (858) 638-1457 > stevek@cts.com (858) 638-0998 : FAX > > It is a problem! I work on VHDL with Xilinx Express under Windows. I had same problem. I have connected library Unisim. library unisim; use unisim.vcomponent.all; It for simulation in ModelSim In library Virtex there are components PCI buf Further, in the text VHDL I used these components. component OBUF_PCI33_3 ..... end component; It has helped. Good luck ============================= Logvin Victor. Rossia. vlogvin@mydeja.com‰ Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 18014
Open .SCF file (waveform editor)
Menu bar: File/End_time
enter value.
Voila!
(BTW, I agree that if you don't know where to look, it's almost
impossible to find!)
-- Bob Elkind
John Becich wrote:
>
> I am using the Altera Baseline Max+Plus software, version 9.3, as recently
> downloaded from Altera. I have designed a few state machines, and I would
> like to simulate their performance.
>
> I have created an .scf file using the Waveform Editor, and I configured it
> so that my waveform simulation would show several input and output signals,
> as found in the project .snf file (I used Node menu, Enter Nodes from SNF).
> So far, so good.
>
> I notice that the span of time covered during the simulation is 1 us (i.e.,
> microsecond). I would like to change this span to me much longer, perhaps 1
> second. I can't figure out how to do this.
>
> Could anyone please tell me what to do?
>
> **********************
>
> I have read some of the HELP available, and it has told me to find a
> "Processing menu in the Compiler." I haven't been able to find any such
> "Processing Menu" anywhere. Can anyone tell me where to look? Or is such
> menu available only in other software than what I am using?
>
> Thanks,
> John Becich
Article: 18015Can you or your company afford paying 10000$ at least for these programs ?!!? If you can then ignore this posting, otherwise I can offer an alternative at 1/100 th of the original price. I offer perfect solutions for small enterprizes and I would like to emphasize on perfect. Just send me an e-mail to freelicenses@hotmail.com or flexlm666@my- deja.com Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 18016
I'm trying to map some existing VHDL code(describing a datapath with a
32bit adder)
into the Virtex FPGA using Foundation2.1i on the PC. Previously this
data path was
mapped to a standard ASIC library using DC(Design Compiler) on a Unix
work station.
When I set the clock constraint to >50MHz on the Unix version of DC, it
inferred a "fast-
carry" adder(used porpagate/generate terms) and the design meets timing.
When I set the same clock constraint on the same VHDL code in
Foundation2.1i
(targetting a Virtex XVC400) it doesn't meet timing, running somewhat
less than
50MHz. Note: the version of Synopsys Design Compiler running inside
Foundation2.1i
is called "FPGA Express" I believe, and may not be the same DC that
runs on Unix.
When I reviewed the long path in the static timing analysis, it showed
the long path
"rippling" through 32 CLB's(each CLB =2bit adder + carryin). This
version of DC
did not infer the "fast-carry" adder required to meet timing. This is
not a case of
improper clock constraints because the timing analyzer reports that it
missed the
50MHz target and only runs ~30MHz!
Note: I do have the following in the VHDL code:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;
When Xilinx talks about fast carry generation logic apparently they mean
generate
a "ripple-carry" fast!?
I've discussed this w/ with an engineer at Xilinx Technical Support. He
ran a testcase
where he described a 32-bit adder between two registers. He used the
same code
that I am using for the add function:
SUM <= A(31 downto 0) + B(31 downto 0);
with the same clock constraint on Foundation2.1i and got the same
results: one
big ripple-carry adder which did not meet timing. To get around this
problem
I am coding the 32-bit propagate/generate fast-carry adder by hand.
Anyone else seen this problem?
Steve Martindell
real email address is:
s-martindell@ti.com
Article: 18017hi, a few questions on the virtex clock system (+): 1. let's assume that i get the fastest speed grade part. 2. let's assume i get the xcv1000. i need the biggest one for it's height. actual utilization will be very low. let's say i use about 4 columns, max. 3. let's assume that i use a linearly regulated power supply and there is very little ripple on it. nothing else is on the supply. 4. can i run a low skew clock at 250 MHz? i think that speed will work for my application(*). what speed is achievable? 5. what is the power in mwatt/MHz for that clock? 6. what is the maximum flop-flop skew for the low skew clock? 7. anyone have a feel for how much jitter would be on the clock? see 3, above. 8. ball park estimate for part cost? i am w/out clue. (yeah, i can try the www, but getting into the distributor www site was way slow this evening). thanks very much in advance, a bit urgent, rk (+) yeah, i can read the whole data sheet, app notes, etc., etc. but need some estimates quick for day job. and am under the cannon to get some stuff out NOW! (more than just this and it's gonna be another loooooooooooooong night :-) (*) the application is right now a proposal and feasibility study i'm doing. so, no sales critter follow-ups, please. if we do it, we can figure out where to buy them.Article: 18018
Hello Ozgur, Stuart is a distributor of the Exemplar product, a direct competitor of ours. I thought it might be helpful if I corrected his statement. Synplify 5.2.1 is an official release of Synplify, as was version 5.1.5a. Synplify 5.2.1 adds support for the new Apex20K architecture from Altera. It is identical to 5.1.5a for other vendors. Therefore, I expect you will experience the same behavior for Spartan in either 5.1.5a or 5.2.1. It is perfectly ok to use 5.2.1 for Spartan. We do not know of any problems with inferencing or creation of counters in our software since the 5.0.8a release. If you have a test case that demonstrates the reduced counter detection, we will gladly take a look at it. You can send it to us at support@synplicity.com and we will do our best to understand the difference. Best regards, Andrew Dauman Director of Corporate Applications Engineering Synplicity, Inc. Ozgur Kayalar wrote: > Hi > I use Synplify version 5.21. > Version 5.21 cannot find counters as the previous version v5.08a does. > Ver.5.21 finds 1 counter while v5.08a finds 5 counters in my same > design. > This is valid for the target Xilinx Spartan 30 device, and I wonder if > v521 cause Design Manager not to use carry logic for the 'missing' > counters. > Maybe it is better to use older version of Synplify in such a condition > Does anyone observed such a situation?Thank you for your time, > OzgurArticle: 18019
er, what was exactly the problem in the earlier release? <rk gets nervous> thanks, rk Andrew Dauman wrote: > Hello Ozgur, > > Stuart is a distributor of the Exemplar product, a direct competitor of > ours. > I thought it might be helpful if I corrected his statement. > Synplify 5.2.1 is an official release of Synplify, as was version 5.1.5a. > Synplify 5.2.1 adds support for the new Apex20K architecture from Altera. > It is identical to 5.1.5a for other vendors. Therefore, I expect you will > experience > the same behavior for Spartan in either 5.1.5a or 5.2.1. It is perfectly ok > to use 5.2.1 > for Spartan. > > We do not know of any problems with inferencing or creation of counters in > our software > since the 5.0.8a release. If you have a test case that demonstrates the > reduced > counter detection, we will gladly take a look at it. You can send it to us > at support@synplicity.com > and we will do our best to understand the difference. > > Best regards, > Andrew Dauman > Director of Corporate Applications Engineering > Synplicity, Inc. > > Ozgur Kayalar wrote: > > > Hi > > I use Synplify version 5.21. > > Version 5.21 cannot find counters as the previous version v5.08a does. > > Ver.5.21 finds 1 counter while v5.08a finds 5 counters in my same > > design. > > This is valid for the target Xilinx Spartan 30 device, and I wonder if > > v521 cause Design Manager not to use carry logic for the 'missing' > > counters. > > Maybe it is better to use older version of Synplify in such a condition > > Does anyone observed such a situation?Thank you for your time, > > OzgurArticle: 18020
Steve,
You need to include the basic design ware libraries. DW01 and DW02.
These should come with the basic Synopsys package. Hope
this helps.
change the c to a k and com to net to reach me. I try to avoid spam
Tim
Steve Martindell wrote:
> I'm trying to map some existing VHDL code(describing a datapath with a
> 32bit adder)
> into the Virtex FPGA using Foundation2.1i on the PC. Previously this
> data path was
> mapped to a standard ASIC library using DC(Design Compiler) on a Unix
> work station.
> When I set the clock constraint to >50MHz on the Unix version of DC, it
> inferred a "fast-
> carry" adder(used porpagate/generate terms) and the design meets timing.
>
> When I set the same clock constraint on the same VHDL code in
> Foundation2.1i
> (targetting a Virtex XVC400) it doesn't meet timing, running somewhat
> less than
> 50MHz. Note: the version of Synopsys Design Compiler running inside
> Foundation2.1i
> is called "FPGA Express" I believe, and may not be the same DC that
> runs on Unix.
>
> When I reviewed the long path in the static timing analysis, it showed
> the long path
> "rippling" through 32 CLB's(each CLB =2bit adder + carryin). This
> version of DC
> did not infer the "fast-carry" adder required to meet timing. This is
> not a case of
> improper clock constraints because the timing analyzer reports that it
> missed the
> 50MHz target and only runs ~30MHz!
>
> Note: I do have the following in the VHDL code:
> library IEEE;
> use IEEE.std_logic_1164.all;
> use IEEE.std_logic_signed.all;
>
> When Xilinx talks about fast carry generation logic apparently they mean
> generate
> a "ripple-carry" fast!?
>
> I've discussed this w/ with an engineer at Xilinx Technical Support. He
> ran a testcase
> where he described a 32-bit adder between two registers. He used the
> same code
> that I am using for the add function:
>
> SUM <= A(31 downto 0) + B(31 downto 0);
>
> with the same clock constraint on Foundation2.1i and got the same
> results: one
> big ripple-carry adder which did not meet timing. To get around this
> problem
> I am coding the 32-bit propagate/generate fast-carry adder by hand.
> Anyone else seen this problem?
>
> Steve Martindell
> real email address is:
> s-martindell@ti.com
Article: 18021Hi, We have synthesized a design for Altera's Flex10k family fpga (EPF10K100ABC600-1) starting from VHDL. We are using Synopsys for synthesis and Maxplus II ver 9.25 for place and route. This returns pin assignments for the IO ports in our design. Our FPGA is located on a PCB. We fixed the pin assignments and hence the PCB routing using one of the synthesis runs that met our clock requirements (50Mhz). Subsequently, we have discovered a bug in our design that needs a small change to fix (adding a flip-flop). Now since the PCB routing is fixed, we have to provide Maxplus with pin constraints (otherwise it produces a totally different pin assignment). This causes Maxplus to give us a best case clock of 33MHz and the p&r takes more than 10 hrs even though the change to the design is minimal. 1) Is there a way to retain most of the placed and routed design from a previous run and add a small 'patch' to the design in Maxplus without affecting the existent placement and routing? 2) Is there a way in which the p&r algorithm can be made to provide the same pin assignment as we got for the previous run without constraining it with pin assignments? Thanks, PrashantArticle: 18022
Article: 18023
the book has send it. isbn-0-13-977-398-3 thank you Adam Biniszkiewcz <A.Biniszkiewicz@pz.zgora.pl> wrote in message news:7q3gtr$o5j$1@main.amu.edu.pl... > Hi, > I want to buy Xilinx Foundation, version 1.5 with FPGA Express. > Can you provide me with pricing, if someone is interested in? > Regards - Adam > A.Biniszkiewicz@pz.zgora.pl > > >Article: 18024
On Thu, 23 Sep 1999 21:00:40 -0400, rk <stellare@NOSPAM.erols.com> wrote: [snip] >3. let's assume that i use a linearly regulated power supply and there >is very little ripple on it. nothing else is on the supply. >7. anyone have a feel for how much jitter would be on the clock? see 3, >above. I have data sheets for both Virtex and Apex (Altera) parts. Interestingly, the jitter spec for both is the same (200ps assuming 50ps input jitter), even though the Xilinx part uses a DLL and the Altera part uses a PLL. I think that the DLL should give better jitter performance. (Or perhaps Xilinx made some cost tradeoff.) Certainly, the jitter transfer functions should be different. (PLL should be lowpass; DLL should be flat.) Has anyone observed this on a real part? Allan.
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