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Threads Starting Apr 2008
130759: 08/04/01: Torsten Landschoff: Simple (?) timing constraint for output pins
130761: 08/04/01: <job@amontec.com>: Re: Simple (?) timing constraint for output pins
130802: 08/04/02: MM: Re: Simple (?) timing constraint for output pins
130763: 08/04/01: Torsten Landschoff: Re: Simple (?) timing constraint for output pins
130770: 08/04/01: Torsten Landschoff: Re: Simple (?) timing constraint for output pins
130803: 08/04/02: Torsten Landschoff: Re: Simple (?) timing constraint for output pins
130804: 08/04/02: Torsten Landschoff: Re: Simple (?) timing constraint for output pins
130775: 08/04/01: <robquigley@gmail.com>: ISE 9.2i project question
130777: 08/04/01: <robquigley@gmail.com>: Re: ISE 9.2i project question
130776: 08/04/01: austin: now I can talk about it...
130779: 08/04/01: Jon Beniston: Re: now I can talk about it...
130780: 08/04/01: austin: Re: now I can talk about it...
130781: 08/04/01: austin: Re: now I can talk about it...
130797: 08/04/02: Frank Buss: Re: now I can talk about it...
130801: 08/04/02: Jim Granville: Re: now I can talk about it...
130784: 08/04/01: Peter Alfke: Re: now I can talk about it...
130809: 08/04/02: austin: Re: now I can talk about it...
130785: 08/04/01: Jon Beniston: Re: now I can talk about it...
130790: 08/04/01: Peter Alfke: Re: now I can talk about it...
130791: 08/04/01: austin: Re: now I can talk about it...
130786: 08/04/01: <paragon.john@gmail.com>: Re: now I can talk about it...
130799: 08/04/02: Symon: Re: now I can talk about it...
130810: 08/04/02: <paragon.john@gmail.com>: Re: now I can talk about it...
130798: 08/04/02: <sky465nm@trline4.org>: Re: now I can talk about it...
130793: 08/04/01: fl: Why does ISE 9.2 optimize out the logic
130800: 08/04/01: ni: coregenerator bram in synplify pro error
130813: 08/04/02: Duane Clark: Re: coregenerator bram in synplify pro error
130821: 08/04/02: Duane Clark: Re: coregenerator bram in synplify pro error
130840: 08/04/03: Brian Drummond: Re: coregenerator bram in synplify pro error
130845: 08/04/03: Jeff Cunningham: Re: coregenerator bram in synplify pro error
130858: 08/04/03: jtw: Re: coregenerator bram in synplify pro error
130863: 08/04/03: Duane Clark: Re: coregenerator bram in synplify pro error
130869: 08/04/04: jtw: Re: coregenerator bram in synplify pro error
130860: 08/04/03: Duane Clark: Re: coregenerator bram in synplify pro error
130861: 08/04/03: Mike Treseler: Re: coregenerator bram in synplify pro error
130818: 08/04/02: ni: Re: coregenerator bram in synplify pro error
130824: 08/04/02: ni: Re: coregenerator bram in synplify pro error
130805: 08/04/02: Pablo: "Number of BSCANs: 2 out of 1 200%"
130806: 08/04/02: <tarmopalm@gmx.de>: Re: "Number of BSCANs: 2 out of 1 200%"
130807: 08/04/02: Zara: Re: "Number of BSCANs: 2 out of 1 200%"
130808: 08/04/02: Torsten Landschoff: Re: "Number of BSCANs: 2 out of 1 200%"
130848: 08/04/03: Pablo: Re: "Number of BSCANs: 2 out of 1 200%"
130875: 08/04/04: Moazzam: Re: "Number of BSCANs: 2 out of 1 200%"
130876: 08/04/04: Pablo: Re: "Number of BSCANs: 2 out of 1 200%"
130811: 08/04/02: <robquigley@gmail.com>: Xst_Choice nodes
130812: 08/04/02: Kolja Sulimma: Re: Xst_Choice nodes
130814: 08/04/02: disq: Xilinx ISE 10.1 Ubuntu Linux Installation - Driver Installation
130816: 08/04/02: Uwe Bonnes: Re: Xilinx ISE 10.1 Ubuntu Linux Installation - Driver Installation ?Problem
130820: 08/04/02: Dan K: ModelSim XE problems with a VHDL coregen in a Virtex 5
130884: 08/04/04: Sean Durkin: Re: ModelSim XE problems with a VHDL coregen in a Virtex 5
130823: 08/04/02: <craig.taylor@xilinx.com>: Conterfeit parts guidance
130879: 08/04/04: Morten Leikvoll: Re: Conterfeit parts guidance
130897: 08/04/04: Symon: Re: Conterfeit parts guidance
130909: 08/04/04: Nico Coesel: Re: Conterfeit parts guidance
130915: 08/04/05: Jim Granville: Re: Conterfeit parts guidance
130956: 08/04/07: Jim Granville: Re: Conterfeit parts guidance
130912: 08/04/05: <sky465nm@trline4.org>: Re: Conterfeit parts guidance
130955: 08/04/06: <pdorsey@gmail.com>: Re: Conterfeit parts guidance
130966: 08/04/07: Craig: Re: Conterfeit parts guidance
131025: 08/04/08: jon: Re: Conterfeit parts guidance
130834: 08/04/03: Antti: EDK 10.1 first impressions
130835: 08/04/03: Antti: Re: EDK 10.1 first impressions
130841: 08/04/03: Patrick Dubois: Re: EDK 10.1 first impressions
130853: 08/04/03: Andy Peters: Re: EDK 10.1 first impressions
130900: 08/04/04: Ed McGettigan: Re: EDK 10.1 first impressions
130862: 08/04/03: Antti: Re: EDK 10.1 first impressions
130914: 08/04/04: Kolja Sulimma: Re: EDK 10.1 first impressions
130836: 08/04/03: maverick: Protecting design from being downloaded on other (similar) FPGA
130837: 08/04/03: Antti: Re: Protecting design from being downloaded on other (similar) FPGA
130839: 08/04/03: austin: Re: Protecting design from being downloaded on other (similar) FPGA
130855: 08/04/03: John McCaskill: Re: Protecting design from being downloaded on other (similar) FPGA
130865: 08/04/03: MM: Re: Protecting design from being downloaded on other (similar) FPGA devices
130889: 08/04/04: Krzysztof Kepa: Re: Protecting design from being downloaded on other (similar) FPGA devices
130954: 08/04/06: MM: Re: Protecting design from being downloaded on other (similar) FPGA devices
130880: 08/04/04: maverick: Re: Protecting design from being downloaded on other (similar) FPGA
130881: 08/04/04: Antti: Re: Protecting design from being downloaded on other (similar) FPGA
130882: 08/04/04: Antti: Re: Protecting design from being downloaded on other (similar) FPGA
130932: 08/04/05: Bob Smith: Re: Protecting design from being downloaded on other (similar) FPGA
130993: 08/04/08: Andreas Ehliar: Re: Protecting design from being downloaded on other (similar) FPGA devices
130933: 08/04/05: Antti: Re: Protecting design from being downloaded on other (similar) FPGA
130936: 08/04/05: Alan Nishioka: Re: Protecting design from being downloaded on other (similar) FPGA
130843: 08/04/03: <g.drozdzowski@gmail.com>: Beginner's silly question about ICAP
130844: 08/04/03: austin: Re: Beginner's silly question about ICAP
130847: 08/04/03: Jens Hagemeyer: Re: Beginner's silly question about ICAP
130878: 08/04/04: <g.drozdzowski@gmail.com>: Re: Beginner's silly question about ICAP
130850: 08/04/03: <cpandya@yahoo.com>: Spartan3 JTAG flash In System Programming over Ethernet
130947: 08/04/06: Petter Gustad: Re: Spartan3 JTAG flash In System Programming over Ethernet
130975: 08/04/07: Fei Liu: Re: Spartan3 JTAG flash In System Programming over Ethernet
130983: 08/04/07: Nico Coesel: Re: Spartan3 JTAG flash In System Programming over Ethernet
131064: 08/04/09: <cs_posting@hotmail.com>: Re: Spartan3 JTAG flash In System Programming over Ethernet
130852: 08/04/03: Bubba: No synchronization word in prom file (XILINX)?
130874: 08/04/04: Bubba: Re: No synchronization word in prom file (XILINX)?
130877: 08/04/04: Bubba: Re: No synchronization word in prom file (XILINX)?
130867: 08/04/03: ni: synplify pro generates negative slack
130886: 08/04/04: Ben Jones: Re: synplify pro generates negative slack
130901: 08/04/04: Kevin Neilson: Re: synplify pro generates negative slack
130904: 08/04/04: Mike Treseler: Re: synplify pro generates negative slack
130930: 08/04/05: Mike Treseler: Re: synplify pro generates negative slack
130896: 08/04/04: ni: Re: synplify pro generates negative slack
130913: 08/04/04: ni: Re: synplify pro generates negative slack
130868: 08/04/03: Fei Liu: problem with synthesis
130871: 08/04/04: Muzaffer Kal: Re: problem with synthesis
130872: 08/04/03: <climber.tim@gmail.com>: Downloading some data from flash memory thru JTAG.
130885: 08/04/04: archana: loop back on a MARVELL switch
130890: 08/04/04: zlyh: One more question. WebPACK key with ISE
130891: 08/04/04: Andy Peters: Re: One more question. WebPACK key with ISE
130892: 08/04/04: <sky465nm@trline4.org>: Xilinx FPGA + SMPS
130895: 08/04/04: Symon: Re: Xilinx FPGA + SMPS
130902: 08/04/04: MM: Re: Xilinx FPGA + SMPS
130899: 08/04/04: austin: Re: Xilinx FPGA + SMPS
130908: 08/04/04: Nico Coesel: Re: Xilinx FPGA + SMPS
130910: 08/04/05: Jim Granville: Re: Xilinx FPGA + SMPS
130911: 08/04/05: Allan Herriman: Re: Xilinx FPGA + SMPS
130918: 08/04/04: austin: Re: Xilinx FPGA + SMPS
130917: 08/04/04: austin: Re: Xilinx FPGA + SMPS
130906: 08/04/04: Brad Smallridge: Xilinx inferred FIFOs
130919: 08/04/04: austin: Re: Xilinx inferred FIFOs
130946: 08/04/06: Brad Smallridge: Re: Xilinx inferred FIFOs
130948: 08/04/06: austin: Re: Xilinx inferred FIFOs
130949: 08/04/06: Frank Buss: Re: Xilinx inferred FIFOs
130950: 08/04/07: Jim Granville: Re: Xilinx inferred FIFOs
130958: 08/04/07: Frank Buss: Re: Xilinx inferred FIFOs
130987: 08/04/07: Eric Smith: Re: Xilinx inferred FIFOs
130971: 08/04/07: Kevin Neilson: Re: Xilinx inferred FIFOs
130951: 08/04/06: Peter Alfke: Re: Xilinx inferred FIFOs
130920: 08/04/04: Ankit: Project Ideas
130922: 08/04/05: Frank Buss: Re: Project Ideas
130923: 08/04/05: Joseph: PLA datasheet - PLS161
130926: 08/04/05: Jim Granville: Re: PLA datasheet - PLS161
130927: 08/04/05: Jim Granville: Re: PLA datasheet - PLS161
130937: 08/04/05: Fei Liu: problem with synthesis of a state machine
130938: 08/04/05: Fei Liu: Re: problem with synthesis of a state machine
130939: 08/04/05: glen herrmannsfeldt: Re: problem with synthesis of a state machine
130940: 08/04/05: Muzaffer Kal: Re: problem with synthesis of a state machine
130942: 08/04/05: Muzaffer Kal: Re: problem with synthesis of a state machine
130941: 08/04/05: Fei Liu: Re: problem with synthesis of a state machine
130944: 08/04/06: nivesh: Use of floating point numbers in xilinx EDK .........
130952: 08/04/06: Andy: Re: Use of floating point numbers in xilinx EDK .........
130945: 08/04/06: Jaime Andres Aranguren Cardona: Re: Examples for Spartan3 StarterKit
130953: 08/04/06: Karl: system level language: why all this fuss about
130960: 08/04/07: Kolja Sulimma: Re: system level language: why all this fuss about
130963: 08/04/07: HT-Lab: Re: system level language: why all this fuss about
130961: 08/04/07: Jon Beniston: Re: system level language: why all this fuss about
130962: 08/04/07: Kolja Sulimma: Re: system level language: why all this fuss about
130979: 08/04/07: Kevin Neilson: Re: system level language: why all this fuss about
130982: 08/04/07: Andy Peters: Re: system level language: why all this fuss about
130984: 08/04/07: Uwe Bonnes: Re: system level language: why all this fuss about
130986: 08/04/07: Kevin Neilson: Re: system level language: why all this fuss about
131091: 08/04/10: Colin Paul Gloster: Re: system level language: why all this fuss about
130957: 08/04/06: Antti: Xilinx xilfatfs and systemACE speed issue
130978: 08/04/07: morphiend: Re: Xilinx xilfatfs and systemACE speed issue
130980: 08/04/07: Antti: Re: Xilinx xilfatfs and systemACE speed issue
130996: 08/04/08: Antti: Re: Xilinx xilfatfs and systemACE speed issue
131895: 08/05/06: UETIAN: Re: Xilinx xilfatfs and systemACE speed issue
130967: 08/04/07: grant0920: FPGA configuration mode on ML310
130968: 08/04/07: Antti: Re: FPGA configuration mode on ML310
130969: 08/04/07: grant0920: Re: FPGA configuration mode on ML310
130990: 08/04/07: Ed McGettigan: Re: FPGA configuration mode on ML310
131053: 08/04/08: grant0920: Re: FPGA configuration mode on ML310
130981: 08/04/07: radarman: Modify POF with new ESB (ROM) content?
130995: 08/04/08: Antti: Re: Modify POF with new ESB (ROM) content?
130999: 08/04/08: Petter Gustad: Re: Modify POF with new ESB (ROM) content?
131005: 08/04/08: Petter Gustad: Re: Modify POF with new ESB (ROM) content?
131014: 08/04/08: Petter Gustad: Re: Modify POF with new ESB (ROM) content?
131022: 08/04/08: Petter Gustad: Re: Modify POF with new ESB (ROM) content?
131040: 08/04/08: Petter Gustad: Re: Modify POF with new ESB (ROM) content?
131031: 08/04/09: Jim Granville: Re: Modify POF with new ESB (ROM) content?
131043: 08/04/08: Uwe Bonnes: Re: Modify POF with new ESB (ROM) content?
131055: 08/04/09: Andreas Ehliar: Re: Modify POF with new ESB (ROM) content?
131060: 08/04/09: Petter Gustad: Re: Modify POF with new ESB (ROM) content?
131056: 08/04/09: Brian Drummond: Re: Modify POF with new ESB (ROM) content?
131000: 08/04/08: Antti: Re: Modify POF with new ESB (ROM) content?
131006: 08/04/08: Antti: Re: Modify POF with new ESB (ROM) content?
131016: 08/04/08: Antti: Re: Modify POF with new ESB (ROM) content?
131024: 08/04/08: Antti: Re: Modify POF with new ESB (ROM) content?
131041: 08/04/08: <cs_posting@hotmail.com>: Re: Modify POF with new ESB (ROM) content?
130991: 08/04/07: benn: Avalon Bus <-> Wishbone Bus
130992: 08/04/08: KJ: Re: Avalon Bus <-> Wishbone Bus
130994: 08/04/08: Mark McDougall: Re: Avalon Bus <-> Wishbone Bus
131017: 08/04/08: <ghelbig@lycos.com>: Re: Avalon Bus <-> Wishbone Bus
130997: 08/04/08: xenix: MIG/Corgen to XPS core insertion
130998: 08/04/08: xenix: Re: MIG/Corgen to XPS core insertion
131085: 08/04/09: xenix: Re: MIG/Corgen to XPS core insertion
131172: 08/04/14: xenix: Re: MIG/Corgen to XPS core insertion
131001: 08/04/08: <jamicrotech@gmail.com>: OBUF gate delay
131004: 08/04/08: Symon: Re: OBUF gate delay
131010: 08/04/08: Symon: Re: OBUF gate delay
131007: 08/04/08: John_H: Re: OBUF gate delay
131002: 08/04/08: LC: NoisII or else.
131003: 08/04/08: <=?ISO-8859-1?Q?G=F3rski_Adam?=>: Re: NoisII or else.
131009: 08/04/08: LC: Re: NoisII or else.
131012: 08/04/08: <=?ISO-8859-1?Q?G=F3rski_Adam?=>: Re: NoisII or else.
131057: 08/04/09: LC: Re: NoisII or else.
131011: 08/04/08: David Spencer: Re: NoisII or else.
131058: 08/04/09: LC: Re: NoisII or else.
131059: 08/04/09: <=?ISO-8859-1?Q?G=F3rski_Adam?=>: Re: NoisII or else.
131062: 08/04/09: LC: Re: NoisII or else.
131008: 08/04/08: Symon: Intel plans to tackle cosmic ray threat
131013: 08/04/08: austin: Re: Intel plans to tackle cosmic ray threat (actually they have been
131015: 08/04/08: Symon: Re: Intel plans to tackle cosmic ray threat (actually they have been working on it for at least five years...austin)
131019: 08/04/08: austin: Re: Intel plans to tackle cosmic ray threat (actually they have been
131020: 08/04/08: austin: Re: Intel plans to tackle cosmic ray threat (actually they have been
131099: 08/04/10: austin: Re: Intel plans to tackle cosmic ray threat (actually they have been
131032: 08/04/08: Jon Elson: Re: Intel plans to tackle cosmic ray threat (actually they have been
131018: 08/04/08: austin: Re: Intel plans to tackle cosmic ray threat (actually they have been
131021: 08/04/08: Symon: Re: Intel plans to tackle cosmic ray threat (actually they have been working on it for at least five years...austin)
131023: 08/04/08: austin: Re: Intel plans to tackle cosmic ray threat (actually they have been
131029: 08/04/08: Symon: Re: Intel plans to tackle cosmic ray threat (actually they have been working on it for at least five years...austin)
131035: 08/04/08: Jon Elson: Re: Intel plans to tackle cosmic ray threat (actually they have been
131038: 08/04/08: austin: Re: Intel plans to tackle cosmic ray threat (actually they have been
131186: 08/04/14: Symon: Re: Intel plans to tackle cosmic ray threat (actually they have been working on it for at least five years...austin)
131192: 08/04/15: Marty Ryba: Re: Intel plans to tackle cosmic ray threat (actually they have been working on it for at least five years...austin)
131030: 08/04/09: Jim Granville: Re: Intel plans to tackle cosmic ray threat (actually they have beenworking
131033: 08/04/08: Jon Elson: Re: Intel plans to tackle cosmic ray threat (actually they have been
131100: 08/04/10: austin: Re: Intel plans to tackle cosmic ray threat (actually they have been
131089: 08/04/10: Colin Paul Gloster: Re: Intel plans to tackle cosmic ray threat (actually they have been
131090: 08/04/10: Colin Paul Gloster: Re: Intel plans to tackle cosmic ray threat (actually they have been
131125: 08/04/11: Colin Paul Gloster: Re: Intel plans to tackle cosmic ray threat (actually they have been
131126: 08/04/11: austin: Space - Xilinx Frontier?
131183: 08/04/14: <cs_posting@hotmail.com>: Re: Intel plans to tackle cosmic ray threat (actually they have been
131298: 08/04/18: Colin Paul Gloster: Re: Intel plans to tackle cosmic ray threat (actually they have been
131069: 08/04/09: austin: Re: Intel plans to tackle cosmic ray threat
131026: 08/04/08: jjlindula@hotmail.com: Starting a PCI Express Application
131027: 08/04/08: <sky465nm@trline4.org>: Re: Starting a PCI Express Application
131122: 08/04/11: Bernard Esteban: Re: Starting a PCI Express Application
131028: 08/04/08: VIPS: 32 bit multiplier
131034: 08/04/08: Alvin Andries: Re: 32 bit multiplier
131036: 08/04/08: Tim (one of many): Re: 32 bit multiplier
131037: 08/04/08: Symon: Re: 32 bit multiplier
131042: 08/04/08: Ray Andraka: Re: 32 bit multiplier
131044: 08/04/08: Uwe Bonnes: Re: 32 bit multiplier
131048: 08/04/09: Jim Granville: Re: 32 bit multiplier
131046: 08/04/08: Peter Alfke: Re: 32 bit multiplier
131084: 08/04/10: Jim Granville: Re: 32 bit multiplier
131094: 08/04/10: Kolja Sulimma: Re: 32 bit multiplier
131045: 08/04/08: Franck Y: Disable optimisation - Ring oscillator
131047: 08/04/08: Uwe Bonnes: Re: Disable optimisation - Ring oscillator
131054: 08/04/09: Uwe Bonnes: Re: Disable optimisation - Ring oscillator
131049: 08/04/09: Jim Granville: Re: Disable optimisation - Ring oscillator
131050: 08/04/08: Franck Y: Re: Disable optimisation - Ring oscillator
131051: 08/04/08: Franck Y: Re: Disable optimisation - Ring oscillator
131063: 08/04/09: radarman: Re: Disable optimisation - Ring oscillator
131087: 08/04/10: Kolja Sulimma: Re: Disable optimisation - Ring oscillator
131052: 08/04/08: Fei Liu: looking for critique for a spartan3a lcd controller verilog module
131103: 08/04/10: Fei Liu: Re: looking for critique for a spartan3a lcd controller verilog module
131061: 08/04/09: FPGA: Task in verilog
131167: 08/04/14: <sky465nm@trline4.org>: Re: Task in verilog
131170: 08/04/14: Tricky: Re: Task in verilog
131065: 08/04/09: Habib Bouaziz-Viallet: Xilinx CPLD programming tool under Linux
131066: 08/04/09: DJ Delorie: Re: Xilinx CPLD programming tool under Linux
131072: 08/04/09: Uwe Bonnes: Re: Xilinx CPLD programming tool under Linux
131088: 08/04/10: Uwe Bonnes: Re: Xilinx CPLD programming tool under Linux
131101: 08/04/10: Eric Smith: Re: Xilinx CPLD programming tool under Linux
131068: 08/04/09: Habib Bouaziz-Viallet: Re: Xilinx CPLD programming tool under Linux
131086: 08/04/10: Habib Bouaziz-Viallet: Re: Xilinx CPLD programming tool under Linux
131093: 08/04/10: Habib Bouaziz-Viallet: Re: Xilinx CPLD programming tool under Linux
131071: 08/04/09: Pete: Xilinx FFT C-sim model
131081: 08/04/10: Marty Ryba: Re: Xilinx FFT C-sim model
131123: 08/04/11: Patrick Dubois: Re: Xilinx FFT C-sim model
131077: 08/04/09: Wojciech Zabolotny: Specifying strict setup constraint in ISE
131078: 08/04/09: Peter Alfke: Re: Specifying strict setup constraint in ISE
131080: 08/04/09: John_H: Re: Specifying strict setup constraint in ISE
131092: 08/04/10: Gabor: Re: Specifying strict setup constraint in ISE
131095: 08/04/10: Symon: Re: Specifying strict setup constraint in ISE
131096: 08/04/10: Symon: Re: clock instanciation
131097: 08/04/10: Mike Treseler: Re: clock instanciation
131098: 08/04/10: Symon: Re: clock instanciation
131104: 08/04/10: water9580@yahoo.com: why to trigger a NMI error after just receiving 35 pakcets?
131107: 08/04/11: RCIngham: Re: why to trigger a NMI error after just receiving 35 pakcets?
131105: 08/04/10: makhan: Probelms simulating Xilinx FFT version 3.2 core in ModelSim SE
131115: 08/04/11: makhan: Re: Probelms simulating Xilinx FFT version 3.2 core in ModelSim SE
131116: 08/04/11: sprocket: Re: Probelms simulating Xilinx FFT version 3.2 core in ModelSim SE
131106: 08/04/11: Jonathan Bromley: Re: Split register in smaller segments
131110: 08/04/11: Jonathan Bromley: Re: Split register in smaller segments
131112: 08/04/11: Jonathan Bromley: Re: Split register in smaller segments
131114: 08/04/11: Michael Meeuwisse: Re: Split register in smaller segments
131111: 08/04/11: Michael Meeuwisse: Re: Split register in smaller segments
131108: 08/04/11: <giorgos.puiklis@gmail.com>: Xilinx ISE synthesis error (error:3524 Unexpected end of line.)
131109: 08/04/11: Michael Meeuwisse: Split register in smaller segments
131113: 08/04/11: Lars: Xilinx tech Xclusive
131117: 08/04/11: Symon: Re: Xilinx tech Xclusive
131124: 08/04/11: austin: Re: Xilinx tech Xclusive
131135: 08/04/12: Jim Granville: Re: Xilinx tech Xclusive
131137: 08/04/12: Symon: Re: Xilinx tech Xclusive
131139: 08/04/12: Jim Granville: Re: Xilinx tech Xclusive
131191: 08/04/14: Eric Smith: Re: Xilinx tech Xclusive
131118: 08/04/11: Lars: Re: Xilinx tech Xclusive
131120: 08/04/11: Lars: Re: Xilinx tech Xclusive
131121: 08/04/11: Marlboro: Re: Xilinx tech Xclusive
131131: 08/04/11: AugustoEinsfeldt: Re: Xilinx tech Xclusive
131136: 08/04/11: Peter Alfke: Re: Xilinx tech Xclusive
131165: 08/04/13: Lars: Re: Xilinx tech Xclusive
131119: 08/04/11: Roger: 64 bit WebPack
131127: 08/04/11: Eric Smith: Re: 64 bit WebPack
131166: 08/04/14: David Brown: Re: 64 bit WebPack
131189: 08/04/14: <steve.lass@xilinx.com>: Re: 64 bit WebPack
131195: 08/04/15: David Brown: Re: 64 bit WebPack
131190: 08/04/14: Eric Smith: Re: 64 bit WebPack
131199: 08/04/15: Roger: Re: 64 bit WebPack
131223: 08/04/15: Gavin Scott: Re: 64 bit WebPack
131226: 08/04/15: Eric Smith: Re: 64 bit WebPack
131233: 08/04/16: Roger: Re: 64 bit WebPack
131128: 08/04/11: FP: case statements- verilog to vhdl
131129: 08/04/11: jens: Re: case statements- verilog to vhdl
131130: 08/04/11: Dave Pollum: Re: case statements- verilog to vhdl
131182: 08/04/14: Mike Treseler: Re: case statements- verilog to vhdl
131188: 08/04/14: Mike Treseler: Re: case statements- verilog to vhdl
131133: 08/04/11: Andy: Re: case statements- verilog to vhdl
131180: 08/04/14: FP: Re: case statements- verilog to vhdl
131187: 08/04/14: FP: Re: case statements- verilog to vhdl
131132: 08/04/11: u_stadler@yahoo.de: Virtex4 FX PPC and Fsl
131653: 08/04/28: <damak.taheni@gmail.com>: Re: Virtex4 FX PPC and Fsl
131134: 08/04/11: Fei Liu: high noise/signal in a simple serial to mono dac module
131138: 08/04/11: kevin93: Re: high noise/signal in a simple serial to mono dac module
131140: 08/04/11: Fei Liu: Re: high noise/signal in a simple serial to mono dac module
131141: 08/04/11: Alan Nishioka: Re: high noise/signal in a simple serial to mono dac module
131150: 08/04/13: Fei Liu: Re: high noise/signal in a simple serial to mono dac module
131152: 08/04/12: John_H: Re: high noise/signal in a simple serial to mono dac module
131153: 08/04/13: Fei Liu: Re: high noise/signal in a simple serial to mono dac module
131142: 08/04/12: LC: Need help on UNISIM.Vcomponents.all
131143: 08/04/12: Arlet Ottens: Re: Need help on UNISIM.Vcomponents.all
131168: 08/04/14: LC: Re: Need help on UNISIM.Vcomponents.all
131145: 08/04/12: vladitx: Re: Need help on UNISIM.Vcomponents.all
131169: 08/04/14: LC: Re: Need help on UNISIM.Vcomponents.all
131144: 08/04/12: Antti: CF (systemace) SD card, etc performance
131154: 08/04/13: Antti: Re: CF (systemace) SD card, etc performance
131146: 08/04/12: KJ: Re: simple example with timing problems
131147: 08/04/12: kislo: Spartan3E startup problems
131148: 08/04/12: kislo: Re: Spartan3E startup problems
131151: 08/04/13: <sky465nm@trline4.org>: Re: Spartan3E startup problems
131157: 08/04/13: kislo: Re: Spartan3E startup problems
131158: 08/04/13: kislo: Re: Spartan3E startup problems
131163: 08/04/13: Moazzam: Re: Spartan3E startup problems
131149: 08/04/12: Michael Trim: Re: ISE 9.2 and Windriver
131159: 08/04/13: Michael: Question about Spartan 3E starter kit
131160: 08/04/13: Symon: Re: Question about Spartan 3E starter kit
131161: 08/04/13: Michael: Re: Question about Spartan 3E starter kit
131162: 08/04/13: pdudley1@comcast.net: HiTech Global Eval boards?
131203: 08/04/15: morphiend: Re: HiTech Global Eval boards?
131164: 08/04/13: Goli: XST support for User Defined Primitives
131173: 08/04/14: Brian Drummond: Re: XST support for User Defined Primitives
131177: 08/04/14: mk: Re: XST support for User Defined Primitives
131171: 08/04/14: kislo: Chipscope 9.2 in XPS
131174: 08/04/14: Michael: Which to learn: Verilog vs. VHDL?
131175: 08/04/14: Mike Treseler: Re: Which to learn: Verilog vs. VHDL?
131196: 08/04/15: RCIngham: Re: Which to learn: Verilog vs. VHDL?
131322: 08/04/18: Jim Lewis: Re: Which to learn: Verilog vs. VHDL?
131205: 08/04/15: Kevin Neilson: Re: Which to learn: Verilog vs. VHDL?
131219: 08/04/15: HT-Lab: Re: Which to learn: Verilog vs. VHDL?
131227: 08/04/15: Eric Smith: Re: Which to learn: Verilog vs. VHDL?
131214: 08/04/15: Fei Liu: Re: Which to learn: Verilog vs. VHDL?
131236: 08/04/16: Brian Drummond: Re: Which to learn: Verilog vs. VHDL?
131224: 08/04/15: lm317t: Re: Which to learn: Verilog vs. VHDL?
131228: 08/04/15: Eric Smith: Re: Which to learn: Verilog vs. VHDL?
154743: 13/01/03: glen herrmannsfeldt: Re: Which to learn: Verilog vs. VHDL?
154745: 13/01/03: glen herrmannsfeldt: Re: Which to learn: Verilog vs. VHDL?
154749: 13/01/04: Rui Maciel: Re: Which to learn: Verilog vs. VHDL?
154750: 13/01/04: David Brown: Re: Which to learn: Verilog vs. VHDL?
154752: 13/01/04: Rui Maciel: Re: Which to learn: Verilog vs. VHDL?
154756: 13/01/04: David Brown: Re: Which to learn: Verilog vs. VHDL?
154761: 13/01/04: glen herrmannsfeldt: Re: Which to learn: Verilog vs. VHDL?
154775: 13/01/07: David Brown: Re: Which to learn: Verilog vs. VHDL?
131229: 08/04/15: lm317t: Re: Which to learn: Verilog vs. VHDL?
131323: 08/04/18: Jim Lewis: Re: Which to learn: Verilog vs. VHDL?
154712: 12/12/28: <joey899244@yahoo.cn>: Re: Which to learn: Verilog vs. VHDL?
154716: 12/12/28: rickman: Re: Which to learn: Verilog vs. VHDL?
154720: 12/12/29: glen herrmannsfeldt: Re: Which to learn: Verilog vs. VHDL?
154725: 12/12/29: Nicolas Matringe: Re: Which to learn: Verilog vs. VHDL?
154722: 12/12/28: rickman: Re: Which to learn: Verilog vs. VHDL?
154732: 12/12/31: Andrew Holme: Re: Which to learn: Verilog vs. VHDL?
154717: 12/12/28: glen herrmannsfeldt: Re: Which to learn: Verilog vs. VHDL?
154718: 12/12/28: Tim Wescott: Re: Which to learn: Verilog vs. VHDL?
154728: 12/12/29: Michael S: Re: Which to learn: Verilog vs. VHDL?
154733: 12/12/31: Brian Drummond: Re: Which to learn: Verilog vs. VHDL?
154737: 13/01/02: Rob Gaddi: Re: Which to learn: Verilog vs. VHDL?
154740: 13/01/03: <4rt.dw8.5t4wr@gmail.com>: Re: Which to learn: Verilog vs. VHDL?
154741: 13/01/03: <4rt.dw8.5t4wr@gmail.com>: Re: Which to learn: Verilog vs. VHDL?
154742: 13/01/03: Rob Gaddi: Re: Which to learn: Verilog vs. VHDL?
154744: 13/01/03: Tim Wescott: Re: Which to learn: Verilog vs. VHDL?
154747: 13/01/03: Brian Drummond: Re: Which to learn: Verilog vs. VHDL?
154748: 13/01/04: Brian Drummond: Re: Which to learn: Verilog vs. VHDL?
154759: 13/01/04: Tim Wescott: Re: Which to learn: Verilog vs. VHDL?
154779: 13/01/07: <jonesandy@comcast.net>: Re: Which to learn: Verilog vs. VHDL?
154780: 13/01/08: Brian Drummond: Re: Which to learn: Verilog vs. VHDL?
154785: 13/01/09: Michael S: Re: Which to learn: Verilog vs. VHDL?
154786: 13/01/10: Brian Drummond: Re: Which to learn: Verilog vs. VHDL?
154787: 13/01/10: Michael S: Re: Which to learn: Verilog vs. VHDL?
154788: 13/01/10: Brian Drummond: Re: Which to learn: Verilog vs. VHDL?
154790: 13/01/10: Michael S: Re: Which to learn: Verilog vs. VHDL?
154794: 13/01/11: Brian Drummond: Re: Which to learn: Verilog vs. VHDL?
154795: 13/01/10: Rob Gaddi: Re: Which to learn: Verilog vs. VHDL?
154796: 13/01/10: Michael S: Re: Which to learn: Verilog vs. VHDL?
131176: 08/04/14: John Aderseen: Actel Cortex
131181: 08/04/14: <job@amontec.com>: Re: Actel Cortex
131178: 08/04/14: Sue: DOS script file to synthesize a VHDL design
131194: 08/04/15: HT-Lab: Re: DOS script file to synthesize a VHDL design
131197: 08/04/15: Brian Drummond: Re: DOS script file to synthesize a VHDL design
131216: 08/04/15: Alain: Re: DOS script file to synthesize a VHDL design
131179: 08/04/14: NRClark: "Multi-source in Unit" Verilog synthesis woes
131184: 08/04/14: Alvin Andries: Re: "Multi-source in Unit" Verilog synthesis woes
131185: 08/04/14: Gabor: Re: "Multi-source in Unit" Verilog synthesis woes
131193: 08/04/15: Habib Bouaziz-Viallet: Xilinx JTAG Linux programming
131198: 08/04/15: Michael: Simulation tools for Xilinx ISE
131201: 08/04/15: <ghelbig@lycos.com>: Re: Simulation tools for Xilinx ISE
131207: 08/04/15: Kevin Neilson: Re: Simulation tools for Xilinx ISE
131210: 08/04/15: HT-Lab: Re: Simulation tools for Xilinx ISE
131213: 08/04/15: Kevin Neilson: Re: Simulation tools for Xilinx ISE
131241: 08/04/16: Kevin Neilson: Re: Simulation tools for Xilinx ISE
131218: 08/04/15: HT-Lab: Re: Simulation tools for Xilinx ISE
131304: 08/04/18: Nico Coesel: Re: Simulation tools for Xilinx ISE
131208: 08/04/15: Michael: Re: Simulation tools for Xilinx ISE
131212: 08/04/15: Michael: Re: Simulation tools for Xilinx ISE
131215: 08/04/15: Michael: Re: Simulation tools for Xilinx ISE
131225: 08/04/15: lm317t: Re: Simulation tools for Xilinx ISE
131271: 08/04/17: Chumnarn P.: Re: Simulation tools for Xilinx ISE
131282: 08/04/17: Michael: Re: Simulation tools for Xilinx ISE
131200: 08/04/15: <robquigley@gmail.com>: Pre and Post Synthesis Simulation mismatch
131202: 08/04/15: John_H: Re: Pre and Post Synthesis Simulation mismatch
131211: 08/04/15: Muzaffer Kal: Re: Pre and Post Synthesis Simulation mismatch
131204: 08/04/15: John_H: Re: Snythesis error
131206: 08/04/15: Kevin Neilson: Re: Snythesis error
131220: 08/04/15: Mike Treseler: Re: Snythesis error
131239: 08/04/16: Mike Treseler: Re: Snythesis error
131230: 08/04/15: Thomas Stanka: Re: Snythesis error
131247: 08/04/16: Andy: Re: Snythesis error
131209: 08/04/15: Andy Peters: Re: Snythesis error
131217: 08/04/15: Bathala: Inconsistent File Reading/writing in binary format using MicroBlaze
131221: 08/04/15: vijayant.rutgers@gmail.com: asic gate count
131222: 08/04/15: Mike Treseler: Re: asic gate count
131240: 08/04/16: <ghelbig@lycos.com>: Re: asic gate count
131249: 08/04/17: Muzaffer Kal: Re: asic gate count
131753: 08/04/30: Mike Treseler: Re: asic gate count
131790: 08/05/02: RCIngham: Re: asic gate count
131752: 08/04/30: Vijayant: Re: asic gate count
131766: 08/05/01: vijayant.rutgers@gmail.com: Re: asic gate count
131787: 08/05/01: Thomas Stanka: Re: asic gate count
131847: 08/05/03: vijayant.rutgers@gmail.com: Re: asic gate count
131231: 08/04/16: <ajin1983@gmail.com>: Help Need about reconfiguring the PLL with prescale counter n and
131232: 08/04/16: Nemesis: Virtex 4 DCM problem
131234: 08/04/16: Martin Thompson: Re: Virtex 4 DCM problem
131250: 08/04/17: Martin Thompson: Re: Virtex 4 DCM problem
131235: 08/04/16: Nemesis: Re: Virtex 4 DCM problem
131238: 08/04/16: Nemesis: Re: Virtex 4 DCM problem
131297: 08/04/18: Nemesis: Re: Virtex 4 DCM problem
131340: 08/04/20: adi: Re: Virtex 4 DCM problem
131237: 08/04/16: bjzhangwn@gmail.com: 91c111 drivers for NIOSII without ucosII/lwip stack
131242: 08/04/16: ni: chipscope pro , lower level signals not visible
131248: 08/04/16: Patrick Dubois: Re: chipscope pro , lower level signals not visible
131243: 08/04/16: rha_x: ICAP_VIRTEX4 primitive
131280: 08/04/17: Erik Anderson: Re: ICAP_VIRTEX4 primitive
131244: 08/04/17: argee: Wishbone, TSK3000 and endianness problem
131245: 08/04/16: Dan K: how do I test signals in a testbench that are 1 or 2 levels down in the UUT?
131246: 08/04/16: Mike Treseler: Re: how do I test signals in a testbench that are 1 or 2 levels down
131252: 08/04/17: RCIngham: Re: how do I test signals in a testbench that are 1 or 2 levels down in the UUT?
131256: 08/04/17: HT-Lab: Re: how do I test signals in a testbench that are 1 or 2 levels down in the UUT?
131278: 08/04/17: Duane Clark: Re: how do I test signals in a testbench that are 1 or 2 levels down
131279: 08/04/17: HT-Lab: Re: how do I test signals in a testbench that are 1 or 2 levels down in the UUT?
131260: 08/04/17: KJ: Re: how do I test signals in a testbench that are 1 or 2 levels down
131262: 08/04/17: Andy: Re: how do I test signals in a testbench that are 1 or 2 levels down
131251: 08/04/17: Mark: Help, router can't rout all connections (XILINX)
131253: 08/04/17: Symon: Re: Help, router can't rout all connections (XILINX)
131255: 08/04/17: Mark: Re: Help, router can't rout all connections (XILINX)
131259: 08/04/17: Brian Drummond: Re: Help, router can't rout all connections (XILINX)
131254: 08/04/17: HT-Lab: Re: Help, router can't rout all connections (XILINX)
131257: 08/04/17: Mark: Re: Help, router can't rout all connections (XILINX)
131258: 08/04/17: Mark: Re: Help, router can't rout all connections (XILINX)
131263: 08/04/17: <myx2@gmx.de>: DMA in PLB custom core (XilinxV4)
131264: 08/04/17: <chrisdekoh@gmail.com>: attached a 2nd peripheral to FSL bus. how to use it in software?
131286: 08/04/17: u_stadler@yahoo.de: Re: attached a 2nd peripheral to FSL bus. how to use it in software?
131309: 08/04/18: <chrisdekoh@gmail.com>: Re: attached a 2nd peripheral to FSL bus. how to use it in software?
131393: 08/04/21: Göran Bilski: Re: attached a 2nd peripheral to FSL bus. how to use it in software?
131454: 08/04/21: <chrisdekoh@gmail.com>: Re: attached a 2nd peripheral to FSL bus. how to use it in software?
131265: 08/04/17: Dave: Survey: FPGA PCB layout
131268: 08/04/17: Mike Treseler: Re: Survey: FPGA PCB layout
131269: 08/04/17: qrk: Re: Survey: FPGA PCB layout
131272: 08/04/17: Joerg: Re: Survey: FPGA PCB layout
131274: 08/04/17: Symon: Re: Survey: FPGA PCB layout
131284: 08/04/17: Steve: Re: Survey: FPGA PCB layout
131287: 08/04/17: Jeff Cunningham: Re: Survey: FPGA PCB layout
131289: 08/04/17: Joel Koltner: Re: Survey: FPGA PCB layout
131290: 08/04/17: Joerg: Re: Survey: FPGA PCB layout
131291: 08/04/17: Joel Koltner: Re: Survey: FPGA PCB layout
131292: 08/04/18: Joerg: Re: Survey: FPGA PCB layout
131295: 08/04/18: Andy Botterill: Re: Survey: FPGA PCB layout
131303: 08/04/18: Joel Koltner: Re: Survey: FPGA PCB layout
131306: 08/04/18: Joerg: Re: Survey: FPGA PCB layout
131308: 08/04/18: Chuck Harris: Re: Survey: FPGA PCB layout
131311: 08/04/18: Joerg: Re: Survey: FPGA PCB layout
131313: 08/04/18: Joel Koltner: Re: Survey: FPGA PCB layout
131315: 08/04/18: Joerg: Re: Survey: FPGA PCB layout
131316: 08/04/18: Joel Koltner: Re: Survey: FPGA PCB layout
131317: 08/04/18: Joerg: Re: Survey: FPGA PCB layout
131318: 08/04/18: Joel Koltner: Re: Survey: FPGA PCB layout
131330: 08/04/19: Joerg: Re: Survey: FPGA PCB layout
131334: 08/04/19: krw: Re: Survey: FPGA PCB layout
131335: 08/04/20: Joerg: Re: Survey: FPGA PCB layout
131337: 08/04/19: krw: Re: Survey: FPGA PCB layout
131552: 08/04/25: JosephKK: Re: Survey: FPGA PCB layout
131551: 08/04/24: JosephKK: Re: Survey: FPGA PCB layout
131575: 08/04/25: Joerg: Re: Survey: FPGA PCB layout
131602: 08/04/25: krw: Re: Survey: FPGA PCB layout
131606: 08/04/25: Joerg: Re: Survey: FPGA PCB layout
131625: 08/04/26: krw: Re: Survey: FPGA PCB layout
131627: 08/04/26: Michael A. Terrell: Re: Survey: FPGA PCB layout
131427: 08/04/21: Joel Koltner: Re: Survey: FPGA PCB layout
131433: 08/04/21: Joerg: Re: Survey: FPGA PCB layout
131437: 08/04/21: Joel Koltner: Re: Survey: FPGA PCB layout
131555: 08/04/24: JosephKK: Re: Survey: FPGA PCB layout
131445: 08/04/21: John Larkin: Re: Survey: FPGA PCB layout
131446: 08/04/21: Joerg: Re: Survey: FPGA PCB layout
131553: 08/04/24: JosephKK: Re: Survey: FPGA PCB layout
131560: 08/04/25: Joerg: Re: Survey: FPGA PCB layout
131632: 08/04/27: JosephKK: Re: Survey: FPGA PCB layout
131639: 08/04/27: Joerg: Re: Survey: FPGA PCB layout
131550: 08/04/24: JosephKK: Re: Survey: FPGA PCB layout
131562: 08/04/25: Joerg: Re: Survey: FPGA PCB layout
131570: 08/04/25: Joel Koltner: Re: Survey: FPGA PCB layout
131633: 08/04/27: JosephKK: Re: Survey: FPGA PCB layout
131641: 08/04/27: Joerg: Re: Survey: FPGA PCB layout
131646: 08/04/27: Michael A. Terrell: Re: Survey: FPGA PCB layout
131650: 08/04/27: krw: Re: Survey: FPGA PCB layout
131651: 08/04/27: Michael A. Terrell: Re: Survey: FPGA PCB layout
131310: 08/04/18: qrk: Re: Survey: FPGA PCB layout
131305: 08/04/18: Joel Koltner: Re: Survey: FPGA PCB layout
131545: 08/04/24: JosephKK: Re: Survey: FPGA PCB layout
131576: 08/04/25: Joerg: Re: Survey: FPGA PCB layout
131634: 08/04/27: JosephKK: Re: Survey: FPGA PCB layout
131642: 08/04/27: Joerg: Re: Survey: FPGA PCB layout
131556: 08/04/24: JosephKK: Re: Survey: FPGA PCB layout
131571: 08/04/25: Joel Koltner: Re: Survey: FPGA PCB layout
131273: 08/04/17: Symon: Re: Survey: FPGA PCB layout
131276: 08/04/17: Symon: Re: Survey: FPGA PCB layout
131275: 08/04/17: Andy: Re: Survey: FPGA PCB layout
131277: 08/04/17: John Adair: Re: Survey: FPGA PCB layout
131285: 08/04/17: Dave: Re: Survey: FPGA PCB layout
131294: 08/04/17: John Larkin: Re: Survey: FPGA PCB layout
131301: 08/04/18: Joerg: Re: Survey: FPGA PCB layout
131296: 08/04/18: David L. Jones: Re: Survey: FPGA PCB layout
131319: 08/04/18: Nico Coesel: Re: Survey: FPGA PCB layout
131320: 08/04/18: Hal Murray: Re: Survey: FPGA PCB layout
131321: 08/04/18: Joel Koltner: Re: Survey: FPGA PCB layout
131326: 08/04/19: Nico Coesel: Re: Survey: FPGA PCB layout
131331: 08/04/19: Joerg: Re: Survey: FPGA PCB layout
131339: 08/04/20: Nico Coesel: Re: Survey: FPGA PCB layout
131351: 08/04/20: Joerg: Re: Survey: FPGA PCB layout
131352: 08/04/20: John Larkin: Re: Survey: FPGA PCB layout
131353: 08/04/20: Joerg: Re: Survey: FPGA PCB layout
131356: 08/04/20: John Larkin: Re: Survey: FPGA PCB layout
131365: 08/04/20: Joerg: Re: Survey: FPGA PCB layout
131375: 08/04/20: krw: Re: Survey: FPGA PCB layout
131412: 08/04/21: Joerg: Re: Survey: FPGA PCB layout
131452: 08/04/21: krw: Re: Survey: FPGA PCB layout
131455: 08/04/21: Joerg: Re: Survey: FPGA PCB layout
131458: 08/04/21: krw: Re: Survey: FPGA PCB layout
131615: 08/04/26: Eric Smith: Re: Survey: FPGA PCB layout
131621: 08/04/26: Joerg: Re: Survey: FPGA PCB layout
131635: 08/04/27: JosephKK: Re: Survey: FPGA PCB layout
131644: 08/04/27: Joerg: Re: Survey: FPGA PCB layout
131645: 08/04/27: Chuck Harris: Re: Survey: FPGA PCB layout
131428: 08/04/21: Joel Koltner: Re: Survey: FPGA PCB layout
131444: 08/04/21: John Larkin: Re: Survey: FPGA PCB layout
131453: 08/04/21: krw: Re: Survey: FPGA PCB layout
131456: 08/04/21: Joerg: Re: Survey: FPGA PCB layout
131460: 08/04/21: krw: Re: Survey: FPGA PCB layout
131364: 08/04/20: krw: Re: Survey: FPGA PCB layout
131355: 08/04/20: Michael A. Terrell: Re: Survey: FPGA PCB layout
131357: 08/04/20: John Larkin: Re: Survey: FPGA PCB layout
131358: 08/04/20: Michael A. Terrell: Re: Survey: FPGA PCB layout
131376: 08/04/20: John Larkin: Re: Survey: FPGA PCB layout
131391: 08/04/21: Michael A. Terrell: Re: Survey: FPGA PCB layout
131416: 08/04/21: Chuck Harris: Re: Survey: FPGA PCB layout
131409: 08/04/21: rickman: Re: Survey: FPGA PCB layout
131414: 08/04/21: rickman: Re: Survey: FPGA PCB layout
131426: 08/04/21: Michael A. Terrell: Re: Survey: FPGA PCB layout
131608: 08/04/25: David L. Jones: Re: Survey: FPGA PCB layout
131660: 08/04/28: <Brian.Sullivan.EMA@gmail.com>: Re: Survey: FPGA PCB layout
131267: 08/04/17: <robquigley@gmail.com>: XST design frequency setting
131270: 08/04/17: Mike Treseler: Re: XST design frequency setting
131281: 08/04/17: HT-Lab: Re: XST design frequency setting
131288: 08/04/17: Brian Davis: Re: XST design frequency setting
131283: 08/04/17: Andreas Ehliar: Chip photos of old FPGAs
131293: 08/04/18: Andreas Ehliar: Re: Chip photos of old FPGAs
131299: 08/04/18: ratemonotonic: New to FPGA : Timing Closure
131302: 08/04/18: Jon Beniston: Re: New to FPGA : Timing Closure
131307: 08/04/18: KJ: Re: New to FPGA : Timing Closure
131300: 08/04/18: <oshea@mail.uri.edu>: Chipscope is Failing
131312: 08/04/18: Raban: Has anyone dealt with Avnet? or NuHorizons when trying to purchase Xilinx stuff
131314: 08/04/18: Mike Treseler: Re: Has anyone dealt with Avnet? or NuHorizons when trying to purchase
131324: 08/04/19: Ken Ryan: Re: Has anyone dealt with Avnet? or NuHorizons when trying to purchase
131328: 08/04/19: John Adair: Re: Has anyone dealt with Avnet? or NuHorizons when trying to
131329: 08/04/19: Georg Acher: Re: Has anyone dealt with Avnet? or NuHorizons when trying to purchase Xilinx stuff
131325: 08/04/18: <ben@hometoolong.inv>: Xilinx DDR2 Interface
131399: 08/04/21: Jim Wu: Re: Xilinx DDR2 Interface
131402: 08/04/21: <ben@hometoolong.inv>: Re: Xilinx DDR2 Interface
131407: 08/04/21: Mike Harrison: Re: Xilinx DDR2 Interface
131438: 08/04/21: Kevin Neilson: Re: Xilinx DDR2 Interface
131451: 08/04/21: <ben@hometoolong.inv>: Re: Xilinx DDR2 Interface
131442: 08/04/21: Gabor: Re: Xilinx DDR2 Interface
131327: 08/04/20: Haile Yu (Harry): How to instantiate macro in verilog
131398: 08/04/21: Jim Wu: Re: How to instantiate macro in verilog
131430: 08/04/21: Kevin Neilson: Re: How to instantiate macro in verilog
131465: 08/04/21: Moazzam: Re: How to instantiate macro in verilog
131534: 08/04/24: Kevin Neilson: Re: How to instantiate macro in verilog
131548: 08/04/24: Moazzam: Re: How to instantiate macro in verilog
131332: 08/04/19: Moikel: Synthesis Comparison
131333: 08/04/19: Mike Treseler: Re: Synthesis Comparison
131404: 08/04/21: KJ: Re: Synthesis Comparison
131408: 08/04/21: Kolja Sulimma: Re: Synthesis Comparison
131418: 08/04/21: KJ: Re: Synthesis Comparison
131336: 08/04/19: Michael: Very simple VHDL problem
131338: 08/04/20: Frank Buss: Re: Very simple VHDL problem
131344: 08/04/20: Frank Buss: Re: Very simple VHDL problem
131368: 08/04/20: glen herrmannsfeldt: Re: Very simple VHDL problem
131401: 08/04/21: Brian Drummond: Re: Very simple VHDL problem
131341: 08/04/20: Nicolas Matringe: Re: Very simple VHDL problem
131347: 08/04/20: Symon: Re: Very simple VHDL problem
131388: 08/04/21: Nicolas Matringe: Re: Very simple VHDL problem
131429: 08/04/21: Kevin Neilson: Re: Very simple VHDL problem
131468: 08/04/22: HT-Lab: Re: Very simple VHDL problem
131588: 08/04/25: Kevin Neilson: Re: Very simple VHDL problem
131594: 08/04/25: Mike Treseler: Re: Very simple VHDL problem
131342: 08/04/20: Michael: Re: Very simple VHDL problem
131343: 08/04/20: michael: Re: Very simple VHDL problem
131345: 08/04/20: Michael: Re: Very simple VHDL problem
131346: 08/04/20: Michael: Re: Very simple VHDL problem
131432: 08/04/21: KJ: Re: Very simple VHDL problem
131659: 08/04/28: Andy: Re: Very simple VHDL problem
131348: 08/04/20: dajjou: how we can prove that really the AES 256 is used to crypt the
131349: 08/04/20: <chrisdekoh@gmail.com>: synchronous reset problems on FPGA
131350: 08/04/20: Mike Treseler: Re: synchronous reset problems on FPGA
131372: 08/04/20: Mike Treseler: Re: synchronous reset problems on FPGA
131470: 08/04/22: Nial Stewart: Re: synchronous reset problems on FPGA
131370: 08/04/20: <chrisdekoh@gmail.com>: Re: synchronous reset problems on FPGA
131371: 08/04/20: Peter Alfke: Re: synchronous reset problems on FPGA
131373: 08/04/20: <chrisdekoh@gmail.com>: Re: synchronous reset problems on FPGA
131379: 08/04/20: Peter Alfke: Re: synchronous reset problems on FPGA
131382: 08/04/20: <chrisdekoh@gmail.com>: Re: synchronous reset problems on FPGA
131392: 08/04/21: HT-Lab: Re: synchronous reset problems on FPGA
131396: 08/04/21: Lars: Re: synchronous reset problems on FPGA
131400: 08/04/21: KJ: Re: synchronous reset problems on FPGA
131481: 08/04/22: Andy Peters: Re: synchronous reset problems on FPGA
131354: 08/04/20: Michael: Problem writing quadrature decoder
131359: 08/04/20: Mike Treseler: Re: Problem writing quadrature decoder
131374: 08/04/20: Mike Treseler: Re: Problem writing quadrature decoder
131360: 08/04/21: Frank Buss: Re: Problem writing quadrature decoder
131367: 08/04/20: glen herrmannsfeldt: Re: Problem writing quadrature decoder
132019: 08/05/09: glen herrmannsfeldt: Re: Problem writing quadrature decoder
132023: 08/05/10: Jim Granville: Re: Problem writing quadrature decoder
132038: 08/05/10: John_H: Re: Problem writing quadrature decoder
132040: 08/05/11: Eric Smith: Re: Problem writing quadrature decoder
132043: 08/05/11: nospam: Re: Problem writing quadrature decoder
132052: 08/05/11: Eric Smith: Re: Problem writing quadrature decoder
132045: 08/05/12: Jim Granville: Re: Problem writing quadrature decoder
132047: 08/05/11: Frank Buss: Re: Problem writing quadrature decoder
132049: 08/05/12: Jim Granville: Re: Problem writing quadrature decoder
132053: 08/05/11: John_H: Re: Problem writing quadrature decoder
132054: 08/05/12: Jim Granville: Re: Problem writing quadrature decoder
132063: 08/05/12: John_H: Re: Problem writing quadrature decoder
132073: 08/05/13: Jim Granville: Re: Problem writing quadrature decoder
132077: 08/05/13: Jim Granville: Re: Problem writing quadrature decoder
132080: 08/05/13: Jim Granville: Re: Problem writing quadrature decoder
132078: 08/05/13: Jim Granville: Re: Problem writing quadrature decoder
132079: 08/05/13: Jim Granville: Re: Problem writing quadrature decoder
132084: 08/05/13: Jim Granville: Re: Problem writing quadrature decoder
132085: 08/05/13: Jim Granville: Re: Problem writing quadrature decoder
132086: 08/05/12: John_H: Re: Problem writing quadrature decoder
132088: 08/05/13: Jim Granville: Re: Problem writing quadrature decoder
132090: 08/05/12: John_H: Re: Problem writing quadrature decoder
132091: 08/05/13: Jim Granville: Re: Problem writing quadrature decoder
132094: 08/05/13: John_H: Re: Problem writing quadrature decoder
132096: 08/05/14: Jim Granville: Re: Problem writing quadrature decoder
132103: 08/05/13: glen herrmannsfeldt: Re: Problem writing quadrature decoder
132104: 08/05/14: Jim Granville: Re: Problem writing quadrature decoder
132106: 08/05/14: Jim Granville: Re: Problem writing quadrature decoder
132111: 08/05/14: Jim Granville: Re: Problem writing quadrature decoder
132039: 08/05/11: Jim Granville: Re: Problem writing quadrature decoder
131410: 08/04/21: John_H: Re: Problem writing quadrature decoder
131471: 08/04/22: Brian Drummond: Re: Problem writing quadrature decoder
131361: 08/04/20: Michael: Re: Problem writing quadrature decoder
131362: 08/04/20: Michael: Re: Problem writing quadrature decoder
131363: 08/04/20: Peter Alfke: Re: Problem writing quadrature decoder
131595: 08/04/25: glen herrmannsfeldt: Re: Problem writing quadrature decoder
131647: 08/04/27: none: Re: Problem writing quadrature decoder
131680: 08/04/29: Jim Granville: Re: Problem writing quadrature decoder
131924: 08/05/08: Jim Granville: Re: Problem writing quadrature decoder
131937: 08/05/08: Jim Granville: Re: Problem writing quadrature decoder
131366: 08/04/20: -jg: Re: Problem writing quadrature decoder
131369: 08/04/20: Peter Alfke: Re: Problem writing quadrature decoder
131377: 08/04/20: Michael: Re: Problem writing quadrature decoder
131378: 08/04/20: Peter Alfke: Re: Problem writing quadrature decoder
131380: 08/04/20: Peter Alfke: Re: Problem writing quadrature decoder
131381: 08/04/20: Michael: Re: Problem writing quadrature decoder
131383: 08/04/20: Peter Alfke: Re: Problem writing quadrature decoder
131384: 08/04/20: Michael: Re: Problem writing quadrature decoder
131385: 08/04/20: Peter Alfke: Re: Problem writing quadrature decoder
131386: 08/04/20: Michael: Re: Problem writing quadrature decoder
131387: 08/04/20: Michael: Re: Problem writing quadrature decoder
131389: 08/04/20: -jg: Re: Problem writing quadrature decoder
131390: 08/04/21: -jg: Re: Problem writing quadrature decoder
131421: 08/04/21: <bcuzeau@gmail.com>: Re: Problem writing quadrature decoder
131422: 08/04/21: Peter Alfke: Re: Problem writing quadrature decoder
131425: 08/04/21: Michael: Re: Problem writing quadrature decoder
131439: 08/04/21: John_H: Re: Problem writing quadrature decoder
131448: 08/04/21: John_H: Re: Problem writing quadrature decoder
131450: 08/04/21: michael: Re: Problem writing quadrature decoder
131461: 08/04/21: -jg: Re: Problem writing quadrature decoder
131597: 08/04/25: Peter Alfke: Re: Problem writing quadrature decoder
131616: 08/04/26: -jg: Re: Problem writing quadrature decoder
131620: 08/04/26: Peter Alfke: Re: Problem writing quadrature decoder
131631: 08/04/26: Peter Alfke: Re: Problem writing quadrature decoder
131636: 08/04/27: -jg: Re: Problem writing quadrature decoder
131637: 08/04/27: -jg: Re: Problem writing quadrature decoder
131640: 08/04/27: Peter Alfke: Re: Problem writing quadrature decoder
131866: 08/05/05: Peter Alfke: Re: Problem writing quadrature decoder
131933: 08/05/07: Peter Alfke: Re: Problem writing quadrature decoder
132036: 08/05/10: Peter Alfke: Re: Problem writing quadrature decoder
132044: 08/05/11: Peter Alfke: Re: Problem writing quadrature decoder
132046: 08/05/11: Peter Alfke: Re: Problem writing quadrature decoder
132074: 08/05/12: John_H: Re: Problem writing quadrature decoder
132075: 08/05/12: Peter Alfke: Re: Problem writing quadrature decoder
132081: 08/05/12: John_H: Re: Problem writing quadrature decoder
132100: 08/05/13: Peter Alfke: Re: Problem writing quadrature decoder
132105: 08/05/13: John_H: Re: Problem writing quadrature decoder
132108: 08/05/13: Peter Alfke: Re: Problem writing quadrature decoder
132109: 08/05/13: Peter Alfke: Re: Problem writing quadrature decoder
132527: 08/05/29: Mike Treseler: Re: Problem writing quadrature decoder
131394: 08/04/21: Evan Lavelle: ANNOUNCE: Maia 0.8.2: module-level HDL verification tool
131420: 08/04/21: KJ: Re: ANNOUNCE: Maia 0.8.2: module-level HDL verification tool
131423: 08/04/21: Mike Treseler: Re: ANNOUNCE: Maia 0.8.2: module-level HDL verification tool
131435: 08/04/21: Evan Lavelle: Re: ANNOUNCE: Maia 0.8.2: module-level HDL verification tool
131614: 08/04/26: Mike Treseler: Re: ANNOUNCE: Maia 0.8.2: module-level HDL verification tool
131424: 08/04/21: HT-Lab: Re: ANNOUNCE: Maia 0.8.2: module-level HDL verification tool
131436: 08/04/21: Evan Lavelle: Re: ANNOUNCE: Maia 0.8.2: module-level HDL verification tool
131431: 08/04/21: KJ: Re: ANNOUNCE: Maia 0.8.2: module-level HDL verification tool
131441: 08/04/21: Kevin Neilson: Re: ANNOUNCE: Maia 0.8.2: module-level HDL verification tool
131469: 08/04/22: Evan Lavelle: Re: ANNOUNCE: Maia 0.8.2: module-level HDL verification tool
131603: 08/04/25: Andy: Re: ANNOUNCE: Maia 0.8.2: module-level HDL verification tool
131395: 08/04/21: Pablo: XmdStub fails when connecting via JTAG.
131397: 08/04/21: Pablo: OPB_MDM functionality
131403: 08/04/21: Tim Pope: Celoxica RC1000
131411: 08/04/21: HT-Lab: Re: Celoxica RC1000
131443: 08/04/21: Tim Pope: Re: Celoxica RC1000
131405: 08/04/21: <mspiegels@gmail.com>: DCM configuration in Virtex-4 FPGA
131484: 08/04/22: MM: Re: DCM configuration in Virtex-4 FPGA
131486: 08/04/22: austin: Re: DCM configuration in Virtex-4 FPGA
131538: 08/04/24: MM: Re: DCM configuration in Virtex-4 FPGA
131516: 08/04/24: <mspiegels@gmail.com>: Re: DCM configuration in Virtex-4 FPGA
131406: 08/04/21: LC: not inferred RAM, on QII
131413: 08/04/21: ALuPin@web.de: Re: not inferred RAM, on QII
131415: 08/04/21: LC: Re: not inferred RAM, on QII
131459: 08/04/22: LC: Re: not inferred RAM, on QII
131419: 08/04/21: KJ: Re: not inferred RAM, on QII
131457: 08/04/22: LC: Re: not inferred RAM, on QII
131473: 08/04/22: Mike Treseler: Re: not inferred RAM, on QII
131518: 08/04/24: LC: Re: not inferred RAM, on QII
131417: 08/04/21: axalay: opb_intc + PowerPC
131472: 08/04/22: Brian Drummond: Re: opb_intc + PowerPC
131498: 08/04/23: Brian Drummond: Re: opb_intc + PowerPC
131492: 08/04/22: axalay: Re: opb_intc + PowerPC
131434: 08/04/21: <adubinsky457@gmail.com>: Turning off the DLL to run DDR2 at very low frequency
131440: 08/04/21: Kevin Neilson: Re: Turning off the DLL to run DDR2 at very low frequency
131535: 08/04/24: Kevin Neilson: Re: Turning off the DLL to run DDR2 at very low frequency
131490: 08/04/22: <adubinsky457@gmail.com>: Re: Turning off the DLL to run DDR2 at very low frequency
131494: 08/04/23: mng: Re: Turning off the DLL to run DDR2 at very low frequency
131523: 08/04/24: John Adair: Re: Turning off the DLL to run DDR2 at very low frequency
131447: 08/04/21: jjlindula@hotmail.com: Newbie: Testbench question
131449: 08/04/21: jjlindula@hotmail.com: Re: Newbie: Testbench question
131466: 08/04/22: RCIngham: Re: Newbie: Testbench question
131467: 08/04/22: HT-Lab: Re: Newbie: Testbench question
131475: 08/04/22: Nial Stewart: Re: Newbie: Testbench question
131476: 08/04/22: Stef: Re: Newbie: Testbench question
131477: 08/04/22: Philip Potter: Re: Newbie: Testbench question
131474: 08/04/22: jjlindula@hotmail.com: Re: Newbie: Testbench question
131564: 08/04/25: jjlindula@hotmail.com: Re: Newbie: Testbench question
131462: 08/04/22: bob elkind: Altera Cyc II config problems
131463: 08/04/22: Denkedran Joe: How to independently program the embedded PowerPC in a Virtex?
131464: 08/04/22: Matthew Hicks: Re: How to independently program the embedded PowerPC in a Virtex?
131479: 08/04/22: Ed McGettigan: Re: How to independently program the embedded PowerPC in a Virtex?
131480: 08/04/22: Tim Wescott: Re: How to independently program the embedded PowerPC in a Virtex?
131478: 08/04/22: Jon Elson: Need a few Xilinx Spartan FPGAs
131482: 08/04/22: Alan Nishioka: Xilinx is cancelling the Virtex-E XCV1000E-FG860
131483: 08/04/22: austin: Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860
131511: 08/04/23: Alan Nishioka: Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860
131512: 08/04/23: austin: Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860
131537: 08/04/24: dalai lamah: Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860
131540: 08/04/24: Uwe Bonnes: Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860
131505: 08/04/23: Symon: Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860
131522: 08/04/24: Alan Nishioka: Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860
131526: 08/04/24: Symon: Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860
131579: 08/04/25: Peter Alfke: Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860
131514: 08/04/23: Peter Alfke: Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860
131517: 08/04/24: Antti: Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860
131527: 08/04/24: MH: Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860
131547: 08/04/24: Alan Nishioka: Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860
131485: 08/04/22: NN: FPGA Verilog state machine lock up
131487: 08/04/22: Mike Treseler: Re: FPGA Verilog state machine lock up
131488: 08/04/22: <songrise@gmail.com>: Can somebody help about Period Timing Constraints
131504: 08/04/23: Symon: Re: Can somebody help about Period Timing Constraints
131491: 08/04/22: laura: the order in which some switches are turned on
131493: 08/04/23: backhus: Re: the order in which some switches are turned on
131539: 08/04/24: jkljljklk: Re: the order in which some switches are turned on
131596: 08/04/25: glen herrmannsfeldt: Re: the order in which some switches are turned on
131654: 08/04/28: Gabor: Re: the order in which some switches are turned on
131495: 08/04/23: <andrew.nesterov@softhome.net>: 10.1 EDK - How can I create a user library in SDK?
131496: 08/04/23: Andreas Ehliar: Re: Verilog state machines, latches, syntax and a bet!
131497: 08/04/23: ee_ether: Verilog state machines, latches, syntax and a bet!
131503: 08/04/23: KJ: Re: Verilog state machines, latches, syntax and a bet!
131507: 08/04/23: Muzaffer Kal: Re: Verilog state machines, latches, syntax and a bet!
131508: 08/04/23: Muzaffer Kal: Re: Verilog state machines, latches, syntax and a bet!
131529: 08/04/24: Muzaffer Kal: Re: Verilog state machines, latches, syntax and a bet!
131510: 08/04/23: Dave: Re: Verilog state machines, latches, syntax and a bet!
131513: 08/04/23: Eric Crabill: Re: Verilog state machines, latches, syntax and a bet!
131530: 08/04/24: KJ: Re: Verilog state machines, latches, syntax and a bet!
131536: 08/04/24: Kevin Neilson: Re: Verilog state machines, latches, syntax and a bet!
131499: 08/04/23: RealInfo: FPGA comeback
131500: 08/04/23: Symon: Re: FPGA comeback
131501: 08/04/23: oen_br: Re: FPGA comeback
131502: 08/04/23: RealInfo: Re: FPGA comeback
131544: 08/04/25: jtw: Re: FPGA comeback
131695: 08/04/29: RealInfo: Re: FPGA comeback
131703: 08/04/29: John_H: Re: FPGA comeback
131506: 08/04/23: austin: Re: FPGA comeback
131515: 08/04/23: H. Peter Anvin: Re: FPGA comeback
131509: 08/04/23: Peter Glar: superscalar processor design
131519: 08/04/24: Narendra Sisodiya: will there be any problem with diffrent version of sysgen & EDK
131533: 08/04/24: <ghelbig@lycos.com>: Re: will there be any problem with diffrent version of sysgen & EDK
131542: 08/04/24: Narendra Sisodiya: Re: will there be any problem with diffrent version of sysgen & EDK
131546: 08/04/24: Narendra Sisodiya: Re: will there be any problem with diffrent version of sysgen & EDK
131592: 08/04/25: <ghelbig@lycos.com>: Re: will there be any problem with diffrent version of sysgen & EDK
131520: 08/04/24: Narendra Sisodiya: video stream transfer via UART and Bluetooth in FPGA
131525: 08/04/24: Antti: Re: video stream transfer via UART and Bluetooth in FPGA
131531: 08/04/24: Narendra Sisodiya: Re: video stream transfer via UART and Bluetooth in FPGA
131532: 08/04/24: Antti: Re: video stream transfer via UART and Bluetooth in FPGA
131541: 08/04/24: Narendra Sisodiya: Re: video stream transfer via UART and Bluetooth in FPGA
131521: 08/04/24: u_stadler@yahoo.de: HydraXC + EDK
131524: 08/04/24: Antti: Re: HydraXC + EDK
131561: 08/04/25: u_stadler@yahoo.de: Re: HydraXC + EDK
131707: 08/04/29: Antti: Re: HydraXC + EDK
131709: 08/04/29: u_stadler@yahoo.de: Re: HydraXC + EDK
131710: 08/04/29: Antti: Re: HydraXC + EDK
131528: 08/04/24: Shyam Sundar: ACTEL FPGA static timing analysis
131543: 08/04/25: Julio Espada: ATF750 for Proteus
131554: 08/04/25: Robert Lacoste: Re: ATF750 for Proteus
131577: 08/04/25: <ghelbig@lycos.com>: Re: ATF750 for Proteus
131617: 08/04/26: -jg: Re: ATF750 for Proteus
131672: 08/04/29: Julio Espada: Re: ATF750 for Proteus
131549: 08/04/24: krunal: delta sigma adc.....
131557: 08/04/25: Symon: Re: delta sigma adc.....
131563: 08/04/25: austin: Re: -. . ..- ... --. .-. --- ..- --- .--.
131565: 08/04/25: Symon: Re: -. . ..- ... --. .-. --- ..- --- .--.
131567: 08/04/25: austin: Re: -. . ..- ... --. .-. --- ..- --- .--.
131569: 08/04/25: Symon: Re: -. . ..- ... --. .-. --- ..- --- .--.
131581: 08/04/25: austin: Re: -. . ..- ... --. .-. --- ..- --- .--.
131609: 08/04/26: Symon: Re: -. . ..- ... --. .-. --- ..- --- .--.
131657: 08/04/28: austin: Aldiss Lamps, etc.
131587: 08/04/25: none: Re: -. . ..- ... --. .-. --- ..- --- .--.
131589: 08/04/25: austin: Re: -. . ..- ... --. .-. ..- --- .--.
131604: 08/04/25: austin: Re: (won't even attempt to try again .. .. ..)
132526: 08/05/29: MikeWhy: Re: (won't even attempt to try again .. .. ..)
132528: 08/05/29: Ray Andraka: Re: (won't even attempt to try again .. .. ..)
132534: 08/05/29: MikeWhy: Re: (won't even attempt to try again .. .. ..)
132550: 08/05/30: Ray Andraka: Re: (won't even attempt to try again .. .. ..)
132551: 08/05/30: Ray Andraka: Re: (won't even attempt to try again .. .. ..)
132582: 08/06/01: Eric Smith: Re: (won't even attempt to try again .. .. ..)
132585: 08/06/02: Ray Andraka: Re: (won't even attempt to try again .. .. ..)
131598: 08/04/25: John_H: Re: -. . .-- ... --. .-. --- ..- .--.
132539: 08/05/30: Brian Davis: Re: (won't even attempt to try again .. .. ..)
132540: 08/05/30: <parekh.sh@gmail.com>: Re: delta sigma adc.....
131558: 08/04/25: <vboykov@gmail.com>: V5, EMAC simulation problem, when 4 EMACs are used together (ISE
131559: 08/04/25: <tarmopalm@gmx.de>: Re: noob question
131566: 08/04/25: Symon: Re: noob question
131568: 08/04/25: KJ: Re: noob question
131572: 08/04/25: <raghunandan85@gmail.com>: PLB Master Example
131613: 08/04/25: Andy: Re: PLB Master Example
131679: 08/04/28: <raghunandan85@gmail.com>: Re: PLB Master Example
131846: 08/05/03: <raghunandan85@gmail.com>: Re: PLB Master Example
131573: 08/04/25: Hua: Timing closure problem --- how to make the QII fitter smarter
131655: 08/04/28: ALuPin@web.de: Re: Timing closure problem --- how to make the QII fitter smarter
131661: 08/04/28: Ed McGettigan: Re: Timing closure problem --- how to make the QII fitter smarter
132623: 08/06/03: Hua: Re: Timing closure problem --- how to make the QII fitter smarter
132624: 08/06/03: Hua: Re: Timing closure problem --- how to make the QII fitter smarter
132625: 08/06/03: John_H: Re: Timing closure problem --- how to make the QII fitter smarter
131574: 08/04/25: Philip Potter: Re: noob question
131578: 08/04/25: <HairyTheASICGuy@gmail.com>: Breaking News ... Accellera Verification Working Group Forming
131580: 08/04/25: <BestInSoC@gmail.com>: Re: Breaking News ... Accellera Verification Working Group Forming
131582: 08/04/25: Jason Zheng: Re: Breaking News ... Accellera Verification Working Group Forming
131607: 08/04/25: <BestInSoC@gmail.com>: Re: Breaking News ... Accellera Verification Working Group Forming
132041: 08/05/11: <harrytheasicguy@gmail.com>: Re: Breaking News ... Accellera Verification Working Group Forming
132071: 08/05/12: Dave Rich: Re: Breaking News ... Accellera Verification Working Group Forming
131583: 08/04/25: dalai lamah: Spartan3 "commercial" temperature range
131585: 08/04/25: Peter Alfke: Re: Spartan3 "commercial" temperature range
131599: 08/04/25: dalai lamah: Re: Spartan3 "commercial" temperature range
131593: 08/04/25: austin: Re: Spartan3 "commercial" temperature range
131601: 08/04/25: dalai lamah: Re: Spartan3 "commercial" temperature range
131605: 08/04/25: austin: Re: Spartan3 "commercial" temperature range
131584: 08/04/25: fl: How to arrange these SRL16 in a straight column
131590: 08/04/25: Duane Clark: Re: How to arrange these SRL16 in a straight column
131600: 08/04/25: John_H: Re: How to arrange these SRL16 in a straight column
131586: 08/04/25: MM: Virtex-4 inrush power-on current
131591: 08/04/25: austin: Re: Virtex-4 inrush power-on current
131610: 08/04/25: KJ: Re: Virtex-4 inrush power-on current
131611: 08/04/25: BobW: Re: Virtex-4 inrush power-on current
131619: 08/04/26: KJ: Re: Virtex-4 inrush power-on current
131612: 08/04/25: austin: Re: Virtex-4 inrush power-on current
131622: 08/04/26: Rob: Re: Virtex-4 inrush power-on current
131630: 08/04/27: Rob: Re: Virtex-4 inrush power-on current
131668: 08/04/28: austin: Re: Virtex-4 power-on current
131674: 08/04/28: MM: Re: Virtex-4 power-on current
131692: 08/04/29: austin: Re: Virtex-4 power-on current
131705: 08/04/29: MM: Re: Virtex-4 power-on current
131628: 08/04/26: Peter Alfke: Re: Virtex-4 inrush power-on current
131629: 08/04/26: Peter Alfke: Re: Virtex-4 inrush power-on current
131618: 08/04/26: Brian Drummond: Re: noob question
131623: 08/04/26: <swissiyoussef@gmail.com>: CRC algorithm
131624: 08/04/26: Alan Nishioka: Re: CRC algorithm
131626: 08/04/26: <swissiyoussef@gmail.com>: Re: CRC algorithm
131656: 08/04/28: bommels: Re: CRC algorithm
131728: 08/04/30: <swissiyoussef@gmail.com>: Re: CRC algorithm
131638: 08/04/27: <swissiyoussef@gmail.com>: how can i recover my unencrypted bitstream starting from encrypted
131643: 08/04/27: austin: Re: how can i recover my unencrypted bitstream starting from encrypted
131649: 08/04/27: austin: Re: how can i recover my unencrypted bitstream starting from encrypted
131652: 08/04/28: Symon: Re: how can i recover my unencrypted bitstream starting from encrypted one and knowing the KEY
131658: 08/04/28: austin: Re: how can i recover my unencrypted bitstream starting from encrypted
131662: 08/04/28: Gavin Scott: Re: how can i recover my unencrypted bitstream starting from encrypted one and knowing the KEY
131671: 08/04/28: austin: Re: how can i recover my unencrypted bitstream starting from encrypted
131712: 08/04/29: austin: Re: how can i recover my unencrypted bitstream starting from encrypted
131741: 08/04/30: austin: Re: how can i recover my unencrypted bitstream starting from encrypted
131746: 08/04/30: austin: Re: how can i recover my unencrypted bitstream starting from encrypted
131750: 08/04/30: Eric Smith: Re: how can i recover my unencrypted bitstream starting from encrypted one and knowing the KEY
131648: 08/04/27: <swissiyoussef@gmail.com>: Re: how can i recover my unencrypted bitstream starting from
131670: 08/04/28: mowa: Re: how can i recover my unencrypted bitstream starting from
131706: 08/04/29: Antti: Re: how can i recover my unencrypted bitstream starting from
131720: 08/04/29: <bamboutcha9999@hotmail.com>: Re: how can i recover my unencrypted bitstream starting from
131733: 08/04/30: Tonda: Re: how can i recover my unencrypted bitstream starting from
131663: 08/04/28: <sky465nm@trline4.org>: Nano transistor breakthrough?
131664: 08/04/28: Jon Elson: Re: Nano transistor breakthrough?
131665: 08/04/28: Fei Liu: what's next?
131666: 08/04/28: <freeagent.20.oracle@xoxy.net>: How to embed time and date in Xilinx FPGA?
131667: 08/04/28: Symon: Re: How to embed time and date in Xilinx FPGA?
131669: 08/04/28: John Adair: Darnaw1 Schematics
131673: 08/04/28: Jeff Cunningham: understanding xilinx silicon revisions (does ES come before CES4,
131713: 08/04/29: MM: Re: understanding xilinx silicon revisions (does ES come before CES4, etc.)
131716: 08/04/29: austin: Re: understanding xilinx silicon revisions (does ES come before CES4,
131714: 08/04/29: austin: Re: understanding xilinx silicon revisions (does ES come before CES4,
131717: 08/04/29: austin: Re: understanding xilinx silicon revisions (does ES come before CES4,
131675: 08/04/28: eromlignod: Debounce in Verilog?
131676: 08/04/29: Jeff Cunningham: Re: Debounce in Verilog?
131677: 08/04/28: Thomas Stanka: Re: Debounce in Verilog?
131678: 08/04/28: Peter Alfke: Re: Debounce in Verilog?
131699: 08/04/29: John_H: Re: Debounce in Verilog?
131681: 08/04/29: Tommy Thorn: Could someone tell me NIOS II/MB performance on this benchmark?
131684: 08/04/29: Göran Bilski: Re: Could someone tell me NIOS II/MB performance on this benchmark?
131685: 08/04/29: Göran Bilski: Re: Could someone tell me NIOS II/MB performance on this benchmark?
131729: 08/04/30: Göran Bilski: Re: Could someone tell me NIOS II/MB performance on this benchmark?
131701: 08/04/29: Tommy Thorn: Re: Could someone tell me NIOS II/MB performance on this benchmark?
131702: 08/04/29: Tommy Thorn: Re: Could someone tell me NIOS II/MB performance on this benchmark?
131682: 08/04/29: G_Abgrall: Problem with PlanAhead on Partial Reconfiguration on ML403 (Virtex 4)
131691: 08/04/29: G_Abgrall: Re: Problem with PlanAhead on Partial Reconfiguration on ML403
132093: 08/05/13: G_Abgrall: Re: Problem with PlanAhead on Partial Reconfiguration on ML403
131683: 08/04/29: uche: parallel port using XSA-50
131686: 08/04/29: FreeRTOS.org: Virtex4 PPC405 - FPU problem
131687: 08/04/29: XSterna: Chirp generator / CORDIC algo ?
131693: 08/04/29: Duane Clark: Re: Chirp generator / CORDIC algo ?
131696: 08/04/29: XSterna: Re: Chirp generator / CORDIC algo ?
131697: 08/04/29: Kevin Neilson: Re: Chirp generator / CORDIC algo ?
131698: 08/04/29: Kevin Neilson: Re: Chirp generator / CORDIC algo ?
131767: 08/05/01: MM: Re: Chirp generator / CORDIC algo ?
131756: 08/05/01: XSterna: Re: Chirp generator / CORDIC algo ?
131793: 08/05/02: XSterna: Re: Chirp generator / CORDIC algo ?
131936: 08/05/07: Ray Andraka: Re: Chirp generator / CORDIC algo ?
131998: 08/05/09: Duane Clark: Re: Chirp generator / CORDIC algo ?
131943: 08/05/08: XSterna: Re: Chirp generator / CORDIC algo ?
131688: 08/04/29: <digi.megabyte@gmail.com>: floating point and logarithm in vhdl+xilinx
131689: 08/04/29: HT-Lab: Re: floating point and logarithm in vhdl+xilinx
131690: 08/04/29: <charles.elias@wpafb.af.mil>: Functional Simulation of Virtex-4 Block Memory
131694: 08/04/29: Duane Clark: Re: Functional Simulation of Virtex-4 Block Memory
131721: 08/04/29: Brad Smallridge: Re: Functional Simulation of Virtex-4 Block Memory
131737: 08/04/30: Duane Clark: Re: Functional Simulation of Virtex-4 Block Memory
131748: 08/04/30: Brad Smallridge: Re: Functional Simulation of Virtex-4 Block Memory
131751: 08/04/30: Duane Clark: Re: Functional Simulation of Virtex-4 Block Memory
131760: 08/05/01: Mike Treseler: Re: Functional Simulation of Virtex-4 Block Memory
131762: 08/05/01: Duane Clark: Re: Functional Simulation of Virtex-4 Block Memory
131764: 08/05/01: Duane Clark: Re: Functional Simulation of Virtex-4 Block Memory
131780: 08/05/01: Jeff Cunningham: Re: Functional Simulation of Virtex-4 Block Memory
131782: 08/05/02: Duane Clark: Re: Functional Simulation of Virtex-4 Block Memory
131783: 08/05/01: Jeff Cunningham: Re: Functional Simulation of Virtex-4 Block Memory
131785: 08/05/01: Mike Treseler: Re: Functional Simulation of Virtex-4 Block Memory
132149: 08/05/15: Ray Andraka: Re: Functional Simulation of Virtex-4 Block Memory
131736: 08/04/30: <charles.elias@wpafb.af.mil>: Re: Functional Simulation of Virtex-4 Block Memory
131759: 08/05/01: <charles.elias@wpafb.af.mil>: Re: Functional Simulation of Virtex-4 Block Memory
131763: 08/05/01: Peter Alfke: Re: Functional Simulation of Virtex-4 Block Memory
131700: 08/04/29: Kevin Neilson: Style for Highly-Pipelined State Machines
131704: 08/04/29: Mike Treseler: Re: Style for Highly-Pipelined State Machines
131722: 08/04/30: KJ: Re: Style for Highly-Pipelined State Machines
131813: 08/05/02: Kevin Neilson: Re: Style for Highly-Pipelined State Machines
131829: 08/05/02: Mike Treseler: Re: Style for Highly-Pipelined State Machines
131871: 08/05/05: Kevin Neilson: Re: Style for Highly-Pipelined State Machines
131833: 08/05/02: KJ: Re: Style for Highly-Pipelined State Machines
131870: 08/05/05: Kevin Neilson: Re: Style for Highly-Pipelined State Machines
131877: 08/05/06: KJ: Re: Style for Highly-Pipelined State Machines
131825: 08/05/02: Aiken: Re: Style for Highly-Pipelined State Machines
131708: 08/04/29: u_stadler@yahoo.de: PPC + APU + FSL + Xilkernel Problem
131711: 08/04/29: Dave: Hand-editing xilinx.sys
131715: 08/04/29: AugustoEinsfeldt: XCF02S not seen in the JTAG chain
131718: 08/04/29: austin: Re: XCF02S not seen in the JTAG chain
131739: 08/04/30: austin: Re: XCF02S not seen in the JTAG chain
131734: 08/04/30: AugustoEinsfeldt: Re: XCF02S not seen in the JTAG chain
131792: 08/05/02: AugustoEinsfeldt: Re: XCF02S not seen in the JTAG chain
131719: 08/04/29: water9580@yahoo.com: I use a ftp tool test my V5-based PCIE ethernet NIC controller.
131723: 08/04/29: water9580@yahoo.com: how to optimize this comparator for better synthesis result?
131724: 08/04/29: Tommy Thorn: Re: how to optimize this comparator for better synthesis result?
131725: 08/04/30: backhus: Re: how to optimize this comparator for better synthesis result?
131740: 08/04/30: Andy: Re: how to optimize this comparator for better synthesis result?
131726: 08/04/30: Antony: XUPV2P and EDK 10.1
132444: 08/05/27: Antony: Re: XUPV2P and EDK 10.1
131727: 08/04/30: <bamboutcha9999@hotmail.com>: what's the difference between .rba & .rbb files ?
131730: 08/04/30: <swissiyoussef@gmail.com>: Re: what's the difference between .rba & .rbb files ?
131731: 08/04/30: <msn444@gmail.com>: Virtex4 DCM doesn't work unless freezing cold
131732: 08/04/30: Symon: Re: Virtex4 DCM doesn't work unless freezing cold
131738: 08/04/30: MM: Re: Virtex4 DCM doesn't work unless freezing cold
131742: 08/04/30: austin: Re: Virtex4 DCM doesn't work unless freezing cold
131743: 08/04/30: austin: Re: Virtex4 DCM doesn't work unless freezing cold
131770: 08/05/01: <msn444@gmail.com>: Re: Virtex4 DCM doesn't work unless freezing cold
131735: 08/04/30: <shakith.fernando@gmail.com>: PCI Express Switch
131789: 08/05/02: Kolja Sulimma: Re: PCI Express Switch
131939: 08/05/08: Philip Joe: Re: PCI Express Switch
131744: 08/04/30: <chrisdekoh@gmail.com>: co-sim for handel C with modelsim vs pure modelsim VHDL simulation
131745: 08/04/30: Mike Treseler: Re: co-sim for handel C with modelsim vs pure modelsim VHDL simulation
131747: 08/04/30: Kolja Sulimma: Re: how to optimize this comparator for better synthesis result?
131749: 08/04/30: water9580@yahoo.com: Re: how to optimize this comparator for better synthesis result?
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