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Hey everyone,
Im having difficulty with signals that i tie to zero or one (using
Verilog 1'b0, 1'b1 etc) appearing as z's in post synthesis simulation.
They appear fine in pre synthesis simulation, as one or zero depending
on what i specify, but they always appear as z in post synthesis
simulation.
As a result of this i have pre and post synthesis simulation mismatch
results and also my bit file doesnt work properly on my fpga (Virtex
II).
I'm using XST in ISE 9.2.
Is there a way i can have XST take care of this or must i provide a
specific ground signal to a module if i wish to drive a constant zero
or one in a circuit? I've inherited some code with *lots* of zero's
and one's specified like this and it appeared to work ok in Leonardo
Spectrum (our previous synthesis tool).
Any help would be appreciated.
Cheers,
Rob.
From webmaster@nillakaes.de Tue Apr 15 08:18:19 2008
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Message-Id: <4804c735$0$584$6e1ede2f@read.cnntp.org>
From: Thorsten Kiefer <webmaster@nillakaes.de>
Subject: Snythesis error
Newsgroups: comp.arch.fpga
Date: Tue, 15 Apr 2008 17:18:19 +0200
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X-Complaints-To: abuse@cnntp.org
Xref: prodigy.net comp.arch.fpga:143626
X-Received-Date: Mon, 21 Apr 2008 19:31:01 EDT (flpi142.ffdc.sbc.com)
Hi,
when I synthesize the following, I get warnings.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity debounce is
generic(N : integer := 20);
port(
clk,reset : in std_logic;
button : in std_logic;
debounced : out std_logic
);
end debounce;
architecture Behavioral of debounce is
type state_type is (s0,s1);
signal state_reg,state_next : state_type;
signal cnt_reg,cnt_next : unsigned(N-1 downto 0);
begin
process(clk,reset)
begin
if reset='1' then
state_reg <= s0;
cnt_reg <= (others => '0');
elsif clk'event and clk='1' then
state_reg <= state_next;
cnt_reg <= cnt_next;
end if;
end process;
process(state_reg,cnt_reg,button)
begin
if state_reg=s0 and cnt_reg=2**N-1 then
state_next <= s1;
cnt_next <= (others=>'0');
elsif state_reg=s0 and button='0' then
state_next <= s0;
cnt_next <= (others=>'0');
elsif state_reg=s0 and button='1' then
state_next <= s0;
cnt_next <= cnt_next + 1;
elsif state_reg=s1 and cnt_reg=2**N-1 then
state_next <= s0;
cnt_next <= (others=>'0');
elsif state_reg=s1 and button='1' then
state_next <= s1;
cnt_next <= (others=>'0');
elsif state_reg=s1 and button='0' then
state_next <= s1;
cnt_next <= cnt_next + 1;
else
state_next <= state_reg;
cnt_next <= cnt_reg;
end if;
end process;
debounced <= '0' when state_reg=s0 else '1';
end Behavioral;
Warnings :
=========================================================================
* Low Level Synthesis *
=========================================================================
WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
combinatorial loop: N5, cnt_next<0>, cnt_next_share0000<0>.
WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
combinatorial loop: cnt_next_share0000<1>, cnt_next<1>.
WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
combinatorial loop: cnt_next<2>, cnt_next_share0000<2>.
WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
combinatorial loop: cnt_next_share0000<3>, cnt_next<3>.
WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
combinatorial loop: cnt_next<4>, cnt_next_share0000<4>.
WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
combinatorial loop: cnt_next<5>, cnt_next_share0000<5>.
WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
combinatorial loop: cnt_next<6>, cnt_next_share0000<6>.
WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
combinatorial loop: cnt_next<7>, cnt_next_share0000<7>.
WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
combinatorial loop: cnt_next<8>, cnt_next_share0000<8>.
WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
combinatorial loop: cnt_next<9>, cnt_next_share0000<9>.
WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
combinatorial loop: cnt_next<10>, cnt_next_share0000<10>.
WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
combinatorial loop: cnt_next<11>, cnt_next_share0000<11>.
WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
combinatorial loop: cnt_next<12>, cnt_next_share0000<12>.
WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
combinatorial loop: cnt_next<13>, cnt_next_share0000<13>.
WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
combinatorial loop: cnt_next<14>, cnt_next_share0000<14>.
WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
combinatorial loop: cnt_next<15>, cnt_next_share0000<15>.
WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
combinatorial loop: cnt_next<16>, cnt_next_share0000<16>.
WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
combinatorial loop: cnt_next_share0000<17>, cnt_next<17>.
WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
combinatorial loop: cnt_next_share0000<18>, cnt_next<18>.
WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
combinatorial loop: cnt_next_share0000<19>, cnt_next<19>.
What does this mean ?
Best Regards
Thorsten
Article: 131201On Apr 15, 6:15 am, Michael <nleah...@gmail.com> wrote: > Howdy - I'm just getting started with FPGAs. In college I remember we > used ModelSim with ISE for FPGA simulation. We were able to get a > license through our school for free. Like a fool I no longer have that > license, so what free options are out there? I saw that there is > something called ModelSim Xilinx Edition III Starter (http://www.xilinx.com/ise/mxe3/download.htm). I can't tell if that is just a > limited feature package, or a time limited package. Is that what I > want? Or is there something else I should be looking at? > > Thanks! > > -Michael Google: It's not just for mail anymore: <http://www.google.com/search? q=free+hdl+simulator>Article: 131202
robquig...@gmail.com wrote: > Hey everyone, > > Im having difficulty with signals that i tie to zero or one (using > Verilog 1'b0, 1'b1 etc) appearing as z's in post synthesis simulation. > They appear fine in pre synthesis simulation, as one or zero depending > on what i specify, but they always appear as z in post synthesis > simulation. > > As a result of this i have pre and post synthesis simulation mismatch > results and also my bit file doesnt work properly on my fpga (Virtex > II). > > I'm using XST in ISE 9.2. > > Is there a way i can have XST take care of this or must i provide a > specific ground signal to a module if i wish to drive a constant zero > or one in a circuit? I've inherited some code with *lots* of zero's > and one's specified like this and it appeared to work ok in Leonardo > Spectrum (our previous synthesis tool). > > Any help would be appreciated. > > > Cheers, > > > > Rob. The Verilog 1s and 0s should work fine. I'd suggest finding the signals in your post-synthesis verilog file. You should find reason for the signals not being strict 1s or 0s. Anything else here on this newsgroup would be conjecture. Find the signals in the file and you find a way to avoid the z.Article: 131203
On Apr 14, 12:12 am, "pdudl...@comcast.net" <pdudl...@comcast.net> wrote: > Hello > > I need a large Virtex-5 FPGA like the SX95T on a PCIe board with DDR2 > memory. HiTech Global has a variety of boards with these features but I > rarely here that company mentioned on this newsgroup. > > Does anyone out there have experience with HiTech Global eval boards? > How is their quality and documentation? > > Any replies about HiTech Global would be very helpful. > > Pete I have experience with one of their V4FX-60-based boards that comes on a PCI card. The board itself was good. There was no active heat dissipation on the board, which would be a problem if a large portion of that FPGA was actively being used. The documentation was pretty decent, so long as you don't mind the Japanese. I did run into problems with the ethernet support on the board since it was entangled with NDA's. They totally omitted the schematics for the FPGA<->PHY connections from the PDFs supplied (unlike Xilinx) and made a statement about having to contact them and Marvell about getting the access to the necessary information to be able to even build an FPGA image using it. Their example was from an old version of EDK, compared to what I was using at the time (8.2 I think). Their example project was also lacking in that not all of the interfaces on the board/FPGA had examples for the connections. Many of Hi-Tech's boards are made by Inrevium (from Japan), and just resold/labeled here in the US by Hi-Tech. HTH, MikeArticle: 131204
Thorsten Kiefer wrote: > Hi, > when I synthesize the following, I get warnings. > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use ieee.numeric_std.all; > > ---- Uncomment the following library declaration if instantiating > ---- any Xilinx primitives in this code. > --library UNISIM; > --use UNISIM.VComponents.all; > > entity debounce is > generic(N : integer := 20); > port( > clk,reset : in std_logic; > button : in std_logic; > debounced : out std_logic > ); > end debounce; > > architecture Behavioral of debounce is > type state_type is (s0,s1); > signal state_reg,state_next : state_type; > signal cnt_reg,cnt_next : unsigned(N-1 downto 0); > begin > process(clk,reset) > begin > if reset='1' then > state_reg <= s0; > cnt_reg <= (others => '0'); > elsif clk'event and clk='1' then > state_reg <= state_next; > cnt_reg <= cnt_next; > end if; > end process; > > process(state_reg,cnt_reg,button) > begin > if state_reg=s0 and cnt_reg=2**N-1 then > state_next <= s1; > cnt_next <= (others=>'0'); > elsif state_reg=s0 and button='0' then > state_next <= s0; > cnt_next <= (others=>'0'); > elsif state_reg=s0 and button='1' then > state_next <= s0; > cnt_next <= cnt_next + 1; > elsif state_reg=s1 and cnt_reg=2**N-1 then > state_next <= s0; > cnt_next <= (others=>'0'); > elsif state_reg=s1 and button='1' then > state_next <= s1; > cnt_next <= (others=>'0'); > elsif state_reg=s1 and button='0' then > state_next <= s1; > cnt_next <= cnt_next + 1; > else > state_next <= state_reg; > cnt_next <= cnt_reg; > end if; > end process; > > debounced <= '0' when state_reg=s0 else '1'; > end Behavioral; > > > Warnings : > ========================================================================= > * Low Level Synthesis * > ========================================================================= > WARNING:Xst:2170 - Unit debounce : the following signal(s) form a > combinatorial loop: N5, cnt_next<0>, cnt_next_share0000<0>. > WARNING:Xst:2170 - Unit debounce : the following signal(s) form a > combinatorial loop: cnt_next_share0000<1>, cnt_next<1>. > WARNING:Xst:2170 - Unit debounce : the following signal(s) form a > combinatorial loop: cnt_next<2>, cnt_next_share0000<2>. > WARNING:Xst:2170 - Unit debounce : the following signal(s) form a > combinatorial loop: cnt_next_share0000<3>, cnt_next<3>. > WARNING:Xst:2170 - Unit debounce : the following signal(s) form a > combinatorial loop: cnt_next<4>, cnt_next_share0000<4>. > WARNING:Xst:2170 - Unit debounce : the following signal(s) form a > combinatorial loop: cnt_next<5>, cnt_next_share0000<5>. > WARNING:Xst:2170 - Unit debounce : the following signal(s) form a > combinatorial loop: cnt_next<6>, cnt_next_share0000<6>. > WARNING:Xst:2170 - Unit debounce : the following signal(s) form a > combinatorial loop: cnt_next<7>, cnt_next_share0000<7>. > WARNING:Xst:2170 - Unit debounce : the following signal(s) form a > combinatorial loop: cnt_next<8>, cnt_next_share0000<8>. > WARNING:Xst:2170 - Unit debounce : the following signal(s) form a > combinatorial loop: cnt_next<9>, cnt_next_share0000<9>. > WARNING:Xst:2170 - Unit debounce : the following signal(s) form a > combinatorial loop: cnt_next<10>, cnt_next_share0000<10>. > WARNING:Xst:2170 - Unit debounce : the following signal(s) form a > combinatorial loop: cnt_next<11>, cnt_next_share0000<11>. > WARNING:Xst:2170 - Unit debounce : the following signal(s) form a > combinatorial loop: cnt_next<12>, cnt_next_share0000<12>. > WARNING:Xst:2170 - Unit debounce : the following signal(s) form a > combinatorial loop: cnt_next<13>, cnt_next_share0000<13>. > WARNING:Xst:2170 - Unit debounce : the following signal(s) form a > combinatorial loop: cnt_next<14>, cnt_next_share0000<14>. > WARNING:Xst:2170 - Unit debounce : the following signal(s) form a > combinatorial loop: cnt_next<15>, cnt_next_share0000<15>. > WARNING:Xst:2170 - Unit debounce : the following signal(s) form a > combinatorial loop: cnt_next<16>, cnt_next_share0000<16>. > WARNING:Xst:2170 - Unit debounce : the following signal(s) form a > combinatorial loop: cnt_next_share0000<17>, cnt_next<17>. > WARNING:Xst:2170 - Unit debounce : the following signal(s) form a > combinatorial loop: cnt_next_share0000<18>, cnt_next<18>. > WARNING:Xst:2170 - Unit debounce : the following signal(s) form a > combinatorial loop: cnt_next_share0000<19>, cnt_next<19>. > > > What does this mean ? > > Best Regards > Thorsten You have two instances of cnt_next <= cnt_next + 1 where you probably want cnt_next <= cnt_reg + 1. Happy coding! From webmaster@nillakaes.de Tue Apr 15 09:05:44 2008 Path: flpi142.ffdc.sbc.com!flpi104.ffdc.sbc.com!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!goblin2!goblin1!goblin.stu.neva.ru!news.albasani.net!news01.khis.de!feed.cnntp.org!news.cnntp.org!not-for-mail Message-Id: <4804d251$0$584$6e1ede2f@read.cnntp.org> From: Thorsten Kiefer <webmaster@nillakaes.de> Subject: Re: Snythesis error Newsgroups: comp.arch.fpga Date: Tue, 15 Apr 2008 18:05:44 +0200 References: <4804c735$0$584$6e1ede2f@read.cnntp.org> <3f2fced8-70ac-4a2d-90eb-f4def5b617f2@f36g2000hsa.googlegroups.com> User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 128 Organization: CNNTP NNTP-Posting-Host: 10033538.read.cnntp.org X-Trace: DXC=WDEdAMDm76BOag@kJQ3=^DWoT\PAgXa?AY70?_8WM9WM1P5d:S1^>6CdlT:^LKmYjJObd_DO9=BZGSR5>dB75[iO X-Complaints-To: abuse@cnntp.org Xref: prodigy.net comp.arch.fpga:143631 X-Received-Date: Mon, 21 Apr 2008 19:25:42 EDT (flpi142.ffdc.sbc.com) John_H wrote: > Thorsten Kiefer wrote: >> Hi, >> when I synthesize the following, I get warnings. >> >> library IEEE; >> use IEEE.STD_LOGIC_1164.ALL; >> use ieee.numeric_std.all; >> >> ---- Uncomment the following library declaration if instantiating >> ---- any Xilinx primitives in this code. >> --library UNISIM; >> --use UNISIM.VComponents.all; >> >> entity debounce is >> generic(N : integer := 20); >> port( >> clk,reset : in std_logic; >> button : in std_logic; >> debounced : out std_logic >> ); >> end debounce; >> >> architecture Behavioral of debounce is >> type state_type is (s0,s1); >> signal state_reg,state_next : state_type; >> signal cnt_reg,cnt_next : unsigned(N-1 downto 0); >> begin >> process(clk,reset) >> begin >> if reset='1' then >> state_reg <= s0; >> cnt_reg <= (others => '0'); >> elsif clk'event and clk='1' then >> state_reg <= state_next; >> cnt_reg <= cnt_next; >> end if; >> end process; >> >> process(state_reg,cnt_reg,button) >> begin >> if state_reg=s0 and cnt_reg=2**N-1 then >> state_next <= s1; >> cnt_next <= (others=>'0'); >> elsif state_reg=s0 and button='0' then >> state_next <= s0; >> cnt_next <= (others=>'0'); >> elsif state_reg=s0 and button='1' then >> state_next <= s0; >> cnt_next <= cnt_next + 1; >> elsif state_reg=s1 and cnt_reg=2**N-1 then >> state_next <= s0; >> cnt_next <= (others=>'0'); >> elsif state_reg=s1 and button='1' then >> state_next <= s1; >> cnt_next <= (others=>'0'); >> elsif state_reg=s1 and button='0' then >> state_next <= s1; >> cnt_next <= cnt_next + 1; >> else >> state_next <= state_reg; >> cnt_next <= cnt_reg; >> end if; >> end process; >> >> debounced <= '0' when state_reg=s0 else '1'; >> end Behavioral; >> >> >> Warnings : >> ========================================================================= >> * Low Level Synthesis * >> ========================================================================= >> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a >> combinatorial loop: N5, cnt_next<0>, cnt_next_share0000<0>. >> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a >> combinatorial loop: cnt_next_share0000<1>, cnt_next<1>. >> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a >> combinatorial loop: cnt_next<2>, cnt_next_share0000<2>. >> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a >> combinatorial loop: cnt_next_share0000<3>, cnt_next<3>. >> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a >> combinatorial loop: cnt_next<4>, cnt_next_share0000<4>. >> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a >> combinatorial loop: cnt_next<5>, cnt_next_share0000<5>. >> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a >> combinatorial loop: cnt_next<6>, cnt_next_share0000<6>. >> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a >> combinatorial loop: cnt_next<7>, cnt_next_share0000<7>. >> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a >> combinatorial loop: cnt_next<8>, cnt_next_share0000<8>. >> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a >> combinatorial loop: cnt_next<9>, cnt_next_share0000<9>. >> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a >> combinatorial loop: cnt_next<10>, cnt_next_share0000<10>. >> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a >> combinatorial loop: cnt_next<11>, cnt_next_share0000<11>. >> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a >> combinatorial loop: cnt_next<12>, cnt_next_share0000<12>. >> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a >> combinatorial loop: cnt_next<13>, cnt_next_share0000<13>. >> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a >> combinatorial loop: cnt_next<14>, cnt_next_share0000<14>. >> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a >> combinatorial loop: cnt_next<15>, cnt_next_share0000<15>. >> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a >> combinatorial loop: cnt_next<16>, cnt_next_share0000<16>. >> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a >> combinatorial loop: cnt_next_share0000<17>, cnt_next<17>. >> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a >> combinatorial loop: cnt_next_share0000<18>, cnt_next<18>. >> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a >> combinatorial loop: cnt_next_share0000<19>, cnt_next<19>. >> >> >> What does this mean ? >> >> Best Regards >> Thorsten > > You have two instances of cnt_next <= cnt_next + 1 where you probably > want cnt_next <= cnt_reg + 1. > > Happy coding! THX !!Article: 131205
Michael wrote: > Howdy - I'm just beginning with FPGAs. I am using a Spartan 3E Starter > Kit with Xilinx ISE. I am an electrical engineer by training and did > some verilog in my collegiate days - but that was quite some time ago > and it is all very fuzzy now. I have decided that as an EE I should be > familiar with FPGAs - so I'm re-educating myself. With that said - > which would be more useful to learn in the industrial world: Verilog > or VHDL? > > Thanks! > > -Michael Verilog is better, but VHDL is used more in FPGAs. SystemVerilog (a Verilog superset) is the future, but in the FPGA world, the future is often further away than you'd think. (Verilog-2001 features are still lacking in some tools.) The far future is sequential C-to-gates. Teach that to your grandchildren. -KevinArticle: 131206
> process(state_reg,cnt_reg,button) > begin > if state_reg=s0 and cnt_reg=2**N-1 then > state_next <= s1; > cnt_next <= (others=>'0'); > elsif state_reg=s0 and button='0' then > state_next <= s0; > cnt_next <= (others=>'0'); > elsif state_reg=s0 and button='1' then > state_next <= s0; > cnt_next <= cnt_next + 1; > I think the line above shows how the combinatorial loop is formed, because you're making a value in a combinatorial process a function of itself. I think what you really want is: > cnt_next <= cnt_reg + 1; I recommend putting the whole state machine in a single clocked process. It makes the state machine easier to maintain and then you avoid having two names for registers and you avoid having combinatorial loops. One side effect is that actions happen not in the named state but during the next state. -KevinArticle: 131207
Michael wrote: > Howdy - I'm just getting started with FPGAs. In college I remember we > used ModelSim with ISE for FPGA simulation. We were able to get a > license through our school for free. Like a fool I no longer have that > license, so what free options are out there? I saw that there is > something called ModelSim Xilinx Edition III Starter (http:// > www.xilinx.com/ise/mxe3/download.htm). I can't tell if that is just a > limited feature package, or a time limited package. Is that what I > want? Or is there something else I should be looking at? > > Thanks! > > -Michael The ModelSim starter is limited. I think the main limitation is that it is programmed to get radically slower as the number of lines of HDL increases. -KevinArticle: 131208
On Apr 15, 11:34=A0am, ghel...@lycos.com wrote: > On Apr 15, 6:15 am, Michael <nleah...@gmail.com> wrote: > > > Howdy - I'm just getting started with FPGAs. In college I remember we > > used ModelSim with ISE for FPGA simulation. We were able to get a > > license through our school for free. Like a fool I no longer have that > > license, so what free options are out there? I saw that there is > > something called ModelSim Xilinx Edition III Starter (http://www.xilinx.= com/ise/mxe3/download.htm). I can't tell if that is just a > > limited feature package, or a time limited package. Is that what I > > want? Or is there something else I should be looking at? > > > Thanks! > > > -Michael > > Google: =A0It's not just for mail anymore: <http://www.google.com/search? > q=3Dfree+hdl+simulator> I'm aware that there are many free simulators out there - but do any of them interface with ISE like ModelSim does? Also, I noticed that there is also the ModelSim PE Student Edition. I suspect I still qualify as a student - so maybe that is the best choice? -MichaelArticle: 131209
On Apr 15, 8:18 am, Thorsten Kiefer <webmas...@nillakaes.de> wrote: > Hi, > when I synthesize the following, I get warnings. > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use ieee.numeric_std.all; > > ---- Uncomment the following library declaration if instantiating > ---- any Xilinx primitives in this code. > --library UNISIM; > --use UNISIM.VComponents.all; > > entity debounce is > generic(N : integer := 20); > port( > clk,reset : in std_logic; > button : in std_logic; > debounced : out std_logic > ); > end debounce; > > architecture Behavioral of debounce is > type state_type is (s0,s1); > signal state_reg,state_next : state_type; > signal cnt_reg,cnt_next : unsigned(N-1 downto 0); > begin > process(clk,reset) > begin > if reset='1' then > state_reg <= s0; > cnt_reg <= (others => '0'); > elsif clk'event and clk='1' then > state_reg <= state_next; > cnt_reg <= cnt_next; > end if; > end process; > > process(state_reg,cnt_reg,button) > begin > if state_reg=s0 and cnt_reg=2**N-1 then > state_next <= s1; > cnt_next <= (others=>'0'); > elsif state_reg=s0 and button='0' then > state_next <= s0; > cnt_next <= (others=>'0'); > elsif state_reg=s0 and button='1' then > state_next <= s0; > cnt_next <= cnt_next + 1; > elsif state_reg=s1 and cnt_reg=2**N-1 then > state_next <= s0; > cnt_next <= (others=>'0'); > elsif state_reg=s1 and button='1' then > state_next <= s1; > cnt_next <= (others=>'0'); > elsif state_reg=s1 and button='0' then > state_next <= s1; > cnt_next <= cnt_next + 1; > else > state_next <= state_reg; > cnt_next <= cnt_reg; > end if; > end process; > > debounced <= '0' when state_reg=s0 else '1'; > end Behavioral; > > Warnings : > ========================================================================= > * Low Level Synthesis * > ========================================================================= > WARNING:Xst:2170 - Unit debounce : the following signal(s) form a > combinatorial loop: N5, cnt_next<0>, cnt_next_share0000<0>. > WARNING:Xst:2170 - Unit debounce : the following signal(s) form a > combinatorial loop: cnt_next_share0000<1>, cnt_next<1>. > WARNING:Xst:2170 - Unit debounce : the following signal(s) form a > combinatorial loop: cnt_next<2>, cnt_next_share0000<2>. > WARNING:Xst:2170 - Unit debounce : the following signal(s) form a > combinatorial loop: cnt_next_share0000<3>, cnt_next<3>. > WARNING:Xst:2170 - Unit debounce : the following signal(s) form a > combinatorial loop: cnt_next<4>, cnt_next_share0000<4>. > WARNING:Xst:2170 - Unit debounce : the following signal(s) form a > combinatorial loop: cnt_next<5>, cnt_next_share0000<5>. > WARNING:Xst:2170 - Unit debounce : the following signal(s) form a > combinatorial loop: cnt_next<6>, cnt_next_share0000<6>. > WARNING:Xst:2170 - Unit debounce : the following signal(s) form a > combinatorial loop: cnt_next<7>, cnt_next_share0000<7>. > WARNING:Xst:2170 - Unit debounce : the following signal(s) form a > combinatorial loop: cnt_next<8>, cnt_next_share0000<8>. > WARNING:Xst:2170 - Unit debounce : the following signal(s) form a > combinatorial loop: cnt_next<9>, cnt_next_share0000<9>. > WARNING:Xst:2170 - Unit debounce : the following signal(s) form a > combinatorial loop: cnt_next<10>, cnt_next_share0000<10>. > WARNING:Xst:2170 - Unit debounce : the following signal(s) form a > combinatorial loop: cnt_next<11>, cnt_next_share0000<11>. > WARNING:Xst:2170 - Unit debounce : the following signal(s) form a > combinatorial loop: cnt_next<12>, cnt_next_share0000<12>. > WARNING:Xst:2170 - Unit debounce : the following signal(s) form a > combinatorial loop: cnt_next<13>, cnt_next_share0000<13>. > WARNING:Xst:2170 - Unit debounce : the following signal(s) form a > combinatorial loop: cnt_next<14>, cnt_next_share0000<14>. > WARNING:Xst:2170 - Unit debounce : the following signal(s) form a > combinatorial loop: cnt_next<15>, cnt_next_share0000<15>. > WARNING:Xst:2170 - Unit debounce : the following signal(s) form a > combinatorial loop: cnt_next<16>, cnt_next_share0000<16>. > WARNING:Xst:2170 - Unit debounce : the following signal(s) form a > combinatorial loop: cnt_next_share0000<17>, cnt_next<17>. > WARNING:Xst:2170 - Unit debounce : the following signal(s) form a > combinatorial loop: cnt_next_share0000<18>, cnt_next<18>. > WARNING:Xst:2170 - Unit debounce : the following signal(s) form a > combinatorial loop: cnt_next_share0000<19>, cnt_next<19>. > > What does this mean ? cnt_next is never registered. Don't use the two-process state machine description. It leads to exactly the problem you have. -aArticle: 131210
"Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message news:fu2ku0$aep3@cnn.xsj.xilinx.com... > Michael wrote: >> Howdy - I'm just getting started with FPGAs. In college I remember we >> used ModelSim with ISE for FPGA simulation. We were able to get a >> license through our school for free. Like a fool I no longer have that >> license, so what free options are out there? I saw that there is >> something called ModelSim Xilinx Edition III Starter (http:// >> www.xilinx.com/ise/mxe3/download.htm). I can't tell if that is just a >> limited feature package, or a time limited package. Is that what I >> want? Or is there something else I should be looking at? >> >> Thanks! >> >> -Michael > > The ModelSim starter is limited. I think the main limitation is that it > is programmed to get radically slower as the number of lines of HDL > increases. -Kevin Starter edition slows down to 1% of PE (basically grinds to a halt) after 10000 lines (executable lines), below 10000 lines it operates at 30% of PE. MXE3 edition operates at 40% of PE and slows down to 1% after 50000 lines. There is no swift, mixed language or SystemC support in either version. Hans www.ht-lab.comArticle: 131211
On Tue, 15 Apr 2008 07:49:23 -0700 (PDT), robquigley@gmail.com wrote: >Hey everyone, > >Im having difficulty with signals that i tie to zero or one (using >Verilog 1'b0, 1'b1 etc) appearing as z's in post synthesis simulation. >They appear fine in pre synthesis simulation, as one or zero depending >on what i specify, but they always appear as z in post synthesis >simulation. > Depending on how the optimization is done, it is possible that the constants are propagated to where they are used to leave the original nets unused/unconnected; this may be your problem. >As a result of this i have pre and post synthesis simulation mismatch >results and also my bit file doesnt work properly on my fpga (Virtex >II). This may not necessarily be the case. Before you blame the tool, look at your check list and see if any check marks are missing? (you say you don't have a check list, here is a sample: did you run STA?, do you meet timing? did you constrain your multi-cycle paths correctly? did you make sure all asynch paths are managed safely and all async path flops are turned off for back-annotated simulations? I am sure many can be added to this list) Another item you can check is to look at the gate level and find a node where any of your constant signals would be used. If you can find a simple enough logic implementation you can verify for yourself that the constant net is not needed in the logic and that the constant has been already inserted into the logic before optimization.Article: 131212
On Apr 15, 12:43=A0pm, "HT-Lab" <han...@ht-lab.com> wrote: > "Kevin Neilson" <kevin_neil...@removethiscomcast.net> wrote in message > > news:fu2ku0$aep3@cnn.xsj.xilinx.com... > > > > > > > Michael wrote: > >> Howdy - I'm just getting started with FPGAs. In college I remember we > >> used ModelSim with ISE for FPGA simulation. We were able to get a > >> license through our school for free. Like a fool I no longer have that > >> license, so what free options are out there? I saw that there is > >> something called ModelSim Xilinx Edition III Starter (http:// > >>www.xilinx.com/ise/mxe3/download.htm). I can't tell if that is just a > >> limited feature package, or a time limited package. Is that what I > >> want? Or is there something else I should be looking at? > > >> Thanks! > > >> -Michael > > > The ModelSim starter is limited. =A0I think the main limitation is that = it > > is programmed to get radically slower as the number of lines of HDL > > increases. =A0-Kevin > > Starter edition slows down to 1% of PE (basically grinds to a halt) after > 10000 lines (executable lines), below 10000 lines it operates at 30% of PE= . > > MXE3 edition operates at 40% of PE and slows down to 1% after 50000 lines.= > > There is no swift, mixed language or SystemC support in either version. > > Hanswww.ht-lab.com Hi Hans - thanks for the information. I'm not terribly worried about speed at the moment - I'm just trying to learn the basics for now. Do you know how the student edition (http://www.model.com/resources/ student_edition/student_default.asp) compares to these? It can't handle mixed HDL designs which seems a bit of a handicap - but I can work around that. I couldn't find any mention of a limit on speed or the number of executable lines. Also - is there a Xilinx simulator that is built into ISE? I am following a Xilinx tutorial (http://www.xilinx.com/support/techsup/ tutorials/tutorials9.htm) and it first says "Whether you use the ModelSim simulator or the ISE Simulator with this tutorial, you will achieve the same results." suggesting there is a fully functional tutorial built into ISE, and then two paragraphs down it says "In order to use this tutorial, you must install ModelSim on your computer.". So that just confused me. Thanks! -MichaelArticle: 131213
> Also - is there a Xilinx simulator that is built into ISE? I am > following a Xilinx tutorial (http://www.xilinx.com/support/techsup/ > tutorials/tutorials9.htm) and it first says "Whether you use > the ModelSim simulator or the ISE Simulator with this tutorial, you > will achieve the same results." suggesting there is a fully functional > tutorial built into ISE, and then two paragraphs down it says "In > order to use this tutorial, you must install ModelSim on your > computer.". So that just confused me. > > Thanks! > > -Michael The most recent version of ISIM (the ISE simulator) is much faster and has a new parser so it supports the language(s) much better. The user interface is a bit coarser and the waveform viewer is not as nice as Modelsim's, but it might work well for you. I didn't consider this because it's not really free, since ISE isn't free, but if you already have ISE it might be a good option. -KevinArticle: 131214
Michael wrote: > Howdy - I'm just beginning with FPGAs. I am using a Spartan 3E Starter > Kit with Xilinx ISE. I am an electrical engineer by training and did > some verilog in my collegiate days - but that was quite some time ago > and it is all very fuzzy now. I have decided that as an EE I should be > familiar with FPGAs - so I'm re-educating myself. With that said - > which would be more useful to learn in the industrial world: Verilog > or VHDL? > > Thanks! > > -Michael I personally found verilog very intuitive with my software engineering background. VHDL on the other hand seems weird to me. YMMY. FeiArticle: 131215
On Apr 15, 2:10=A0pm, Kevin Neilson <kevin_neil...@removethiscomcast.net> wrote: > > Also - is there a Xilinx simulator that is built into ISE? I am > > following a Xilinx tutorial (http://www.xilinx.com/support/techsup/ > > tutorials/tutorials9.htm) and it first says "Whether you use > > the ModelSim simulator or the ISE Simulator with this tutorial, you > > will achieve the same results." suggesting there is a fully functional > > tutorial built into ISE, and then two paragraphs down it says "In > > order to use this tutorial, you must install ModelSim on your > > computer.". So that just confused me. > > > Thanks! > > > -Michael > > The most recent version of ISIM (the ISE simulator) is much faster and > has a new parser so it supports the language(s) much better. =A0The user > interface is a bit coarser and the waveform viewer is not as nice as > Modelsim's, but it might work well for you. =A0I didn't consider this > because it's not really free, since ISE isn't free, but if you already > have ISE it might be a good option. =A0-Kevin I'm confused - I just downloaded the "ISE WebPACK 9.2i" a couple days ago and didn't pay a thing. (and it never asked me to pay a thing). Does this have a built in simulator, or is it only the version that you pay for that has a built in simulator? Thanks, -MichaelArticle: 131216
Hi, You can use Tcl script. ISE10.1 can generate it for you : "Tcl Script Generation: Project Navigator can generate a Tcl script that contains all the necessary Tcl commands to create, modify, and implement your project from a Tcl command prompt. To generate this script, select Project > Generate Tcl Script..." See also http://www.xilinx.com/products/design_tools/logic_design/implementation/ise_qrefguide.pdf Regards From webmaster@nillakaes.de Tue Apr 15 12:00:20 2008 Path: flpi142.ffdc.sbc.com!flpi104.ffdc.sbc.com!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!goblin2!goblin.stu.neva.ru!feed20.multikabel.net!multikabel.net!feed10.multikabel.net!feeder.news-service.com!news.motzarella.org!motzarella.org!feed.cnntp.org!news.cnntp.org!not-for-mail Message-Id: <4804fb76$0$584$6e1ede2f@read.cnntp.org> From: Thorsten Kiefer <webmaster@nillakaes.de> Subject: Re: Snythesis error Newsgroups: comp.arch.fpga Date: Tue, 15 Apr 2008 21:00:20 +0200 References: <4804c735$0$584$6e1ede2f@read.cnntp.org> <c9db330a-abe5-467b-9559-d92dfe8706e9@1g2000prf.googlegroups.com> User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 127 Organization: CNNTP NNTP-Posting-Host: 36bed3b3.read.cnntp.org X-Trace: DXC=Y^_URDDe4o^hIm;o<VC`>UWoT\PAgXa?QY70?_8WM9W]1P5d:S1^>6SdlT:^LKmYjZlMLY:\>gY0PVJ@RQDmEb[W X-Complaints-To: abuse@cnntp.org Xref: prodigy.net comp.arch.fpga:143644 X-Received-Date: Mon, 21 Apr 2008 19:30:05 EDT (flpi142.ffdc.sbc.com) Andy Peters wrote: > On Apr 15, 8:18 am, Thorsten Kiefer <webmas...@nillakaes.de> wrote: >> Hi, >> when I synthesize the following, I get warnings. >> >> library IEEE; >> use IEEE.STD_LOGIC_1164.ALL; >> use ieee.numeric_std.all; >> >> ---- Uncomment the following library declaration if instantiating >> ---- any Xilinx primitives in this code. >> --library UNISIM; >> --use UNISIM.VComponents.all; >> >> entity debounce is >> generic(N : integer := 20); >> port( >> clk,reset : in std_logic; >> button : in std_logic; >> debounced : out std_logic >> ); >> end debounce; >> >> architecture Behavioral of debounce is >> type state_type is (s0,s1); >> signal state_reg,state_next : state_type; >> signal cnt_reg,cnt_next : unsigned(N-1 downto 0); >> begin >> process(clk,reset) >> begin >> if reset='1' then >> state_reg <= s0; >> cnt_reg <= (others => '0'); >> elsif clk'event and clk='1' then >> state_reg <= state_next; >> cnt_reg <= cnt_next; >> end if; >> end process; >> >> process(state_reg,cnt_reg,button) >> begin >> if state_reg=s0 and cnt_reg=2**N-1 then >> state_next <= s1; >> cnt_next <= (others=>'0'); >> elsif state_reg=s0 and button='0' then >> state_next <= s0; >> cnt_next <= (others=>'0'); >> elsif state_reg=s0 and button='1' then >> state_next <= s0; >> cnt_next <= cnt_next + 1; >> elsif state_reg=s1 and cnt_reg=2**N-1 then >> state_next <= s0; >> cnt_next <= (others=>'0'); >> elsif state_reg=s1 and button='1' then >> state_next <= s1; >> cnt_next <= (others=>'0'); >> elsif state_reg=s1 and button='0' then >> state_next <= s1; >> cnt_next <= cnt_next + 1; >> else >> state_next <= state_reg; >> cnt_next <= cnt_reg; >> end if; >> end process; >> >> debounced <= '0' when state_reg=s0 else '1'; >> end Behavioral; >> >> Warnings : >> ========================================================================= >> * Low Level Synthesis * >> ========================================================================= >> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a >> combinatorial loop: N5, cnt_next<0>, cnt_next_share0000<0>. >> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a >> combinatorial loop: cnt_next_share0000<1>, cnt_next<1>. >> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a >> combinatorial loop: cnt_next<2>, cnt_next_share0000<2>. >> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a >> combinatorial loop: cnt_next_share0000<3>, cnt_next<3>. >> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a >> combinatorial loop: cnt_next<4>, cnt_next_share0000<4>. >> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a >> combinatorial loop: cnt_next<5>, cnt_next_share0000<5>. >> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a >> combinatorial loop: cnt_next<6>, cnt_next_share0000<6>. >> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a >> combinatorial loop: cnt_next<7>, cnt_next_share0000<7>. >> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a >> combinatorial loop: cnt_next<8>, cnt_next_share0000<8>. >> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a >> combinatorial loop: cnt_next<9>, cnt_next_share0000<9>. >> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a >> combinatorial loop: cnt_next<10>, cnt_next_share0000<10>. >> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a >> combinatorial loop: cnt_next<11>, cnt_next_share0000<11>. >> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a >> combinatorial loop: cnt_next<12>, cnt_next_share0000<12>. >> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a >> combinatorial loop: cnt_next<13>, cnt_next_share0000<13>. >> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a >> combinatorial loop: cnt_next<14>, cnt_next_share0000<14>. >> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a >> combinatorial loop: cnt_next<15>, cnt_next_share0000<15>. >> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a >> combinatorial loop: cnt_next<16>, cnt_next_share0000<16>. >> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a >> combinatorial loop: cnt_next_share0000<17>, cnt_next<17>. >> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a >> combinatorial loop: cnt_next_share0000<18>, cnt_next<18>. >> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a >> combinatorial loop: cnt_next_share0000<19>, cnt_next<19>. >> >> What does this mean ? > > cnt_next is never registered. > > Don't use the two-process state machine description. It leads to > exactly the problem you have. > > -a Is the a concurrent statement for the next-state-logic better ? But what if the "next-state logic" becomes more complex ?Article: 131217
---------- Forwarded message ----------
From: Priyantha De Silva <priyanthads@gmail.com>
Date: Wed, Apr 16, 2008 at 2:26 AM
Subject: Inconsistent File Reading/writing in binary format using
MicroBlaze
To: Shakith Fernando <shakith.fernando@gmail.com>
Hi,
I'm trying to read a file from Compact Flash Card in MPEG-4 file in
binary format on MicroBlaze. Then Decode it and write output to CF
card in binary format. Although functioning on PC the output on PC is
correct, output on Micro-blaze is inconsistent.
A snippet of the code is as follows
SYSACE_FILE *outfile;
SYSACE_FILE *writefile;
......
if ((outfile = sysace_fopen("stream.txt", "r")) == NULL) {
xil_printf("Couldn't open the file\r\n");
}
else{
xil_printf("Testing 1\n");
sysace_fread( (void *) mybuf, 1, 1, outfile);
......
if ((writefile = sysace_fopen("outfile.txt", "w")) == NULL) {
xil_printf("Couldn't open the file\r\n");
}
else{
xil_printf("Testing 3\n");}
sysace_fwrite((char*)buf[0],1, 2*cw, writefile2);
}
}
Specification
EDK version:8.2.02i
FPGA Board: Virtex II Pro
Is it due to fact as data is read as char? Or Little Endian/ Big
Endian issue? Any thoughts on the matter?
Priyantha
From webmaster@nillakaes.de Tue Apr 15 12:03:14 2008
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Message-Id: <4804fbec$0$584$6e1ede2f@read.cnntp.org>
From: Thorsten Kiefer <webmaster@nillakaes.de>
Subject: Re: Snythesis error
Newsgroups: comp.arch.fpga
Date: Tue, 15 Apr 2008 21:03:14 +0200
References: <4804c735$0$584$6e1ede2f@read.cnntp.org> <fu2kor$aep2@cnn.xsj.xilinx.com>
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X-Complaints-To: abuse@cnntp.org
Xref: prodigy.net comp.arch.fpga:143646
X-Received-Date: Mon, 21 Apr 2008 19:30:06 EDT (flpi142.ffdc.sbc.com)
Kevin Neilson wrote:
>
>> process(state_reg,cnt_reg,button)
>> begin
>> if state_reg=s0 and cnt_reg=2**N-1 then
>> state_next <= s1;
>> cnt_next <= (others=>'0');
>> elsif state_reg=s0 and button='0' then
>> state_next <= s0;
>> cnt_next <= (others=>'0');
>> elsif state_reg=s0 and button='1' then
>> state_next <= s0;
>> cnt_next <= cnt_next + 1;
>
>>
> I think the line above shows how the combinatorial loop is formed,
> because you're making a value in a combinatorial process a function of
> itself. I think what you really want is:
>
> > cnt_next <= cnt_reg + 1;
>
> I recommend putting the whole state machine in a single clocked process.
> It makes the state machine easier to maintain and then you avoid
> having two names for registers and you avoid having combinatorial loops.
> One side effect is that actions happen not in the named state but
> during the next state.
> -Kevin
can you convert that little example into a single process ?
I have no idea how to do that...
My book says, the state machine has to be separated
into "register/flipflop","next-state logic" and "output logic"
-TK
Article: 131218"Michael" <nleahcim@gmail.com> wrote in message news:d46de822-ec69-411f-9c02-1d98727b9f46@d26g2000prg.googlegroups.com... On Apr 15, 12:43 pm, "HT-Lab" <han...@ht-lab.com> wrote: > "Kevin Neilson" <kevin_neil...@removethiscomcast.net> wrote in message > > news:fu2ku0$aep3@cnn.xsj.xilinx.com... > > > > > > > Michael wrote: > >> Howdy - I'm just getting started with FPGAs. In college I remember we > >> used ModelSim with ISE for FPGA simulation. We were able to get a > >> license through our school for free. Like a fool I no longer have that > >> license, so what free options are out there? I saw that there is > >> something called ModelSim Xilinx Edition III Starter (http:// > >>www.xilinx.com/ise/mxe3/download.htm). I can't tell if that is just a > >> limited feature package, or a time limited package. Is that what I > >> want? Or is there something else I should be looking at? > > >> Thanks! > > >> -Michael > > > The ModelSim starter is limited. I think the main limitation is that it > > is programmed to get radically slower as the number of lines of HDL > > increases. -Kevin > > Starter edition slows down to 1% of PE (basically grinds to a halt) after > 10000 lines (executable lines), below 10000 lines it operates at 30% of > PE. > > MXE3 edition operates at 40% of PE and slows down to 1% after 50000 lines. > > There is no swift, mixed language or SystemC support in either version. > > Hanswww.ht-lab.com >Hi Hans - thanks for the information. I'm not terribly worried about >speed at the moment - I'm just trying to learn the basics for now. Do >you know how the student edition (http://www.model.com/resources/ >student_edition/student_default.asp) compares to these? I believe it is the same speed as PE but I am not 100% sure. >It can't handle mixed HDL designs which seems a bit of a handicap - I agree, some companies (I don't want to mention any names *cough*Micron*cough*) decided to only provide models in one language forcing users to spend extra money on a dual language license, perhaps they are sponsored by the EDA industry? :-) Hans www.ht-lab.comArticle: 131219
"Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message news:fu2k7i$aep1@cnn.xsj.xilinx.com... > Michael wrote: >> Howdy - I'm just beginning with FPGAs. I am using a Spartan 3E Starter >> Kit with Xilinx ISE. I am an electrical engineer by training and did >> some verilog in my collegiate days - but that was quite some time ago >> and it is all very fuzzy now. I have decided that as an EE I should be >> familiar with FPGAs - so I'm re-educating myself. With that said - >> which would be more useful to learn in the industrial world: Verilog >> or VHDL? >> >> Thanks! >> >> -Michael > Verilog is better, but VHDL is used more in FPGAs. Statements like this are best described with the help of a bit of multimedia: http://www.youtube.com/watch?v=0PSMr_0qCak Hans www.ht-lab.com > SystemVerilog (a Verilog superset) is the future, but in the FPGA world, > the future is often further away than you'd think. (Verilog-2001 features > are still lacking in some tools.) The far future is sequential > C-to-gates. Teach that to your grandchildren. -KevinArticle: 131220
Thorsten Kiefer wrote:
> can you convert that little example into a single process ?
I do it like this:
main : process(reset, clock) is
-- declarations
begin -- process template
if reset = '1' then
init_regs;
elsif rising_edge(clock) then
update_regs;
end if;
update_ports;
end process main;
end architecture synth;
Details here:
http://home.comcast.net/~mike_treseler/
--Mike Treseler
Article: 131221hi, i have got xilinx fft IP core from coregen. Is there any way that i can get asic gate count for this ? Any help / hint is greatly appreciated. thanks, vijayant.Article: 131222
vijayant.rutgers@gmail.com wrote:
> i have got xilinx fft IP core from coregen. Is there any way that i
> can get asic gate count for this ? Any help / hint is greatly
> appreciated.
An accurate count requires source code.
-- Mike Treseler
Article: 131223Roger <rogerwilson@hotmail.com> wrote: > Thanks for the comments in response to my initial query. It sounds like > there won't be a 64 bit Webpack - which is a shame as the devices covered by > it are sufficient for my work and I've got a PC with Vista 64 bit on it! It's unfortunate that so many people seem to have have this feeling that 64-bit programs are better than 32-bit programs in all cases :P Of course it's also unfortunate that Windows does not support an ILP32 memory model that would utilize the other AMD extensions to the x86 architecure such as the additional registers and register widths. G.Article: 131224
On Apr 14, 9:18 am, Michael <nleah...@gmail.com> wrote: > Howdy - I'm just beginning with FPGAs. I am using a Spartan 3E Starter > Kit with Xilinx ISE. I am an electrical engineer by training and did > some verilog in my collegiate days - but that was quite some time ago > and it is all very fuzzy now. I have decided that as an EE I should be > familiar with FPGAs - so I'm re-educating myself. With that said - > which would be more useful to learn in the industrial world: Verilog > or VHDL? > > Thanks! > > -Michael The syntax for Verilog will be a bit more familiar to you if you program in C/C++. Don't let this keep you from seeing it as synthesizable hardware though. It takes practice to keep from coding garbage that is unsynthesizable. Verilog is also a bit easier with syntax and requires somewhat fewer lines to do the same thing. Also if you know one, the other is pretty easy to read. A book I used as a reference in my Digital ASIC class has great examples of both: Hdl Chip Design: A Practical Guide for Designing, Synthesizing & Simulating Asics & Fpgas Using Vhdl or Verilog by Douglas J. Smith I bought it for $65, amazon has a ridiculous price of $284, WTF? don't get it from them. That said, it is not like C vs Python where the entire philosophy is different. And it is hard to read one vs. the other
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