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It works fine for Webpack 10.1 but does not work for Chipscope. I get the following error on chipscope: COMMAND: open_platform_usb_cable FREQUENCY=6000000 PORT=USB21 INFO: Started ChipScope host (localhost:50001) INFO: Opened socket connection: localhost 50001 localhost/127.0.0.1 INFO: Reusing A0020001 key. INFO: Reusing 24020001 key. INFO: OS platform = i686. INFO: Connecting to cable (Usb Port - USB21). INFO: Checking cable driver. INFO: File version of /opt/Xilinx/10.1/ChipScope/bin/lin/../../xilinx/ bin/lin/xusbdfwu.hex = 1030. INFO: File version of /usr/share/xusbdfwu.hex = 1030. INFO: libusb-driver.so version: 2008-03-29 09:08:41. INFO: Cable connection failed. ERROR: Failed to open Xilinx Platform USB Cable. See message(s) above. I am running Ubuntu GG with a Spartan 3e FPGA. Any suggestions would be appreciatedArticle: 131301
John Larkin wrote: > On Thu, 17 Apr 2008 09:43:09 -0700 (PDT), Dave <dhschetz@gmail.com> > wrote: > >> Does anybody out there have a good methodology for determining your >> optimal FPGA pinouts, for making PCB layouts nice, pretty, and clean? >> The brute force method is fairly maddening. I'd be curious to hear if >> anybody has any 'tricks of the trade' here. > > What's the brute force method? We preassign most fpga pins for clean, > no-crossover routing to other chips. We discuss the general issues, > especially placement, with our pcb layout guy and he actually decides > which pins go where. Then he back-annotates the schematic and gives us > a file we can use to create the fpga pin constraints file. Sometimes > bank issues complicate the process, but it works pretty well. > >> Also, just out of curiosity, how many of you do your own PCB layout, >> versus farming it out? It would certainly save us a lot of money to >> buy the tools and do it ourselves, but it seems like laying out a >> board out well requires quite a bit of experience, especially a 6-8 >> layer board with high pin count FPGA's. > > We'd never farm it out. We do critical mixed-signal stuff, and need to > be near our layout guy constantly. He puts up a version on our server > daily at least, and we keep an eye on progress. And we have a lot of > mini-meetings to change the rules as needed. Besides, we have evolved > some styles (and libraries!) that we couldn't very well transfer to a > service bureau. PCB layout is too important to farm out. > I always farm out the layout. At the most I do a mock layout of, say, a hotrod RF amp area and send it to the layouter. During layout Gerbers go back and forth all the time, sometimes in 15min intervals. Once my layouter had to be in Vermont during the job, no problem. Crunch time, he worked into the night, I had a laptop in the living room and whenever it beeped I'd go into the office, check the Gerbers and reply. Also really nice was a company overseas. I only had to check some critical areas during layout (which was done over there). They used a subversion system so a scattered team could cooperate without accidentally stepping on each others files. It was almost as if their server was here in the basement. >> We're just setting up a hardware shop here, and although I've been >> doing FPGA and board schematics design for a while, it's always been >> at a larger company with resources to farm the layout out, and we >> never did anything high-speed to really worry about the board layout >> too much. Thanks in advance for your opinions. > > > For really critical stuff, sometimes I'll take over and route that > part of the board myself. It's just too hard to communicate exactly > what I want. > Yes, for really hot stuff it's good to sit next to each other. In the past I'd driver over there and me, the layouter and his cat would do the tough parts of the layout together. Unfortunately his cat has passed away by now. -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM.Article: 131302
> How would you tackle such a situation? Any work around? Buy a faster FPGA if possible. Cheers, JonArticle: 131303
"Joerg" <notthisjoergsch@removethispacbell.net> wrote in message news:0SSNj.2092$7Z2.69@newssvr12.news.prodigy.net... > Errr, well, those sure sound like ivory tower statements. For some reason > all the phenolic I ever used has never smelled. Maybe you're missing those receptors in your nose? :-) I've found that phenolic has a much stronger smell than FR-4... not necessarily all that "malodorous" vs. any other common board materials, but definitely a lot more noticeable. > Sometimes I wish that professors had more nose-to-the-grindstone industry > work under the belt. I mean real design work where cost is a big factor. > Otherwise they are going to tell students they should use Rogers for just > about everything ... Yep, that is a problem. Have you been to something like IEEE's MTT-S recently? It really is a different world, and unfortunately the same part of our culture that now says you need a BSEE to be an oscilloscope salesman is, I think, what has made it much more difficult for working engineers to enter academia. Becoming a EE professor is now seen as a career in and of itself, rather to the preclusion of of being a "practicing" engineer where you have significant cost constraints. ---JoelArticle: 131304
lm317t <lm317t@gmail.com> wrote: >For behavioral sim you could go with a brand agnostic tool like ghdl >and iverilog are both free, and I've used them sucessfully for simple >to quite large designs. I find the Xilinx and Altera tools to be too >slow and cumbersome, but I haven't compared those sim tools to ghdl or >iverilog. Interesting. Would it be possible to do a functional simulation based on the post-place & route VHDL file generated by ISE with ghdl? -- Programmeren in Almere? E-mail naar nico@nctdevpuntnl (punt=.)Article: 131305
"David L. Jones" <altzone@gmail.com> wrote in message news:b60473de-efdf-458a-aae3-ebc5ea85b9e6@a1g2000hsb.googlegroups.com... > 5) Hit the "add subnet jumper" feature and it finishes the tracks and > does all the pin swaps for you and updates the schematic. Sounds like a really nice feature, David -- thanks for the tip.Article: 131306
Joel Koltner wrote: > "Joerg" <notthisjoergsch@removethispacbell.net> wrote in message > news:0SSNj.2092$7Z2.69@newssvr12.news.prodigy.net... >> Errr, well, those sure sound like ivory tower statements. For some reason >> all the phenolic I ever used has never smelled. > > Maybe you're missing those receptors in your nose? :-) I've found that > phenolic has a much stronger smell than FR-4... not necessarily all that > "malodorous" vs. any other common board materials, but definitely a lot more > noticeable. > Possibly :-) Just went over to the lab and took a sniff. The really old dark versions might have a wee scent but the newer more light boards don't. The shepherd looked at me quite puzzled when I sniffed the boards. So she took a sniff as well but walked away upon dicovering that it ain't edible. If there were a stench she'd have sneezed. >> Sometimes I wish that professors had more nose-to-the-grindstone industry >> work under the belt. I mean real design work where cost is a big factor. >> Otherwise they are going to tell students they should use Rogers for just >> about everything ... > > Yep, that is a problem. Have you been to something like IEEE's MTT-S > recently? It really is a different world, and unfortunately the same part of > our culture that now says you need a BSEE to be an oscilloscope salesman is, I > think, what has made it much more difficult for working engineers to enter > academia. Becoming a EE professor is now seen as a career in and of itself, > rather to the preclusion of of being a "practicing" engineer where you have > significant cost constraints. > IEEE also needs step onto the real world of engineering, and soon. Else member retention will become a problem. I'd be interested in teaching once I retire but the bureaucratic hurdles are so high that it might have to be in a more private setting, without academic institutions, colleges or schools involved. I am not going to spend thousands on a teaching credential just to appease some bureaucrat. And the students must be motivated, otherwise I won't do it. -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM.Article: 131307
On Apr 18, 7:08=A0am, ratemonotonic <niladri1...@gmail.com> wrote: > Hi All, > > I am new to FPGA development , I have encountered a timing closure > problem and would appreciate some advice from experienced xilinx guys. > > My problem is as follows - > <snip> > when I integrated our modem IP in the FPGA. The ehternet post breaks , > the externla bus transaction are exactly the same , but I cannot read > and write to the external Ehternet MAC Phy chip registers properly > even though the Logic analyser doesnt show any change. > > By changing some timing constriants now we have a working model with > both modules working. But any further changes breaks every thing ( The > flash and SDRAM inteface as well). Obviously we are right on the edge. > > How would you tackle such a situation? Any work around? > You mention that you changed 'some timing constraints' but never said that you have successfully completed static timing analysis. Timing constraints are not just something to change on a whim, they come about because of the timing requirements of the devices to which your design is connected. So I would suggest 1. Complete a full static timing analysis. 2. Fix any paths that are reported as failures. 3. Are there multiple clocks? If so, how are the inevitable clock domain crossings handled? Kevin JenningsArticle: 131308
Joerg wrote: > > I'd be interested in teaching once I retire but the bureaucratic hurdles > are so high that it might have to be in a more private setting, without > academic institutions, colleges or schools involved. I am not going to > spend thousands on a teaching credential just to appease some > bureaucrat. And the students must be motivated, otherwise I won't do it. Teaching doesn't require much in the way of credentials for university level. Getting on the tenure track is an entirely different matter. If you want to teach, head off to see the dean of your local university/community college, and ask what they need. Not much money, but it still can be a very satisfying experience. -ChuckArticle: 131309
Hi,
1) the xparameters.h file does not contain the slot ids like you
mention above. any idea why this is so? I am looking at the file from
the
$PROJECT_DIR/microblaze_0/include directory. How do I go about
fixing this?
2) when I tried writing and reading from the first peripheral with
the putfsl(val,0) and getfsl(val,1) respectively, I have not yet
attached the 2nd peripheral. This is what I was previously doing
peripheral1 ==> write : use command putfsl(val,0) # WORKS OK
read : use command getfsl(val,1) # WORKS OK
peripheral2 ==> write : use command putfsl(val,2) # NOTHING HAPPENS
ON THE BUS
read : use command getfsl(val,3) # NOTHING
HAPPENS ON THE BUS
this seem to work for peripheral1. peripheral2 however cannot be
written to or read from. I verified this using RTL simulation by
generating behavioral model of the system. Now that I have attached
the 2nd fsl peripheral, should i change it in the following way?
peripheral1 ==> write : use command putfsl(val,0)
read : use command getfsl(val,0)
peripheral2 ==> write : use command putfsl(val,1)
read : use command getfsl(val,1)
3) the create peripheral method which you mentioned does not help much
either. It creates default driver files which do not mention anything
about the slot IDs either. the generic drivers merely contains
functions of which you are to supply the slot ID; of which, this I am
not too sure.
please let me know, if there is anyone who has any idea what is going
on...
Chris
Article: 131310On Thu, 17 Apr 2008 17:52:38 -0700, "Joel Koltner" <zapwireDASHgroups@yahoo.com> wrote: >"Joerg" <notthisjoergsch@removethispacbell.net> wrote in message >news:ZjRNj.9697$2g1.9469@nlpi068.nbdc.sbc.com... >> Not anymore. Part of my daily bread is earned salvaging designs where >> someone thought "Oh, it's just slow stuff". But it ain't grampa's old SN7400 >> anymore, today's logic chips are fast. > >OK, ok, good point. Doesn't someone now have a logic family that's purposely >been slowed down due to this "problem?" > [snippage] You can control edge rates (drive current) on FPGAs, at least the Xilinx families we use. Amazing how simple you can make a DDR2 memory interface to a FPGA with a little thought. We get by with no terminations with beautiful looking signals. That saves a lot of power and board area. --- MarkArticle: 131311
Chuck Harris wrote: > Joerg wrote: > >> >> I'd be interested in teaching once I retire but the bureaucratic >> hurdles are so high that it might have to be in a more private >> setting, without academic institutions, colleges or schools involved. >> I am not going to spend thousands on a teaching credential just to >> appease some bureaucrat. And the students must be motivated, otherwise >> I won't do it. > > Teaching doesn't require much in the way of credentials for university > level. > Getting on the tenure track is an entirely different matter. > There shouldn't be any tenure in the first place. There is a reason why the tenure concept does not exist in industry. Just my humble opinion. > If you want to teach, head off to see the dean of your local > university/community > college, and ask what they need. Not much money, but it still can be a > very > satisfying experience. > Some day I will, when I throttle back design work and money (hopefully) isn't a big issue. It doesn't have to be any ritzy school as long as the audience is motivated and the school isn't a huge driving distance away. -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM.Article: 131312
Hello, I am new to this FPGA stuff and I wanted to purchase a starter kit and get volume pricing for a few Xilinx FPGA's If one where to buy through Avnet or maybe NuHorizons, would anyone like to share your past experiences when working with them? It seems all they care are who you are, what company you work with, what you exactly are you doing. In other words, how many parts are you going to buy from us before I spend any time with you. Do you have to be a big company or are they trying to discourage small startups or students or whoever? Like what do you have to purchase, software or hardware or what dollar amount to do you have to purchase just to get few questions answered, sales wise for pricing or even worse, tech support? Thanks.Article: 131313
"Joerg" <notthisjoergsch@removethispacbell.net> wrote in message news:Zv5Oj.4677$iK6.2580@nlpi069.nbdc.sbc.com... > There shouldn't be any tenure in the first place. There is a reason why the > tenure concept does not exist in industry. Just my humble opinion. Doesn't tenure just mean that you have to screw up particularly badly to get fired? And that even after you officially quit teaching/researching you're generally still allowed to come and play in the lab and perhaps have an office? Or is there more to it than that? I was asked to write a letter of recommendation for a professor I had to turn him from an assistant professor into a full-fledged (and perhaps tenure track?) professor. He's a good teacher so I was happy to do it, but I found it a little odd that the professor in charge of this whole process said, "If you don't feel you can write a letter that presents [this guy] in a positive light, it's OK -- let me know and we'll find someone else." Hmmm....! > Some day I will, when I throttle back design work and money (hopefully) > isn't a big issue. It doesn't have to be any ritzy school as long as the > audience is motivated and the school isn't a huge driving distance away. These days "distance learning" is becoming quite popular. You could probably host your own classes on more advanced/specialized topics (where they might not be enough people interested to get an actual physical class together in a smaller town), set it up so that everyone gets audio & video and remote students can send back audio (for questions/discussion), charge tuition to cover the conference server feels, your costs and compensation, etc. and be quite successful. Doug Smith (http://www.emcesd.com/) appears to have done pretty well with his approach of giving away a *significant* amount of useful information for free and then having a subscription service for those who want even more. ---JoelArticle: 131314
Raban wrote:
> Like what do you have to purchase, software or hardware or what dollar
> amount to do you have to purchase just to get few questions answered, sales
> wise for pricing or even worse, tech support?
Distributors are order takers.
I don't call them until I know what I want.
Example: "I would like budgetary pricing on 1000 pieces
of an XYZ123-3 for delivery in March 2009 "
But do your homework first.
Check relative prices/options with Digikey.
Research the boards yourself on-line.
Read the manuals.
Look at the schematics.
Etc.
-- Mike Treseler
Article: 131315Joel Koltner wrote: > "Joerg" <notthisjoergsch@removethispacbell.net> wrote in message > news:Zv5Oj.4677$iK6.2580@nlpi069.nbdc.sbc.com... >> There shouldn't be any tenure in the first place. There is a reason why the >> tenure concept does not exist in industry. Just my humble opinion. > > Doesn't tenure just mean that you have to screw up particularly badly to get > fired? And that even after you officially quit teaching/researching you're > generally still allowed to come and play in the lab and perhaps have an > office? Or is there more to it than that? > Plus probably a nice retirement benefit. > I was asked to write a letter of recommendation for a professor I had to turn > him from an assistant professor into a full-fledged (and perhaps tenure > track?) professor. He's a good teacher so I was happy to do it, but I found > it a little odd that the professor in charge of this whole process said, "If > you don't feel you can write a letter that presents [this guy] in a positive > light, it's OK -- let me know and we'll find someone else." Hmmm....! > That is strange. Normally they should have known this guy inside out before even offering tenure if that's what his new position entails. >> Some day I will, when I throttle back design work and money (hopefully) >> isn't a big issue. It doesn't have to be any ritzy school as long as the >> audience is motivated and the school isn't a huge driving distance away. > > These days "distance learning" is becoming quite popular. You could probably > host your own classes on more advanced/specialized topics (where they might > not be enough people interested to get an actual physical class together in a > smaller town), set it up so that everyone gets audio & video and remote > students can send back audio (for questions/discussion), charge tuition to > cover the conference server feels, your costs and compensation, etc. and be > quite successful. > True, but I am a believer in face to face sessions when it comes to explaining EE matters. You can't beat the hands-on training in front of a big scope or analyzer. "Sir, I can't get that dang thang to trigger!" > Doug Smith (http://www.emcesd.com/) appears to have done pretty well with his > approach of giving away a *significant* amount of useful information for free > and then having a subscription service for those who want even more. > Yes, his site is indeed excellent. I am surprised IEEE lets him publish his papers. When I wrote papers for IEEE transactions there was a pretty clear statement that you pretty much surrender copyright to them. -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM.Article: 131316
"Joerg" <notthisjoergsch@removethispacbell.net> wrote in message news:KD6Oj.9778$2g1.2542@nlpi068.nbdc.sbc.com... > That is strange. Normally they should have known this guy inside out before > even offering tenure if that's what his new position entails. I believe they did know him inside and out, were happy with his performance, and that's why it happened: They had already decided they were going to offer him the promotion, but some standard procedure required getting a student evaluation as well... so they had to find someone who was willing to write up a positive one. I just think it's strange that they bother getting a student evaluation when their minds are already made up... since it then puts them in the rather awkward position of having to say, "Please write us a good evaluation, or if you don't feel you can, that's OK, we'll find someone else..." Weird. Perhaps they'd do better to ask a handful of students to write up objective evaluations without the pressure of "...but, um, it has to be positive?" -- and then culling any that were negative? :-) I suppose they're stuck in a way... being tied to the government (they're a land-grant university) means they have to follow lots of procedures that regular businesses don't. Regarding the nice retirement packages... my understanding was that state workers ended up with rather cushy retirement packages in exchange for having to accept noticeably below-average salaries (relative to private industry) during their working years. In Oreogn we have the PERS (Public Employee Retirement System) which used to work this way, but the "cushy" benefits were signifcantly reduced via the ballot box when some interested parties pointed out how much better PERS was than what those folks in private industry get. Hence you now have a system where public employee pay still isn't competitive with private industry and now the retirement isn't either! This was a common topic of complaint by the professors (that you'd get to know well enough) when I was in grad school; a significant number left for private industry during that time, and I certainly coudn't blame them. That being said, I don't know enough to evaluate whether or not public jobs are still attractive when you look at the total package -- some people would argue they are and that PERS benefit reductions were just "corrections" to a system that had become too "generous" in its compensation. ---JoelArticle: 131317
Joel Koltner wrote: > "Joerg" <notthisjoergsch@removethispacbell.net> wrote in message > news:KD6Oj.9778$2g1.2542@nlpi068.nbdc.sbc.com... >> That is strange. Normally they should have known this guy inside out before >> even offering tenure if that's what his new position entails. > > I believe they did know him inside and out, were happy with his performance, > and that's why it happened: They had already decided they were going to offer > him the promotion, but some standard procedure required getting a student > evaluation as well... so they had to find someone who was willing to write up > a positive one. I just think it's strange that they bother getting a student > evaluation when their minds are already made up... since it then puts them in > the rather awkward position of having to say, "Please write us a good > evaluation, or if you don't feel you can, that's OK, we'll find someone > else..." Weird. > > Perhaps they'd do better to ask a handful of students to write up objective > evaluations without the pressure of "...but, um, it has to be positive?" -- > and then culling any that were negative? :-) I suppose they're stuck in a > way... being tied to the government (they're a land-grant university) means > they have to follow lots of procedures that regular businesses don't. > > Regarding the nice retirement packages... my understanding was that state > workers ended up with rather cushy retirement packages in exchange for having > to accept noticeably below-average salaries (relative to private industry) > during their working years. In Oreogn we have the PERS (Public Employee > Retirement System) which used to work this way, but the "cushy" benefits were > signifcantly reduced via the ballot box when some interested parties pointed > out how much better PERS was than what those folks in private industry get. > Hence you now have a system where public employee pay still isn't competitive > with private industry and now the retirement isn't either! This was a common > topic of complaint by the professors (that you'd get to know well enough) when > I was in grad school; a significant number left for private industry during > that time, and I certainly coudn't blame them. > > That being said, I don't know enough to evaluate whether or not public jobs > are still attractive when you look at the total package -- some people would > argue they are and that PERS benefit reductions were just "corrections" to a > system that had become too "generous" in its compensation. > All I know from here (CA) is that their benefits are mind-boggling. Paid sick leave, fat disability payments where lots of people tried and succeeded to be declared "disabled", cradle-to-grave medical with hardly any co-pay. The latter alone will saddle our communities with previously unheard of debt. Oh, and then lots of jobs have the retirement benefit tied to the last work year. So, folks have themselves transferred into high-cost areas such as the Bay Area for 13 months or so, then move back. That ratchets their monthly checks up substantially, until their dying day. That ain't right. -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM.Article: 131318
"Joerg" <notthisjoergsch@removethispacbell.net> wrote in message news:tq7Oj.1556$FF6.588@newssvr29.news.prodigy.net... > All I know from here (CA) is that their benefits are mind-boggling... Well, it's entirely reasonable to have retirement benefits for public employees be comparable to what private companies offer... I just hope that public employee salaries will then become comparable as well (which implies a pay raise), since otherwise I don't see how the gov't. expects they'll get comparable quality out of their workers. One problem with the government seems to be that they don't expect their employees to be agile over time. See this article: http://www.gcn.com/print/24_30/37174-1.html -- Someone the government ends up with a bunch of 70 year old programmers and therefore has to hire IBM to build them the modernized e-filing systems? Surely there must be some new hires in the past, say, 40 years who could have been working on this and hence, on average, would only be middle-aged today!? > Oh, and then lots of jobs have the retirement benefit tied to the last work > year. I expect that was implemented to help people who were *forced* to move? It seems like it needs reworking to differentiate between cases where the government wants to move you vs. you just voluntarily wanting to do so. ---JoelArticle: 131319
Dave <dhschetz@gmail.com> wrote: >Does anybody out there have a good methodology for determining your >optimal FPGA pinouts, for making PCB layouts nice, pretty, and clean? >The brute force method is fairly maddening. I'd be curious to hear if >anybody has any 'tricks of the trade' here. I start thinking about how the PCB should be routed the minute I start to draw a schematic. I always draw components with their actual pin-outs. This helps to group pins together and it helps to troubleshoot the circuit when the prototype is on your bench (no need to lookup the pinouts because they are in your diagram). >Also, just out of curiosity, how many of you do your own PCB layout, >versus farming it out? It would certainly save us a lot of money to >buy the tools and do it ourselves, but it seems like laying out a Whether you should do PCB layout by yourself or hire someone to do it for you depends on if you have the time and talent to design a PCB. After all at high frequencies and / or large currents a PCB becomes a component of your circuit. -- Programmeren in Almere? E-mail naar nico@nctdevpuntnl (punt=.)Article: 131320
> I always draw components with their actual >pin-outs. What does that mean? -- These are my opinions, not necessarily my employer's. I hate spam.Article: 131321
"Hal Murray" <hal-usenet@ip-64-139-1-69.sjc.megapath.net> wrote in message news:JdudnXIVmePbjJTVnZ2dnUVZ_vfinZ2d@megapath.net... >> I always draw components with their actual >>pin-outs. > What does that mean? I suspect he means that the schematic symbol he draws have the pins arranged with the same placement as that which occurs on the physical device. I've drawn some symbols like this at times, as it works OK for small devices, but of course has problems as soon as someone hits the "mirror" button on your symbol... and becomes intractable for devices with hundreds or even thousands of pins. You sometimes see magazines doing this in beginning electronics articles where they'll have a bunch of logic gates or similar drawn nicely within the DIP rectangle it comes in on top of a solderless breadboard or something so it's crystal clear how the circuit should be wired up.Article: 131322
>> which would be more useful to learn in the industrial world: Verilog >> or VHDL? > > In Europe (including UK) VHDL is more commonly used. > > In USA Verilog is prevalent. The studies I have seen were on $$$ spent on EDA tools which seems to show that people pay more money for Verilog tools. Some liked Verilog bigots liked to imply this correlated to users. For a rough order of measure of users, I look at Monster and based on rough data (not removing VHDL companies advertising also for Verilog coders and vice versa), there is a even split of VHDL and Verilog in the US market. Do you have a more accurate measure? Cheers, JimArticle: 131323
Michael, You might consider the industry you are interested in and research the companies that you may wish to work for and see what they use. This will give you the best idea as to which to learn first. Cheers, Jim > Howdy - I'm just beginning with FPGAs. I am using a Spartan 3E Starter > Kit with Xilinx ISE. I am an electrical engineer by training and did > some verilog in my collegiate days - but that was quite some time ago > and it is all very fuzzy now. I have decided that as an EE I should be > familiar with FPGAs - so I'm re-educating myself. With that said - > which would be more useful to learn in the industrial world: Verilog > or VHDL? > > Thanks! > > -MichaelArticle: 131324
I used to deal a lot with Avnet at work. If there is a potential for significant design-ins (i.e. a real production run) they offer quite a lot beyond just peddling chips. I've gotten a great deal of Xilinx help from Avnet FAEs at times the Xilinx FAEs were stretched too thin to respond to my problems in a timely manner. They have folks who specialize in other chip vendors as well (TI, Micron, Actel, etc.) as well as discretes and analog stuff (I'm sure more, these are just the areas I've experienced). Their FAEs are pretty knowledgeable, and especially they know how to get answers for questions they can't answer themselves. :-) All in all, at least for our size company Avnet was very good to work with (alas we have been decimated by our parent company so there's not a lot of reason for the Avnet guys to come around anymore ...). Hope this helps! ken Raban wrote: > Hello, > > I am new to this FPGA stuff and I wanted to purchase a starter kit and get > volume pricing for a few Xilinx FPGA's > > If one where to buy through Avnet or maybe NuHorizons, would anyone like to > share your past experiences when working with them? > > It seems all they care are who you are, what company you work with, what you > exactly are you doing. In other words, how many parts are you going to buy > from us before I spend any time with you. > > Do you have to be a big company or are they trying to discourage small > startups or students or whoever? > > Like what do you have to purchase, software or hardware or what dollar > amount to do you have to purchase just to get few questions answered, sales > wise for pricing or even worse, tech support? > > Thanks. > >
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