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hi, I am quite a newbie with FPGAs and would like some opinion about existing sFPDP IP Cores for serial communications. We are considering the use of a Virtex-5 ML506 Development Board with GTP multi-gigabit serial transceivers to accomplish a process were the sFPDP communication with an external element is a must. However, we have not found any xilinx sFPDP IP Core or any one from any third-party alliance member (and for V-5). There are some enterprises on the web offering sfpdp IP Cores as Vmetro and 4DSP but we are not sure about how this software can work. Does anyone have any experience with this? or, any advice? Would be very grateful for any infoArticle: 129476
>>> Yes, you have to control the switches and pushbuttons on the board >>> manually. >> I see, many thanks. I guess I can use either of the manual switch to >> control DIRECTION. One thing I don't understand is that the clock is >> 50MHz and my timing constraints is only a few macro seconds. I wonder >> how I can control DIRECTION that fast by manually pushing the switch. >> >> Fei > > That constraint doesn't mean that you will be switching at that rate, > it only defines the maximum rate. I now understand that the vhdl source was doing a up and down counter depending on the direction switch. So I have properly set up PINs: NET "CLOCK" TNM_NET = CLOCK; TIMESPEC TS_CLOCK = PERIOD "CLOCK" 40 ns; OFFSET = IN 10 ns BEFORE "CLOCK"; OFFSET = OUT 10 ns AFTER "CLOCK"; NET "COUNT_OUT<0>" LOC = R20; LED0 NET "COUNT_OUT<1>" LOC = T19; LED1 NET "COUNT_OUT<2>" LOC = U20; LED2 NET "COUNT_OUT<3>" LOC = U19; LED3 NET "DIRECTION" LOC = V8; SW0 NET "CLOCK" LOC = E12; GCLK5 50MHz E12 is GCLK5, the 50MHz oscillator on S3A chip. What's confusing me here is that if period is 40ns, wouldn't frequency be 25MHz? It'd make sense period is 20ns. I am using the numbers in Fig 12 in qst.pdf. After I load impact and program the board, the first 4 LEDs are lit, while the remaining 4 unlit. V8 is the pin for SW0 next to LED 0. After It's a slider switch, turning it high or low makes no difference. The leds don't blink... It's almost as if the clock source is not driving the logic. FeiArticle: 129477
On Feb 25, 12:36 pm, troy.sc...@latticesemi.com wrote: > Gents, > > Saw this thread go by on my alert list and wanted to check in. > > From the perspective of the synthesis and simulator, the Project > Navigator's job is to supply an ordered file list, command line flags, > and in some cases a script to automate a run. There is no user- > defined file order 7.0. It will attempt to build an ordered file list > automatically. I have seen some VHDL designs fail under 7.0 that > requires Service Pack 2 to correct. > > If all else fails, manage HDL source from within Synplify or Precision > and create an EDIF-based ispLEVER project. > > It's accurate to say Project Navigator has some non-standard > conventions for HDL file management. I blame it partially because > system has a long history of managing all sorts of non-HDL file > formats like schematic, ABEL, and the native Lattice parameter > constraints file (LPC) created by IPexpress. Under the hood 7.0 is a > big improvement over 6.x, it has far better capacity, performance, and > language compliance when dealing with long file lists. It also > supports mixing VHDL and Verilog. > > We are working on this area to make it closer to the conventions you'd > find in other EDA tools. > > Troy Scott > Software Marketing > Lattice Semiconductor Corporation Troy, Thanks for replying. I didn't get much from Lattice email support, but the local FAE, Jon Rook, helped me out. I guess the turn around time for Jon is a lot better than the support folks. By the time support got around to asking me for my source files, Joh had the problem figured out. Seems that 7.0 is pretty new, I believe just this month right? Well I was using a version I had downloaded back in November when I had first considered using a Lattice part. The LFXP3 in the 100 pin TQFP is pretty well locked in unless I find something unworkable in the next week or so. The problem was just that 6.0 doesn't support user libraries. Seems there is no way to tell the software that you have one. Version 7.0 lets me tell it what the libraries are and does figure out correctly what order to compile the files. The Xilinx and I think the Altera tools allow (require?) you to specify the compile order. I don't mind that as it is done just once and is easy to do. Hopefully the Lattice tool will continue to work correctly as I add more modules. I am having a little trouble figuring out the clocking capabilities. I found info on the DCS clock mux. That is just what I needed. I can't tell however, if two of them can be used to combine three clocks. I think I will be ok with just two clock inputs, but I'm not sure. My customer is getting good at throwing curves at me. Good thing I duck well! I will also comment that Lattice makes it harder to try out their products. I am used to getting loans of eval boards and complete evaluation software. Lattice is requiring a formal 30 day agreement with a PO. I have never had that with Altera or Xilinx.Article: 129478
Aravind As John and Antti have said Cable III and clones as well should work in most cases. The JTAG on Darnaw1 operates at 2.5V and with Cable III and the look-alikes can sometimes have ocassional issues when operating at this voltage. Avoid extending your cable and try and keep it away from anything electrically noisey to avoid issues. If you have a Xilinx Cable IV or the Platform USB Cable they are superior in operating on a 2.5V JTAG chain. We do have some plans to make a better low cost Cable III look-alike that will operate well down to 1.8V interfaces but at present I can't give a timescale for it's availability. The seperate SPI head on this module voltage is set by the user wire up of the bank2 I/O voltage and is recommended to be set at 3.3V for operation of the SPI Flash. You may find this interface operates better as a result even if you do have an issue with the actual JTAG chain. John Adair Enterpoint Ltd. On 25 Feb, 16:11, aravind <aramos...@gmail.com> wrote: > Hi, I just purchased Enterpoint's Darnaw1 module. I have Xilinx > parallel 3 cable not Parallel 4 cable. Is it possible to configure > spartan3e with Parallel cable 3 through the parallel cable 4 header? > Thanks. > > -AravindArticle: 129479
The clock source is driving the logic. The LEDs are blinking too fast for the human eye to tell the difference. Add a counter circuit to divide the clk frequency down to something the human eye can visually verify the blink rate and watch it count up and down. "Fei Liu" <fei.liu@gmail.com> wrote in message news:47C33597.2070706@gmail.com... >>>> Yes, you have to control the switches and pushbuttons on the board >>>> manually. >>> I see, many thanks. I guess I can use either of the manual switch to >>> control DIRECTION. One thing I don't understand is that the clock is >>> 50MHz and my timing constraints is only a few macro seconds. I wonder >>> how I can control DIRECTION that fast by manually pushing the switch. >>> >>> Fei >> >> That constraint doesn't mean that you will be switching at that rate, >> it only defines the maximum rate. > > I now understand that the vhdl source was doing a up and down counter > depending on the direction switch. So I have properly set up PINs: > NET "CLOCK" TNM_NET = CLOCK; > TIMESPEC TS_CLOCK = PERIOD "CLOCK" 40 ns; > OFFSET = IN 10 ns BEFORE "CLOCK"; > OFFSET = OUT 10 ns AFTER "CLOCK"; > NET "COUNT_OUT<0>" LOC = R20; LED0 > NET "COUNT_OUT<1>" LOC = T19; LED1 > NET "COUNT_OUT<2>" LOC = U20; LED2 > NET "COUNT_OUT<3>" LOC = U19; LED3 > NET "DIRECTION" LOC = V8; SW0 > NET "CLOCK" LOC = E12; GCLK5 50MHz > > E12 is GCLK5, the 50MHz oscillator on S3A chip. What's confusing me here > is that if period is 40ns, wouldn't frequency be 25MHz? It'd make sense > period is 20ns. I am using the numbers in Fig 12 in qst.pdf. > > After I load impact and program the board, the first 4 LEDs are lit, > while the remaining 4 unlit. V8 is the pin for SW0 next to LED 0. After > It's a slider switch, turning it high or low makes no difference. The > leds don't blink... It's almost as if the clock source is not driving > the logic. > > FeiArticle: 129480
On Feb 25, 2:55 am, Rob <BertyBoos...@googlemail.com> wrote: > On Feb 24, 8:53 pm, PatC <p...@patocarr.com> wrote: > > > > > Bob Smith wrote: > > > JK wrote: > > >> your DCM is missing reset, if I am not wrong. > > >> I dont see any reset on your top level port list. > > >> You are getting clkout2, because it is not depending on reset. > > > > Thanks for the suggestion. I added a reset from a switch on the > > > board. A reset does not seem to make any difference. > > > > PatC wrote: > > >> Have you checked the locked output? if it's not locked, FX would not > > >> output anything iirc, as opposed to clk0 which does regardless of lock. > > > > Thanks for the suggestion. I tied an LED on the board to the > > > locked status output. The locked status never goes high (perhaps > > > as you suspected). Any ideas why it won't lock? > > > Since your code sample is snipped, I don't see the BUFG connecting clk0 > > to clkfb. If you are using clock feedback 1x, this is how it should be > > connected. Without this feedback, it won't lock. > > > -P@ > > When using the DCM for frequency synthesis only you are correct in > saying that you don't need to feedback a signal and setting > CLK_FEEDBACK to NONE is the right thing to do. I've succesfully used > this configuration myself. > Strange that the output is at 2V, is this the IO voltage for that > bank? If you haven't already done so, i suggest you try and simulate > the design, as this may give some clue as to what is going on. > Without a RST input you also need to be careful that the clock is > running and stable before configuration. Any change in the input clock > requires RST to be asserted. > I'm also not sure that the LOCKED pin should go high, since the > datasheet states that this is asserted when CLKIN and CLKFB are in > phase, which of course will never happen in this configuration. > > Cheers > Rob Hmm, duty cycle correction is on, which requires the DLL. Turning it off should make feedback unnecessary.Article: 129481
Hello all, I have a bunch of functions I would like to synthesize on Quartus. These are going to be part of a library. I would like to get resource utilization of each function. The functions are generic. My questions are 1) Do I have to write an entity for the synthesis of each function or Can I just pasts individual functions in a .vhdl file to get the resource estimation of each function 2) Since the functions are generic, would we get resource estimation for worst case resources used? eg : if i have a generic function for an adder, would it estimate resource utilization for a 1 bit adder or maximum possible adder. Thanks a bunchArticle: 129482
Hi: Does anyone know whether Altera has some analogous file like XDL of Xilinx so that we can read the place and route of the circuit of Altera's FPGA textually? If not, I wonder whether there is a third tool that can generate an intermediate file so that it can accomplish this process: Altera FPGA circuit (Placed and Routed) <-->intermediate file<-->Xilinx FPGA circuit (Placed and Routed). Thanks. GeorgeArticle: 129483
Bob Smith wrote:
> I'm trying to use a DCM on a Spartan 3E to synthesize a frequency
> of 8 MHz but see only a constant 2 volts on the CLKFX output. The
> google hits on this did not help.
>
> It must be a simple mistake; any ideas what I'm doing wrong?
> The "****" indicate the lines from the prototype that I've changed.
Thanks Pat, Michael, Rob.
The clkin line is given a BUFG.
Haven't tried the simulation but that is next.
Turning off duty cycle correction did not make a difference.
The latest Verilog is attached.
thanks
Bob Smith
module clocks(clkin, reset, clkout1, clkout2, locked);
input clkin; // Digilent Spartan 3e starter kit 50 MHz clock
input reset; // Reset input
output clkout1; // Wanna be 8 MHz
output clkout2; // 50 MHz/32 for comparison
output locked; // DLL lock status
reg [7:0] count;
always @(posedge clkin)
begin
count <= count + 1;
end
assign clkout1 = count[4];
DCM #(
.CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(25), // Can be any Integer from 1 to 32 ************
.CLKFX_MULTIPLY(4), // Can be any Integer from 2 to 32 ************
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(20.0), // Specify period of input clock ************
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("NONE"), // Specify clock feedback of NONE, 1X or 2X ********
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an Integer from 0 to 15
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("FALSE"), // Duty cycle correction, TRUE or FALSE **********
.FACTORY_JF(16'hC080), // FACTORY JF values
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE
) DCM_inst (
.CLK0(CLK0), // 0 degree DCM_SP CLK output
.CLK180(CLK180), // 180 degree DCM_SP CLK output
.CLK270(CLK270), // 270 degree DCM_SP CLK output
.CLK2X(CLK2X), // 2X DCM_SP CLK output
.CLK2X180(CLK2X180), // 2X, 180 degree DCM_SP CLK out
.CLK90(CLK90), // 90 degree DCM_SP CLK output
.CLKDV(CLKDV), // Divided DCM_SP CLK out (CLKDV_DIVIDE)
.CLKFX(clkout2), // DCM_SP CLK synthesis out (M/D) ***********
.CLKFX180(CLKFX180), // 180 degree CLK synthesis out
.LOCKED(locked), // DCM_SP LOCK status output ***********
.PSDONE(PSDONE), // Dynamic phase adjust done output
.STATUS(STATUS), // 8-bit DCM_SP status bits output
.CLKFB(CLKFB), // DCM_SP clock feedback
.CLKIN(clkin), // Clock input (from IBUFG, BUFG or DCM_SP) ***********
.PSCLK(PSCLK), // Dynamic phase adjust clock input
.PSEN(PSEN), // Dynamic phase adjust enable input
.PSINCDEC(PSINCDEC), // Dynamic phase adjust increment/decrement
.RST(reset) // DCM_SP asynchronous reset input ***********
);
endmodule
Article: 129484Hi all, I am doing hardware Cosimulation in System Generator via JTAG PLatform USB cable to my ML501 Evaluation kit but my Cosim block does not have any output. I have already configured the cable setup seperately through iMPACT by auto connecting cable or doing cable setup or ven initializing the chain but to no avail. Can anyone give me some advice on this? Thank you.Article: 129485
Sylvain Munaut <SomeOne@SomeDomain.com> wrote: > Hi, > > I wasn't very satisfied with the available assembler, so a few month > ago I wrote a new compiler for the Picobaze during my spare > weekends ... Hi Sylvain, Nothing to add but encouragement really. The software offerings for picoblaze are limited, especially in the non-windows world. Both picoasm and kpicosim are very good, but their development seems to have stopped. If you can get a polished version of your assembler finished, it sounds like it would be a great tool. Andy From puiterl@notaimvalley.nl Tue Feb 26 01:06:20 2008 Path: newsdbm04.news.prodigy.net!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!goblin1!goblin.stu.neva.ru!feeder.news-service.com!newsgate.cistron.nl!xs4all!transit3.news.xs4all.nl!post.news.xs4all.nl!not-for-mail Message-Id: <47c3d68c$0$14345$e4fe514c@news.xs4all.nl> From: Paul Uiterlinden <puiterl@notaimvalley.nl> Subject: Re: Seed Values Newsgroups: comp.arch.fpga,comp.lang.vhdl Followup-To: comp.arch.fpga Date: Tue, 26 Feb 2008 10:06:20 +0100 References: <35fe7780-4c92-4ba1-aa56-a5294a623e3b@i12g2000prf.googlegroups.com> <13s5rt55srb3u6f@corp.supernews.com> <d65f5303-d0b5-424a-a225-3889789e003d@p43g2000hsc.googlegroups.com> Organization: AimValley User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 30 NNTP-Posting-Host: 80.127.156.247 X-Trace: 1204016780 news.xs4all.nl 14345 [::ffff:80.127.156.247]:60255 X-Complaints-To: abuse@xs4all.nl Xref: prodigy.net comp.arch.fpga:141798 comp.lang.vhdl:73926 FPGA wrote: >> process steps (save file, recompile, re-run simulation)? >> Is there a bug in your scaling process? > I have saved, recompiled and rerun simulation. The strange thing is, I > am getting the same sequence if I output uniform in real format even > after I change the initialisation of Seed1 and Seed2. > uniform(S1,S2,rand1); > rand_real <= rand1; > > I am not sure why this is happening. > SEED1 <= 10;--1 ; > SEED2 <= 20;--2147483647 ; Use variables for SEED1 and SEED2, or make sure there is a wait after assigning the signals. Signals are only updated after a delta delay. So if you do: SEED1 <= 10;--1 ; SEED2 <= 20;--2147483647 ; uniform(SEES1,SEED2,rand1); then uniform uses the values of SEED1 and SEED2 from *before* the assignment. -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not.Article: 129486
Hi everybody, I am currently working on the mulitboot feature of xilinx s3a. I have programmed one of the on-board PROMs with 3 different files at different locations but there are lots of issues using the ICAP protocol to reconfigure from those locations as explained in ug332. Can anyone help me with a detailed (and simple)example explaining how to use ICAP? How can an ICAP driver be used?? KundanArticle: 129487
Nico Coesel wrote: > "Symon" <symon_brewer@hotmail.com> wrote: > >> Nico Coesel wrote: >>> The best answer to all these questions is a question. >> Is it? > > Ofcourse. Interview questions are designed to start a technical debate > in order to reveal the applicant's knowledge (or lack thereof). > Is that the only purpose?Article: 129488
I'm looking for a "rule of thumb" of what I should expect in terms of jitter on the clock signal. It should be relatively easy to find what jitter an oscillator has (e.g. one datasheet said 31ps peak-to-peak jitter (typical)). On the other hand, I have no idea what kind of jitter you could expect from effects that are caused by for example the PCB as I am not an expert on high speed PCB design. Does anyone on this newsgroup either have any decent numbers or a good application note or similar resource they can point me to? Ideally, I would like a rule of thumb like the following: "If the timing analyzer says your design can meet timing with a clock cycle of X ns, subtract Y ns from that to have a reasonable margin against clock jitter." Is Y going to be in the ballpark of 0.05 ns, 0.5 ns, or even longer? /AndreasArticle: 129489
Philip Potter wrote: > Nico Coesel wrote: >> "Symon" <symon_brewer@hotmail.com> wrote: >> >>> Nico Coesel wrote: >>>> The best answer to all these questions is a question. >>> Is it? >> >> Ofcourse. Interview questions are designed to start a technical >> debate in order to reveal the applicant's knowledge (or lack >> thereof). > Is that the only purpose? What other purpose could there be?Article: 129490
On Feb 26, 4:06=A0am, Paul Uiterlinden <puit...@notaimvalley.nl> wrote: > FPGA wrote: > >> process steps (save file, recompile, re-run simulation)? > >> Is there a bug in your scaling process? > > I have saved, recompiled and rerun simulation. The strange thing is, I > > am getting the same sequence if I output uniform in real format even > > after I change the initialisation of Seed1 and Seed2. > > uniform(S1,S2,rand1); > > =A0rand_real <=3D rand1; > > > I am not sure why this is happening. > > SEED1 <=3D 10;--1 ; > > SEED2 <=3D 20;--2147483647 ; > > Use variables for SEED1 and SEED2, or make sure there is a wait after > assigning the signals. > > Signals are only updated after a delta delay. So if you do: > > SEED1 <=3D 10;--1 ; > SEED2 <=3D 20;--2147483647 ; > uniform(SEES1,SEED2,rand1); > > then uniform uses the values of SEED1 and SEED2 from *before* the > assignment. > > -- > Paul Uiterlindenwww.aimvalley.nl > e-mail addres: remove the not. Thanks a bunch guys. I appreciate your help.Article: 129491
>Philip Potter wrote: >> Nico Coesel wrote: >>> "Symon" <symon_brewer@hotmail.com> wrote: >>> >>>> Nico Coesel wrote: >>>>> The best answer to all these questions is a question. >>>> Is it? >>> >>> Ofcourse. Interview questions are designed to start a technical >>> debate in order to reveal the applicant's knowledge (or lack >>> thereof). >> Is that the only purpose? > >What other purpose could there be? I think you all need the philosophy group. This is the place to come when you have a question that needs an answer, not when you have an urge to consider the meaning of life.Article: 129492
Andrew Greensted wrote: > Sylvain Munaut <SomeOne@SomeDomain.com> wrote: >> Hi, >> >> I wasn't very satisfied with the available assembler, so a few month >> ago I wrote a new compiler for the Picobaze during my spare >> weekends ... > > Hi Sylvain, > > Nothing to add but encouragement really. The software offerings for > picoblaze are limited, especially in the non-windows world. Both picoasm > and kpicosim are very good, but their development seems to have stopped. > > If you can get a polished version of your assembler finished, it sounds > like it would be a great tool. > > Andy Of course, you're working on the simulator now, right? :)Article: 129493
>Hello all, > >I have a bunch of functions I would like to synthesize on Quartus. >These are going to be part of a library. I would like to get resource >utilization of each function. The functions are generic. >My questions are >1) Do I have to write an entity for the synthesis of each function or >Can I just pasts individual functions in a .vhdl file to get the >resource estimation of each function >2) Since the functions are generic, would we get resource estimation >for worst case resources used? eg : if i have a generic function for >an adder, would it estimate resource utilization for a 1 bit adder or >maximum possible adder. > >Thanks a bunch > In VHDL, you need an entity+architecture with the inputs and outputs of the function(s) connected to top-level inputs and architectures, otherwise the synthesizer/mapper/etc. functions will discard your logic. If you want to run several functions through in parallel, they can share inputs, but this might not give you enough information on each individual function.Article: 129494
Hello, I have some problem understanding the set_input_delay min and max constraint. Assume that you have an interface that is connected to an FPGA. This interface has a clock (Clk) and a databus (DB). The datavalid window is centered around the rising edge of Clk. Assume a setup time of 1ns and a hold time of 2 ns. The clk period is 10 ns. How should I constrain this with the set_input_delay command? thanks for helping me, KarelArticle: 129495
Andreas, Your question is equivalent to: "If I walk outside, how much noise will I hear?" Jitter is phase noise. How much phase noise you will "hear" is entirely dependent on "where you live": is there a freeway next to you? Railroad tracks, a forest, a waterfall? Jackhammer? Roadside bomb? The question, just like jitter itself, is unbounded (there are no theoretical limits to noise, as it is a matter of time until a larger noise comes along). The "system jitter" will vary of course, depending on primarily: the number of things switching on the same clock edge (both internal, and external), the quality of the bypass solution (was it designed for the clock rate? or is it a generally good solution, or a poor one), and the signal integrity of the IOs (reflections, mismatch, etc.). I have seen from 50 ps on a pcb with everything done right, to over 2,000 picoseconds, on a pcb where "everything went wrong." Some typical numbers for "I didn't care, and I would be happy with my results" come in from 200 to 500 ps (all peak to peak numbers). There is a great deal of collateral on the subject on the Xilinx web pages (signal integrity), but this is "still" an unsolved problem, with no tools, and only moderate estimation ability (eg: jitter prediction is built into the ISE software for the DCM and clock resources). AustinArticle: 129496
Symon wrote: > Philip Potter wrote: >> Nico Coesel wrote: >>> "Symon" <symon_brewer@hotmail.com> wrote: >>> >>>> Nico Coesel wrote: >>>>> The best answer to all these questions is a question. >>>> Is it? >>> Ofcourse. Interview questions are designed to start a technical >>> debate in order to reveal the applicant's knowledge (or lack >>> thereof). >> Is that the only purpose? > > What other purpose could there be? What are you suggesting?Article: 129497
FPGA, > I just commented my signals SEED1,SEED2 in the top level. I > initialised the values of SEED1, SEED2 within the process (not taking > as signal inputs as before). Now, I see that I am getting different > sequence for different values of SEED1, SEED2. Why would this happen? > Shouldnt it behave the same if I have SEED1, SEED2 as signals and then > within process I have variable S1,S2 initialised to signal SEED1, > SEED2 > I dont understand why it behaves so. Your simulator should have reported an error when you declared SEED1 and SEED2 as signals as uniform requires them to be variables. JimArticle: 129498
On Feb 20, 5:18 pm, radarman <jsham...@gmail.com> wrote: > I am trying to port an application from ISE/EDK 8.1i to 9.2i. > Everything is going well except for one thing - the page in Software > Platform Settings for specifying the interrupt handler is missing. > > To start, the EDK project is instantiated within an ISE project as a > subcomponent. I created the new EDK project from scratch using BSB, > and assigned three serial ports, a SPI interface, a couple of GPIO > registers, and a hardware timer. The wizard added the interrupt and > reset controller. I have two active interrupts routed to the interrupt > controller - one from the SPI interface and one from the timer. > > I attempted to manually add the interrupt handler lines to the MSS > file, but no go. The application builds just fine, and goes through > early initialization just fine, but hangs the first time it attempts > to do something that would cause an interrupt to fire. (specifically, > the first time it attempts to write to the SPI DAC) I have rebuilt > both the hardware and the BSP & libraries several times. Everything > builds just fine - but I still don't get the page for interrupts. > > Notably, all of the interrupt options in the microblaze IP core are > grayed out, which indicates that maybe the interrupts are somehow > disabled in the core, but I can't imagine how. > > I've had this problem before in EDK 8.2i, but I don't recall how I > fixed it then. > > Can anyone point me in the right direction? > > Thanks! > -Seth Hi, Refer to the http://www.xilinx.com/support/answers/24988.htm page for the solution, We have to now set the interrupts in the application code regards MadhuArticle: 129499
Dwayne Dilbeck wrote: > The clock source is driving the logic. The LEDs are blinking too fast for > the human eye to tell the difference. Add a counter circuit to divide the > clk frequency down to something the human eye can visually verify the blink > rate and watch it count up and down. > > I slowed down the clock by 1000,000 using another counter, now I can see the LEDs blinking. Very nice, thanks! Fei
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