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On 20 Feb., 18:00, jasonL <junsong.l...@gmail.com> wrote: > I have a project to prototype an ASIC design on FPGA. What are the > things I should do? Here is some of my concerns: > > 1) I understand FPGAs usually have 4 look-up table. Should I rewrite > the ASIC combinational logics to be four-inputs logics to improve the > utilization of FPGA? > > 2) Netting if and case statements over three layers might results a > poor synthesis result in FPGA . Should I changes those netting codes > in ASIC RTL? > > 3) ASIC synthesis need to generate clock tree and power rails. In FPGA > synthesis, Maybe I not need to care too much about it? > > 4) Is there a to-do-list for this kind of job? > > Thank you for any advices. 1) no, unless you are given the opportunity to get old doing this project 2) see 1 3) yes 4) Yes, your 1st and only point: give it to a third party It seems somebody gave you the wrong job, because you neither have experience with fpga nor asic design. At least basic experience with FPGA would be needed.Article: 129301
No problem. The ispLever uses either Synplify or Precision to do the compilation. You will have to read about the tool you use to specify compile order. I use Precision and I believe you can not specify compile order. It will automatically determine it for you based on heirarchy and dependencies. In making the move to ispLever, I had to add some extra use clauses to my user defined libraries to get things to go under ispLever. Because in my previous tools I could do a compile order but with Precision it looks for heirarchy and dependancy to set compile order. "rickman" <gnuarm@gmail.com> wrote in message news:247a3be4-666e-433f-b6d6-08685b4df397@s37g2000prg.googlegroups.com... > Thanks for the reply. No, that is not the problem. The files compile > just fine under Modelsim and using the Altera tools. In both of those > tools I can specify the order to compile the files. These libraries > are files that I have my personal, common definitions and > conversions. I know these files work because they have been used many > times before. > > All I need to know is how the Lattice ispLever tool is told the order > to compile the files. > > > On Feb 19, 12:17 pm, "Colin Hankins" <Colin.Hank...@touit.com> wrote: >> Did you include the use clause in your library package files that require >> dependancies? You can either reference the user defined library itself or >> just do: use work.my_package; >> >> The error messages related to library not found is probably due to the >> library not being successfully compiled in the first place. >> >> Colin >> >> "rickman" <gnu...@gmail.com> wrote in message >> >> news:284755cf-f23b-4979-9ecd-25d229fde921@e23g2000prf.googlegroups.com... >> >> >I am trying to pick up the Lattice ispLEVER tool and am having a bit >> > of trouble with it in regards to libraries. I have several files for >> > the various libraries I have written for my VHDL. In order to use >> > them, they have to be compiled in the correct order since some use >> > definitions from the others. I can't seem to figure out how to tell >> > ispLEVER what order to compile the files. It has a way to telling the >> > tool that a given file *is* a library, but that seems to be where it >> > stops. I can't order the files in the project and it doesn't seem to >> > actually understand that the libraries exist in the VHDL. I get >> > several error message all related to libraries not found or >> > identifiers not declared that should have been in the library files. >> >> > I have looked through every piece of documentation I can find and they >> > all pretty much gloss over the idea of user defined libraries. Is >> > this something so simple I have missed it? >Article: 129302
ASIC protoyping using FPGAs is a common enough occurance. There are multiple low priced tool vendors that specialize in this area. It is best not to re-invent the wheel. Rather look up the tool vendors and let thier tools handle the FPGA mapping issues. The following paper can give you more insight into the process. I doubt you will find any FPGA protoype vendors in this paper, Since Mentor has a cycle based emulator that they compete against the fpgra protoypes with. http://www.mentor.com/products/fpga_pld/techpubs/mentorpaper_33693.cfm "jasonL" <junsong.liao@gmail.com> wrote in message news:28bd74a8-a6ab-4f18-b6f2-073d1ef98ee2@s12g2000prg.googlegroups.com... >I have a project to prototype an ASIC design on FPGA. What are the > things I should do? Here is some of my concerns: > > 1) I understand FPGAs usually have 4 look-up table. Should I rewrite > the ASIC combinational logics to be four-inputs logics to improve the > utilization of FPGA? > > 2) Netting if and case statements over three layers might results a > poor synthesis result in FPGA . Should I changes those netting codes > in ASIC RTL? > > 3) ASIC synthesis need to generate clock tree and power rails. In FPGA > synthesis, Maybe I not need to care too much about it? > > 4) Is there a to-do-list for this kind of job? > > Thank you for any advices.Article: 129303
Be sure to send an email to Xilinx Marketing. They should be interested in this as well. "Antti" <Antti.Lukats@googlemail.com> wrote in message news:5e8592e9-81c4-4a0c-9e1d-94c4702945e3@n58g2000hsf.googlegroups.com... > Hi > > I am making a time limited offer for full ownership rights sale for > > "XSIM Xilinx Platform Simulator" > > The simulator was developed in 2006, it was the first MicroBlaze > software simulator able to run u-Boot and ucLinux. > > If I receive any serious offer, the complete source code and ownership > rights will be sold as package. > The binaries can be recompiled with new copyright and ownerhsip notes > and graphics. > The simulator and currently existing plugins are written with Delphi > (Borland CodeGear). > Plugins can be written in C too, and with CodeGear parts of simulator > could also be in C/C++. > > The simulator has been used to troubleshoot and test u-Boot and > uClinux drivers and standalone software. > > There are some set of plugins available for > * TFT LCD controller > * Nokia 6610 Display > * CompactFlash (can mount raw image) > * SD Card (can mount raw image) > * I2C Real-time clock > * Some other > > Please contact me per email with offer and/or questions. > > If I do not receive any offers at all, I will most likely offer the > simulator myself as shareware. > > Antti LukatsArticle: 129304
Nial Stewart wrote: > I'm going to talk to a potential new client about using FPGAs to > accelerate part of their system. > > As part of what needs done there could be a significant amount of > division(s) done. > > Previously I've been able to multiply by a reciprocal then scale to > make division a double clock operation so this can be easily pipelined. > This is only achieveable if the divisor is pre-known and the > reciprocal can be pre-calculated. > > With what's coming up I'm not sure that I can do this, I know that > > Are there any clever techniques for streamlining divisions that > make them deterministic and don't use a big wodge of logic? > > > Thanks for any pointers, > > > Nial > > I've heard that the CORDIC can be used for division. I'm not sure how favorably this compares with other methods. -KevinArticle: 129305
Thanks for the reply. I'm still not sure we are on the same page. I am trying to use ispLever as an IDE. Yes, I am using Synplify for synthesis, but I don't invoke it directly. When I do invoke it directly I can specify the compile order and it works ok. The initial response from the local FAE seems to be that I need to use an EDIT tool flow and manually run the synthesis tool. The initial response from Lattice support is a canned message pointing me to a note totally unrelated to my problem. I am assuming there are some advantages to using the IDE rather than using the tools as separate, unconnected programs. If nothing else, I expect it should make the setup simpler since I should only have to set up the IDE and that will then handle the other tools. Doesn't the I in IDE stand for Integrated? I also can't see to get Modelsim to work with ispLever, it seems they don't license that with the starter kit. So I will be using the Altera or Xilinx tools to actually simulate my code and just use ispLever to do the synthesis to generate a bit file, at least until I make a final decision and buy the tools. I only wish Xilinx had a part that would do the job, but they don't seem to care much for putting FPGAs into small packages without using BGAs. Altera does have a part that will fit the socket, but it doesn't have nearly as many LUTs as the Lattice part. Which do you think would be easier, convincing Lattice to improve their tools, or getting Xilinx to offer some Flash FPGAs in smaller leaded packages? On Feb 20, 1:14 pm, "Colin Hankins" <Colin.Hank...@touit.com> wrote: > No problem. The ispLever uses either Synplify or Precision to do the > compilation. You will have to read about the tool you use to specify compile > order. I use Precision and I believe you can not specify compile order. It > will automatically determine it for you based on heirarchy and dependencies. > > In making the move to ispLever, I had to add some extra use clauses to my > user defined libraries to get things to go under ispLever. Because in my > previous tools I could do a compile order but with Precision it looks for > heirarchy and dependancy to set compile order. > > "rickman" <gnu...@gmail.com> wrote in message > > news:247a3be4-666e-433f-b6d6-08685b4df397@s37g2000prg.googlegroups.com... > > > Thanks for the reply. No, that is not the problem. The files compile > > just fine under Modelsim and using the Altera tools. In both of those > > tools I can specify the order to compile the files. These libraries > > are files that I have my personal, common definitions and > > conversions. I know these files work because they have been used many > > times before. > > > All I need to know is how the Lattice ispLever tool is told the order > > to compile the files. > > > On Feb 19, 12:17 pm, "Colin Hankins" <Colin.Hank...@touit.com> wrote: > >> Did you include the use clause in your library package files that require > >> dependancies? You can either reference the user defined library itself or > >> just do: use work.my_package; > > >> The error messages related to library not found is probably due to the > >> library not being successfully compiled in the first place. > > >> Colin > > >> "rickman" <gnu...@gmail.com> wrote in message > > >>news:284755cf-f23b-4979-9ecd-25d229fde921@e23g2000prf.googlegroups.com... > > >> >I am trying to pick up the Lattice ispLEVER tool and am having a bit > >> > of trouble with it in regards to libraries. I have several files for > >> > the various libraries I have written for my VHDL. In order to use > >> > them, they have to be compiled in the correct order since some use > >> > definitions from the others. I can't seem to figure out how to tell > >> > ispLEVER what order to compile the files. It has a way to telling the > >> > tool that a given file *is* a library, but that seems to be where it > >> > stops. I can't order the files in the project and it doesn't seem to > >> > actually understand that the libraries exist in the VHDL. I get > >> > several error message all related to libraries not found or > >> > identifiers not declared that should have been in the library files. > > >> > I have looked through every piece of documentation I can find and they > >> > all pretty much gloss over the idea of user defined libraries. Is > >> > this something so simple I have missed it?Article: 129306
Hi, I am using a Virtex II development board and am doing some work with a little system on a chip. I am using onboard block RAM as both the instruction ROM and RAM for programs. I was going along fine until I added some more code for the processor to run, which made the executable too big for the RAM I had created. I simply doubled the size of the RAM to allow the extra space. Everything looked fine in behavioral simulation, so I went ahead and put it on the board. The results weren't as expected, so I looked at the simulation again. I did a post place-and-route simulation at the clock speed of the target device and it worked perfectly. I have since gone back to older code and the smaller memory and things work most of the time. Occasionally I seem to get no output, but I can usually fix it by clearing the project files, restarting the Xilinx software, and resynthesizing my design. Has anyone experienced anything like this before? It doesn't seem like using more of the block RAM should have any effect on the rest of the design. In my searching before I posed this I came across a topic called "Xilinx BRAM failures" that talked about bitfiles working on some chips and not others due to problems with the BRAMs. Is this a possibility? Or maybe there was a static discharge problem at some point that damaged one or more slices or BRAMs that would cause it to fail? Thanks for any suggestions you might have!Article: 129307
On 20 Feb., 19:41, "Dwayne Dilbeck" <ddilb...@yahoo.com> wrote: > Be sure to send an email to Xilinx Marketing. They should be interested in > this as well. > > "Antti" <Antti.Luk...@googlemail.com> wrote in message > > news:5e8592e9-81c4-4a0c-9e1d-94c4702945e3@n58g2000hsf.googlegroups.com... > > > Hi > > > I am making a time limited offer for full ownership rights sale for > > > "XSIM Xilinx Platform Simulator" > > > The simulator was developed in 2006, it was the first MicroBlaze > > software simulator able to run u-Boot and ucLinux. > > > If I receive any serious offer, the complete source code and ownership > > rights will be sold as package. > > The binaries can be recompiled with new copyright and ownerhsip notes > > and graphics. > > The simulator and currently existing plugins are written with Delphi > > (Borland CodeGear). > > Plugins can be written in C too, and with CodeGear parts of simulator > > could also be in C/C++. > > > The simulator has been used to troubleshoot and test u-Boot and > > uClinux drivers and standalone software. > > > There are some set of plugins available for > > * TFT LCD controller > > * Nokia 6610 Display > > * CompactFlash (can mount raw image) > > * SD Card (can mount raw image) > > * I2C Real-time clock > > * Some other > > > Please contact me per email with offer and/or questions. > > > If I do not receive any offers at all, I will most likely offer the > > simulator myself as shareware. > > > Antti Lukats nice to see ONE comment and optimism! I have tried to earn money developing development tools for product from big companies. And I have succeeded to get product live time earnings of around 20.000 USD from the sale of SW development tools for Atmel AVR, but that was it. And I had ZERO support or interest from Atmel. Maybe I talked to wrong guys. Well actually I made bad exclusive resell right agreement. So I do not have much hopes. But it would be nice to be wrong this time. AnttiArticle: 129308
Kevin Neilson wrote: >> > I've heard that the CORDIC can be used for division. I'm not sure how > favorably this compares with other methods. > -Kevin Cordic division is similar to non-restoring sequential division. It uses a lot of adder-subtractors, which means it is either quite slow or it has a large clock latency.Article: 129309
nezhate wrote: > I didn't work with ActiveHDL, but I know that with ActiveHDL you > cannot do post place and route simulation. This soft is only for > behavioral simulation. I don't know where you got that idea. Active HDL simulates a post route netlist just fine. Perhaps you didn't have the simprims library? Active HDL can also simulate an edif netlist, and can co-simulate with Matlab as a testbench (something I don't think Modelsim does). I have both, but I use Active HDL for my day to day work. I use Modelsim pretty much only when I don't have a choice.Article: 129310
Alfreeeeed wrote: > > Looks like SPI Master Mode is the option. I am interested in Jon's > alternative of putting a memory twice the size a program need. Any > ideas how to implement this? BTW , I also need to program two FPGA > with the same program so I would need to do daisy chain with a > Spartan-3E. Well, I'm not going to reveal all my secrets for free, but a fairly simple scheme can be figured out for the SST chips. They need an "instruction" byte serially shifted in to program the memory to read from the beginning. The Xilinx FPGAs all seem to ignore everything before a byte of "FF" which appears right after a short header in the BIT or MCS file. Wiring up a 4-bit counter and a gate chip was the minimum package count scheme I could come up with for that bare minimum. If I needed to program a few bits of the starting address, too, that would probably expand to a 3-chip solution. These SSOP-packaged parts are pretty small. I also built my own programmer for the SST chips, as none of the device programmers would handle them. It was a one-evening job to get the programmer working. One bit from CPU to PROM, one clock bit, one data bit back from the PROM. Pretty simple, plugs into the parallel port. I wrote it in C for Linux, just my personal choice. The way I am setting it up doesn't allow for on-board programming, I DON'T want to give my customers that option. But, there's no reason that couldn't be provided easily. JonArticle: 129311
bobster.thelobster@yahoo.co.nz wrote: > On Feb 13, 8:30 am, Duane Clark <junkm...@junkmail.com> wrote: > > >>Well, I will have to admit that it has been several years since I have >>done post place and route simulation. I really don't see much need for >>that in FPGA design. > > > > > ooo now thats a little scary > Why? I don't use post PAR simulation unless I have a reason to believe the tools messed something up. I can count on my fingers the number of times I've resorted to post PAR simulation. A functional simulation of the RTL followed by a solid timing analysis is far more likely to uncover any problems in the design than a post PAR simulation is.Article: 129312
rickman wrote: > Thanks for the reply. I'm still not sure we are on the same page. I > am trying to use ispLever as an IDE. Yes, I am using Synplify for > synthesis, but I don't invoke it directly. When I do invoke it > directly I can specify the compile order and it works ok. Then why not just batch this flow, that works ? > The initial > response from the local FAE seems to be that I need to use an EDIT > tool flow and manually run the synthesis tool. Which is what you describe above ? > The initial response > from Lattice support is a canned message pointing me to a note totally > unrelated to my problem. > > I am assuming there are some advantages to using the IDE rather than > using the tools as separate, unconnected programs. If nothing else, I > expect it should make the setup simpler since I should only have to > set up the IDE and that will then handle the other tools. Doesn't the > I in IDE stand for Integrated? Yes, but IDE's often fail on the details, and are tested on the 'first user' stuff. The worst IDEs are the one's that do not allow external tool access :) > > I also can't see to get Modelsim to work with ispLever, it seems they > don't license that with the starter kit. So I will be using the > Altera or Xilinx tools to actually simulate my code and just use > ispLever to do the synthesis to generate a bit file, at least until I > make a final decision and buy the tools. > > I only wish Xilinx had a part that would do the job, but they don't > seem to care much for putting FPGAs into small packages without using > BGAs. Altera does have a part that will fit the socket, but it > doesn't have nearly as many LUTs as the Lattice part. I did see Actel have just released a QFN68 package, for their tiniest FPGA (CPLD sized) > > Which do you think would be easier, convincing Lattice to improve > their tools, or getting Xilinx to offer some Flash FPGAs in smaller > leaded packages? That's easy - talk to Lattice :) Give them an example, and convince them LOTS of users will need to do (from the IDE) what you are trying to do. -jgArticle: 129313
jasonL schrieb: > I have a project to prototype an ASIC design on FPGA. What are the > things I should do? Here is some of my concerns: Well .. good HDL code should be portable. ;-) > 1) I understand FPGAs usually have 4 look-up table. Should I rewrite > the ASIC combinational logics to be four-inputs logics to improve the > utilization of FPGA? No. Usually the FPGA is big enough. This is an advanced topic for highly-optimized designs. > 2) Netting if and case statements over three layers might results a > poor synthesis result in FPGA . Should I changes those netting codes > in ASIC RTL? Flipflops are free in FPGAs. Therefore you can pipeline your design easily. The only disadvantage are the additional clocks through the pipeline. > 3) ASIC synthesis need to generate clock tree and power rails. In FPGA > synthesis, Maybe I not need to care too much about it? Ususally you should place an instance of a component, that tells the synthesis tool to use global clocks and global signals for reset. For Xilinx this it a BUFG. > 4) Is there a to-do-list for this kind of job? Usually I replace memories with BlockRAM inside the FPGA and use instances of clock buffers. Thats it. Fully synchronous designs are easily done on FPGAs, but even highly clock-gated designs using a lot of latches run quite fine. RalfArticle: 129314
Narendra Sisodiya <narendra.sisodiya@gmail.com> writes: > May any body tell me , Any Linux Distro (other then commercial , like > redhat, i cann't buy) which will work perfectly with all > components(ISE, EDK, sysgen Matlab, chipscope etc). Try Centos 4, which is equivalent to RHEL 4.Article: 129315
Antti wrote: > On 20 Feb., 19:41, "Dwayne Dilbeck" <ddilb...@yahoo.com> wrote: > >>Be sure to send an email to Xilinx Marketing. They should be interested in >>this as well. >> > > nice to see ONE comment and optimism! > > I have tried to earn money developing development tools for product > from big companies. > And I have succeeded to get product live time earnings of around > 20.000 USD from the sale of SW development tools for Atmel AVR, but > that was it. > And I had ZERO support or interest from Atmel. Maybe I talked to wrong > guys. Well actually I made bad exclusive resell right agreement. > > So I do not have much hopes. But it would be nice to be wrong this > time. > > Antti Large companies do not manage outside tools that well, but there is growing scope for companies to offer better web examples, and especially an eco-system for open source and reference designs. They need to allocate the spend to a budget is the problem, and this falls between marketing and tools, so neither group wants to know. -jgArticle: 129316
>Never mind. Apparently the spec is now freely available here: >http://www.sdcard.org/about/memory_card/pls/ >A quick skim seems to indicate that all the necessary protocol details >are there. The SD Card Association makes available freely some limited specifications. As I understand it, the full specifications are available if you pay to join the SDA. For example, the public documents show how to operate the card up to 25MHz but don't show the different timing sequence used when running at 50MHz (although I have seen some documents which describe that and which, I assume, "leaked out"). Either way, don't expect well-written specifications. The publicly-available documents are abysmal. I'd be amazed if the full specifications were any better. The MMC/SD standards seem to be the fruits of a committee on drugs. Certainly, it's difficult to see how a sane person could invent them. This is reflected in the quality of the documents. For example, the document which claims to describe the "physical layer" actually describes just about everything but the physical layer. Also, some products widely sold with the "SD" logo don't meet the specification. MikeArticle: 129317
Dolphin <Karel.Deprez@gemidis.be> wrote: >Hello, > >Has anybody tried to use MIG with a Spartan 3 to generate a memory >controller that has a big DQ bus? I would like to generate a core that >controls 7 chips (x16), this results in 112 DQ pins. The chips would >use a clock of 133MHz. > >Has anybody got experience with the MIG tool? Is it user-friendly or >do you prefer to write your own DDR core? I'd recommend writing your own core. The designs created by MIG are demonstrators when it comes to Spartan 3 and have too much restrictions when it comes to which pins can be used. Besides, I think 133MHz is pushing the limits of the device. You probably need faster (166MHz) DDR memory in order to meet timing. -- Programmeren in Almere? E-mail naar nico@nctdevpuntnl (punt=.)Article: 129318
Jon Elson wrote: > > > Alfreeeeed wrote: > >> >> Looks like SPI Master Mode is the option. I am interested in Jon's >> alternative of putting a memory twice the size a program need. Any >> ideas how to implement this? BTW , I also need to program two FPGA >> with the same program so I would need to do daisy chain with a >> Spartan-3E. > > > Well, I'm not going to reveal all my secrets for free, but a fairly > simple scheme can be figured out for the SST chips. They need an > "instruction" byte serially shifted in to program the memory to read > from the beginning. I've often wondered why these Serial FLASH vendors have missed the REALLY OBVIOUS option, of alias of a 00 or FF opcode to read, so you could simply connect their serial memory, and just clock to stream out data. Would be 100% upward compatible with present usage. -jgArticle: 129319
I am trying to port an application from ISE/EDK 8.1i to 9.2i. Everything is going well except for one thing - the page in Software Platform Settings for specifying the interrupt handler is missing. To start, the EDK project is instantiated within an ISE project as a subcomponent. I created the new EDK project from scratch using BSB, and assigned three serial ports, a SPI interface, a couple of GPIO registers, and a hardware timer. The wizard added the interrupt and reset controller. I have two active interrupts routed to the interrupt controller - one from the SPI interface and one from the timer. I attempted to manually add the interrupt handler lines to the MSS file, but no go. The application builds just fine, and goes through early initialization just fine, but hangs the first time it attempts to do something that would cause an interrupt to fire. (specifically, the first time it attempts to write to the SPI DAC) I have rebuilt both the hardware and the BSP & libraries several times. Everything builds just fine - but I still don't get the page for interrupts. Notably, all of the interrupt options in the microblaze IP core are grayed out, which indicates that maybe the interrupts are somehow disabled in the core, but I can't imagine how. I've had this problem before in EDK 8.2i, but I don't recall how I fixed it then. Can anyone point me in the right direction? Thanks! -SethArticle: 129320
On 20 Feb., 23:13, Jim Granville <no.s...@designtools.maps.co.nz> wrote: > Jon Elson wrote: > > > Alfreeeeed wrote: > > >> Looks like SPI Master Mode is the option. I am interested in Jon's > >> alternative of putting a memory twice the size a program need. Any > >> ideas how to implement this? BTW , I also need to program two FPGA > >> with the same program so I would need to do daisy chain with a > >> Spartan-3E. > > > Well, I'm not going to reveal all my secrets for free, but a fairly > > simple scheme can be figured out for the SST chips. They need an > > "instruction" byte serially shifted in to program the memory to read > > from the beginning. > > I've often wondered why these Serial FLASH vendors have missed the > REALLY OBVIOUS option, of alias of a 00 or FF opcode to read, > so you could simply connect their serial memory, and just clock to > stream out data. Would be 100% upward compatible with present > usage. > > -jg 45LF010 had a 0xFF read opcode, but its eol ... -LasseArticle: 129321
Hi all, Is there a difference which one is instantiated when the actual VCC in the bank is 3.0V? Thanks, /MikhailArticle: 129322
MM wrote: > Hi all, > > Is there a difference which one is instantiated when the actual VCC > in the bank is 3.0V? > > > Thanks, > /Mikhail Hi Mikhail, Compare the bit files? HTH, Syms.Article: 129323
L-C wrote: > I would like to know if a FPGA is suited for this application: sound > sources localization and separation. The algorithm comes in 3 steps: > sources detection using a steered beamformer (in frequency-domain), a > particle filter to track the sources and a combination of a geometric > source separation algorithm and a non-linear post-filter for source > separation. > > Also, the audio stream comes from an array of 8 microphones, and all > possible microphone pairs must be considered during the detection > phase. > > This algorithm is already implemented of a floating point DSP and I > would like to know if a FPGA could be a good choice to improve > performance. > > I heard that a FPGA wouldn't beat a DSP in floating point calculation, > what do you think about that? Still, I know that an implementation on > a FPGA will require a lot of work to translate the code anyway, so I > suppose it wouldn't be harder to rethink it directly in fixed point. > > The FPGA could be used to improve only a fraction of the algorithm > too. > Thanks for your comments. > > L-C An FPGA solution can beat a DSP micro in floating point as well, but it depends on your implementation. The issue with floating point is that it requires a considerable amount of hardware to do the normalize and denormalize operations. Clever implementation can reduce that overhead. See my paper "Hybrid Floating Point Technique Yields 1.2 Gigasample Per Second 32 to 2048 point Floating Point FFT in a single FPGA" at www.andraka.com/papers.htm for some discussion of reducing that overhead.Article: 129324
Mike Harrison wrote: > > Looking at an FPGA as a 'step up' from a MCU, the primary advantages are > Speed, Parallelism and Pin count. The downsides are power consumption, power management ( multiple > rails), packaging ( BGAs etc.) and availability (fewer parts routinely available off-the-shelf) . > > In terms of power per equivalent operation, the FPGA nearly always wins over the DSP micro. I find the FPGA (assuming an efficient implementation) is typically around 20% of the power of a DSP micro for a given process sample rate. In other words, the FPGA can operate a significantly lower clock rate than a DSP micro operating on the same data stream. The clock rate is a huge factor in power dissipation. The biggest drawbacks for FPGAs are the relative immaturity of the tools and the relative scarcity of design talent. My usual recommendation is that if an application can be handled with a single DSP micro, that is the proper venue for it, as it is cheaper and easier to obtain the talent needed to bring the design through development.
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