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austin wrote: > Philip, > > So, here is the answer: > > "Bottom line - not a bug, no intention of dropping V2Pro support, all > better in 10.1." > > Turns out, we just haven't done all the work needed to support V7.0 in > V2Pro in 9.x, and that work is scheduled for the next release. The > "worst case scenario" of 'not supported' is not the case, and I am > impressed with the work these folks do to provide such a degree of support. Austin, Thanks very much for your reply. This is most reassuring! PhilipArticle: 129151
> Is it possible to install the last version of the free ISE on XP home > edition?let me know,please > > Thanks to you all > > Diego I can see why the website list for supported platforms would give you pause. I have XP Home at home and recall installing ISE Webpack without worry though I've only stressed the product at work with XP Pro. Is the issue that you're looking at purchasing a full ISE copy or a new computer? If you have XP Home and are itching to install ISE Webpack, go for it! Don't bother with this forum to analyze the situation... execute! And have fun with Xilinx@home! - John_H Thank you very much John actually i have ISE 9.2 mounted on my old P4 with XP Pro,and it works fine;maybe something more than the 512 MB of RAM that it mounts would be better,but the speed bottleneck is just my poor style of programming; No, the reason of my question is because a friend ,that want to begin practicing VHDL(at the age of 60,he is a senior engineer) has a laptop mounting XP home,and he would not discover that the thing is impossible after various attempt. But well,thanks to you now i can assure him that it is possible! Thanks once more Diego Milan,ItalyArticle: 129152
On Feb 15, 12:45=A0pm, John_H <newsgr...@johnhandwork.com> wrote: > On Feb 15, 8:11=A0am, FPGA <FPGA.unkn...@gmail.com> wrote: > > > > > > > I have written a process to generate sine wave. I am getting a > > distorted wave and not a pure sine wave. I am not sure if this has > > anything to do with the simulator. > > > two : process > > variable phase_temp,result : real; > > constant scale : real :=3D 2.0*real(bw); > > begin > > =A0 =A0 =A0 =A0 phase_temp :=3D phase_sin; --phase_sin; > > =A0 =A0 =A0 =A0 l1 : for i in 1 to samples_sin loop --number_of_samples = loop > > =A0 =A0 =A0 =A0 result :=3D scale*(amp_sin*(sin(frq_sin + phase_temp)));= > > =A0 =A0 =A0 =A0 sine_real <=3D (amp_sin*(sin(frq_sin + phase_temp))); > > =A0 =A0 =A0 =A0 sinWave <=3D toSigned(result,bw); > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 phase_temp :=3D phase_temp+incr_sin; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 wait for 5 ns; > > =A0 =A0 =A0 =A0 end loop l1; > > > end process two; > > > generic value : =A0 phase_sin : real :=3D 0.0; =A0 samples_sin : integer= :=3D > > 1000; =A0 incr_sin : real :=3D 1.0; > > =A0 frq_sin : real :=3D 1000.0; > > > I dont see the frequency of the wave change if the frq_sin is changed. > > Same happens when samples_sin is changed. I am not sure what is going > > wrong. Please help > > Your frq_sin value is actually just a phase offset. =A0There is no time > associated with this constant to feed the sin(). =A0The phase_temp, on > the other hand, is effectively t*incr_sin where t is a cycle count. > To see the frequency change, change the incr_sin value instead. > > In what way is your sine distorted? > > - John_H- Hide quoted text - > > - Show quoted text - How can I pass time parameter to the sineWave? I was able to remove the distortion by reducing the incr_sin value. Still not clear on the frequency and time parameter that you are talking about.Article: 129153
Symon, OK, I will go quiz the "experts." Not sure, but I do not think the "common large footprint" is a 'no-brainer' (common footprint fits all) for smaller parts (plugged onto a layout for a larger part) in V4. Stand-by, AustinArticle: 129154
On Feb 14, 1:50=A0pm, rossalbi <rossa...@hotmail.com> wrote: > hi, i have writen a pice of code which should impliment a value on > the > LEDs of my FPGA development board as the signal 'count' increases. > However it is going strait to the ' when others =3D> LEDs <=3D > "00000000"; > ' value. > > any help would be much appreciated... > > =A0 =A0 -- Declare signals > =A0 =A0 signal CLK : std_logic; > =A0 =A0 signal RST : std_logic; > =A0 =A0 signal Count : std_logic_vector(21 downto 0); > =A0 =A0 signal LEDs : std_logic_vector(7 downto 0); > =A0 =A0 signal LEDVal : std_logic_vector(7 downto 0); > =A0 =A0 signal Dir : std_logic; > > begin > > =A0 =A0 -- Tie unused signals > =A0 =A0 User_Signals <=3D "ZZZZZZZZ"; > =A0 =A0 IO_CLK_N <=3D 'Z'; > =A0 =A0 IO_CLK_P <=3D 'Z'; > =A0 =A0 IO <=3D (0=3D>LEDs(0), 1=3D>LEDs(3), 41=3D>LEDs(4), 42=3D>LEDs(1),= > 43=3D>LEDs(4), > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 44=3D>LEDs(5), 45=3D>L= EDs(2), 46=3D>LEDs(7), > others =3D> 'Z'); > > =A0 =A0 -- Clock divider > =A0 =A0 process (CLK, RST) > =A0 =A0 begin > =A0 =A0 =A0 =A0 if (RST=3D'1') then > =A0 =A0 =A0 =A0 =A0 =A0 Count <=3D (others=3D>'0'); > =A0 =A0 =A0 =A0 elsif (CLK'event and CLK=3D'1') then > =A0 =A0 =A0 =A0 =A0 =A0 Count <=3D Count + 1; > =A0 =A0 =A0 =A0 end if; > =A0 =A0 end process; > > =A0 =A0 process (CLK, RST) > =A0 =A0 begin > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 case Count is > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 when "0000000000000000000000" =3D> LEDs <= =3D "00000001"; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 when "0000000000000000000001" =3D> LEDs <= =3D "00000010"; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 when "0000000000000000000010" =3D> LEDs <= =3D "00000100"; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 when "0000000000000000000011" =3D> LEDs <= =3D "00001000"; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 when "0000000000000000000100" =3D> LEDs <= =3D "00001001"; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 . > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 . > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 when "0000000000000001111110" =3D> LEDs <= =3D "01000000"; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 when "0000000000000001111111" =3D> LEDs <= =3D "10000000"; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 when others =3D> LEDs <=3D "00000000"; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end case; > > =A0 =A0 end process; I think Count should be in the process sensitivity list. You should get the result you talked about. Cheers!Article: 129155
John_H wrote: > On Feb 15, 8:11 am, FPGA <FPGA.unkn...@gmail.com> wrote: >> I have written a process to generate sine wave. I am getting a >> distorted wave and not a pure sine wave. I am not sure if this has >> anything to do with the simulator. >> >> two : process >> variable phase_temp,result : real; >> constant scale : real := 2.0*real(bw); >> begin >> phase_temp := phase_sin; --phase_sin; >> l1 : for i in 1 to samples_sin loop --number_of_samples loop >> result := scale*(amp_sin*(sin(frq_sin + phase_temp))); >> sine_real <= (amp_sin*(sin(frq_sin + phase_temp))); >> sinWave <= toSigned(result,bw); >> phase_temp := phase_temp+incr_sin; >> wait for 5 ns; >> end loop l1; >> >> end process two; >> >> generic value : phase_sin : real := 0.0; samples_sin : integer := >> 1000; incr_sin : real := 1.0; >> frq_sin : real := 1000.0; >> >> I dont see the frequency of the wave change if the frq_sin is changed. >> Same happens when samples_sin is changed. I am not sure what is going >> wrong. Please help > > Your frq_sin value is actually just a phase offset. There is no time > associated with this constant to feed the sin(). The phase_temp, on > the other hand, is effectively t*incr_sin where t is a cycle count. > To see the frequency change, change the incr_sin value instead. > > In what way is your sine distorted? > > - John_H Change incr_sin to .1 and look at the difference in the waveform. You are stepping through the sine wave in 6 steps so you will not see what you expect. The wave will look a lot prettier with more steps.Article: 129156
Time is being implied in your phase assignment. But you are not coding the
frequency generation correctly.
You code mathematiclly is saying the following
y=A*sin(fq+x)
x=x+c
Where fq is frq_sin, and c is incr_sin the sin wave cycle lasts from 0 to
2PI. There is no time or frequency associated with it. Your fq is just
offseting the start point not seting a period. What you want to do is the
following.
x=x+c
y=A*sin(2*PI*fq*x)
now remember that x is being incremented in time. fq is in hz. You need to
inverse fq to get your period time. which yeilds.
x=x+c;
y=A*sin(2*PI*x/tp)
where tp is the cycle length.
Your code should look like so:
for i in 1 to samples_sin loop
result:= scale*(amp_sin*(sin(2.0*PI*frq_sin*phase_temp);
sine_real<=(amp_sin*(sin(2.0*MATH_PI*frq_sin*phase_temp);
sineWave<=toSigned(result,bw)
phase_temp:= phase_temp+incr_sin;
wait for 5 ns; ---Note: This 5ns is not setting the actual frequncy result
with this code
end loop;
--to see a full sine wave cycle set the following:
phase_sin=0.0;
frq_sin=1000; --(1khz)
samples_sin=1000;
incr_sin=0.000001--(1ms/1000 samples)
With this code the "5ns" doesn't do anything constructive. But you could
change the code to make it useful
If you want the time display of the code to match the values that are given
in my comments use "wait for 1us"
Just looking at the time display based on the above code would apear to have
a 200MHZ
sign wave. (1us/5ns)=200, 200*(1 khz)=200Mhz
"FPGA" <FPGA.unknown@gmail.com> wrote in message
news:9da3001a-c460-44c7-8dad-664c0f05ba4d@h11g2000prf.googlegroups.com...
On Feb 15, 12:45 pm, John_H <newsgr...@johnhandwork.com> wrote:
> On Feb 15, 8:11 am, FPGA <FPGA.unkn...@gmail.com> wrote:
>
>
>
>
>
> > I have written a process to generate sine wave. I am getting a
> > distorted wave and not a pure sine wave. I am not sure if this has
> > anything to do with the simulator.
>
> > two : process
> > variable phase_temp,result : real;
> > constant scale : real := 2.0*real(bw);
> > begin
> > phase_temp := phase_sin; --phase_sin;
> > l1 : for i in 1 to samples_sin loop --number_of_samples loop
> > result := scale*(amp_sin*(sin(frq_sin + phase_temp)));
> > sine_real <= (amp_sin*(sin(frq_sin + phase_temp)));
> > sinWave <= toSigned(result,bw);
> > phase_temp := phase_temp+incr_sin;
> > wait for 5 ns;
> > end loop l1;
>
> > end process two;
>
> > generic value : phase_sin : real := 0.0; samples_sin : integer :=
> > 1000; incr_sin : real := 1.0;
> > frq_sin : real := 1000.0;
>
> > I dont see the frequency of the wave change if the frq_sin is changed.
> > Same happens when samples_sin is changed. I am not sure what is going
> > wrong. Please help
>
> Your frq_sin value is actually just a phase offset. There is no time
> associated with this constant to feed the sin(). The phase_temp, on
> the other hand, is effectively t*incr_sin where t is a cycle count.
> To see the frequency change, change the incr_sin value instead.
>
> In what way is your sine distorted?
>
> - John_H- Hide quoted text -
>
> - Show quoted text -
How can I pass time parameter to the sineWave? I was able to remove
the distortion by reducing the incr_sin value. Still not clear on the
frequency and time parameter that you are talking about.
Article: 129157On Feb 15, 10:53=A0am, FPGA <FPGA.unkn...@gmail.com> wrote: > On Feb 15, 12:45=A0pm, John_H <newsgr...@johnhandwork.com> wrote: > > > > > On Feb 15, 8:11=A0am, FPGA <FPGA.unkn...@gmail.com> wrote: > > > > I have written a process to generate sine wave. I am getting a > > > distorted wave and not a pure sine wave. I am not sure if this has > > > anything to do with the simulator. > > > > two : process > > > variable phase_temp,result : real; > > > constant scale : real :=3D 2.0*real(bw); > > > begin > > > =A0 =A0 =A0 =A0 phase_temp :=3D phase_sin; --phase_sin; > > > =A0 =A0 =A0 =A0 l1 : for i in 1 to samples_sin loop --number_of_sample= s loop > > > =A0 =A0 =A0 =A0 result :=3D scale*(amp_sin*(sin(frq_sin + phase_temp))= ); > > > =A0 =A0 =A0 =A0 sine_real <=3D (amp_sin*(sin(frq_sin + phase_temp))); > > > =A0 =A0 =A0 =A0 sinWave <=3D toSigned(result,bw); > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 phase_temp :=3D phase_temp+incr_sin; > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 wait for 5 ns; > > > =A0 =A0 =A0 =A0 end loop l1; > > > > end process two; > > > > generic value : =A0 phase_sin : real :=3D 0.0; =A0 samples_sin : integ= er :=3D > > > 1000; =A0 incr_sin : real :=3D 1.0; > > > =A0 frq_sin : real :=3D 1000.0; > > > > I dont see the frequency of the wave change if the frq_sin is changed.= > > > Same happens when samples_sin is changed. I am not sure what is going > > > wrong. Please help > > > Your frq_sin value is actually just a phase offset. =A0There is no time > > associated with this constant to feed the sin(). =A0The phase_temp, on > > the other hand, is effectively t*incr_sin where t is a cycle count. > > To see the frequency change, change the incr_sin value instead. > > > In what way is your sine distorted? > > > - John_H- Hide quoted text - > > > - Show quoted text - > > How can I pass time parameter to the sineWave? I was able to remove > the distortion by reducing the incr_sin value. Still not clear on the > frequency and time parameter that you are talking about.- Hide quoted text= - > > - Show quoted text - Phase accumulators are used to mark the prograssion of time. You want sin(f*T) which is sin(f*n*deltaT) where deltaT is your clock period. f*n*deltaT is the same as sum from 1 to n of f*deltaT, this last item being a constant. That's what you're doing with the incr_sin, isn't it? If you have an increment of 1/100 of a sinusoidal period, the sum of 100 increments will be one sinusoidal period bringing you right back to the beginning. You *are* doing this for simulation only, aren't you? - John_HArticle: 129158
In Virtex 5's, the minimum output frequency that a DCM can output is 32Mhz and the minimum output frequency that a PLL can output is 19Mhz (this info is from one of the V5 guide's) I have had this issue where in my DCM was getting locked intermittently when I was trying to output a 30Mhz clock from a DCM. Hope this info helps.. --parag On Feb 12, 1:02 pm, deltabravosi...@gmail.com wrote: > On Feb 11, 6:52 pm, michel.ta...@gmail.com wrote: > > > > > Hi all, > > > I've a problem.. :) > > I have to divide a 48MHz clock to obtain a clock with differents > > frequencies : 100KHz, 500KHz, 1 MHz or 2 MHz. > > First I used flips flops to make a frequency divider, I obtained the > > good frequencies, but I had skew between my master clock (48MHz) and > > my divided clock. > > So, I tried to use a DCM to divide frequency and to deskew divided > > clock using the CLKFB input. But, the problem is the lower limit of > > the DCM output frequency (1MHz) .. > > > So, if anyone have an idea ? > > > Thanks by advance, > > > Best regards, Michel. > > I believe Regional clock buffers in V5 have divider functionality > available......so use DCM to generate Mhz clocks and then pass lowest > mhz clock to a Regional clock buffer in divider mode and you have > clocks with minimum skew. only thing you would need two regional clock > buffers to avoid cumilative skew on 100khz clockArticle: 129159
Hi, I'm designing a platform on a Xilinx Virtex 4 FX60 chip and I am somewhat conerned at the capabilities of the PLB bus in the system. I require very high throughput and I'm conerned that the PLB will be the main bottle neck in the design. I have two approches, use the PLB for all traffic in the system, or offload some of that traffic to a dedicated interface on the MPMC IP that Xilinx provides. I think, eventually, for the very high bandwidth requirements, the MPMC solution is the way to go, but I would like to get a ball park figure of the capabilities of the PLB bus in general. Given that the bus is 64bits, what would be a typically figure for PLB bus frequency: 50, 100, 150, 200Mhz? Would going to a high speed-grade FPGA alter this figure significantly? Thanks for any info, StephenArticle: 129160
On 16 Feb., 13:44, Steve <stephe...@gmail.com> wrote: > Hi, > > I'm designing a platform on a Xilinx Virtex 4 FX60 chip and I am > somewhat conerned at the capabilities of the PLB bus in the system. I > require very high throughput and I'm conerned that the PLB will be the > main bottle neck in the design. I have two approches, use the PLB for > all traffic in the system, or offload some of that traffic to a > dedicated interface on the MPMC IP that Xilinx provides. I think, > eventually, for the very high bandwidth requirements, the MPMC > solution is the way to go, but I would like to get a ball park figure > of the capabilities of the PLB bus in general. > > Given that the bus is 64bits, what would be a typically figure for PLB > bus frequency: 50, 100, 150, 200Mhz? > > Would going to a high speed-grade FPGA alter this figure > significantly? > > Thanks for any info, > > Stephen VERY ballpark: 100MHz sometimes higher too, ML505 ref design is 125MHz as example AnttiArticle: 129161
John, this is true that if you count 2:1 muxes the bitonic sort is (a bit) less expensive) but it's latency compared to the method I suggest is higher. Moreover, if you implement this in an FPGA the solution I proposed might even be cheaper since the FPGA LUTs will be used more efficiently. I will have to check this in more detail but I don't think there is a clear cut optimal solution here. cheers, Nir http://asicdigitaldesign.wordpress.comArticle: 129162
So, around about 100Mhz? It's fair to say that there is no defined upper limit on the clock frequency in the EDK and that the maximum is basically determined by ISE and the FPGA? On 16 Feb, 16:30, Antti <Antti.Luk...@googlemail.com> wrote: > On 16 Feb., 13:44, Steve <stephe...@gmail.com> wrote: > > > > > Hi, > > > I'm designing a platform on a Xilinx Virtex 4 FX60 chip and I am > > somewhat conerned at the capabilities of the PLB bus in the system. I > > require very high throughput and I'm conerned that the PLB will be the > > main bottle neck in the design. I have two approches, use the PLB for > > all traffic in the system, or offload some of that traffic to a > > dedicated interface on the MPMC IP that Xilinx provides. I think, > > eventually, for the very high bandwidth requirements, the MPMC > > solution is the way to go, but I would like to get a ball park figure > > of the capabilities of the PLB bus in general. > > > Given that the bus is 64bits, what would be a typically figure for PLB > > bus frequency: 50, 100, 150, 200Mhz? > > > Would going to a high speed-grade FPGA alter this figure > > significantly? > > > Thanks for any info, > > > Stephen > > VERY ballpark: 100MHz > sometimes higher too, ML505 ref design is 125MHz as example > > AnttiArticle: 129163
Steve wrote: > Hi, > > I'm designing a platform on a Xilinx Virtex 4 FX60 chip and I am > somewhat conerned at the capabilities of the PLB bus in the system. > Given that the bus is 64bits, what would be a typically figure for PLB > bus frequency: 50, 100, 150, 200Mhz? > I don't have the datasheets with me, but if you're running the PPC, then I think you're limited to certain multiples of PPC frequency. I ran the PPC at 300MHz and the PLB at 100MHz (on V2Pro and FX60). I found the real issue was the implementation of the PLB Bus. There was a long combinatorial path that always failed timing, especially as more logic was added to the chip. I spent about a week with PlanAhead tweaking a layout that would consistently route with no errors. > Would going to a high speed-grade FPGA alter this figure > significantly? Maybe not significantly, but a faster chip would give more timing margin. --- Joe Samson Pixel VelocityArticle: 129164
I work for a Linux software house and would like to offer a "Hello, World!" tutorial for FPGAs. The idea is to keep it simple and low cost. The Digilent Basys board looks good for cost but not for (Linux) simplicity. I'd sure like to avoid the windrv module and the parallel port cable. Does anyone know of a way to program the Basys board over the USB cable using Linux? thanks Bob SmithArticle: 129165
This is a benchmark test cd, to get performance data for a specific computer setup. Please contribute by posting a followup with the results from the 'real' column. It's a complete 227 MB zipped .iso file that needs to be written to a cd and booted. Login as toor, type bench.sh, type the data in a followup to this posting. A complete collection of testdata can be found in the '/tmp/ sHHMMSS.tbz' file. And it can be copied by running 'mnt_usb.pl && cp - p /tmp/s??????.tbz /mountpount/usb0 && umount /mountpoint/usb0' or you can simple type down the numbers for 'real' and type them here. If you have any security concerns, please feel free to browse the cd volume. Link to the bootcd: http://www.eatlime.com/download.lc?sid=7F88C923-0B51-1E23-1EEC-53ED80BBA9BC http://tinyurl.com/2j8bor I hope this will shed some better light as to which computer configurations that will perform better or worse for fpga synhtesis- place-route process. A Pentium-III 800 MHz takes approx 25m on the fpga test. Intel core2 ~300s, AMD64 ~500s (free from memory). Please use exact numbers.Article: 129166
Hi,
I'm currently facing a problem downloading my design to FPGA as my
design has overutilized the FPGA resources (slice and DSP48). I'm
using FIR compiler_v1 for both my lowpass and notch filter, I
understand that my notch filter is probably the cause of the error as
it overshot my board's resources (virtex4, xc4vfx12-10ff668). Is there
any kind soul who can advise me on ways to reduce the filter
resources? Thanks in advance. Below is the summary of the error
statement.
best regards,
Zhi Qiang
Running delay-based LUT packing...
ERROR:Pack:2310 - Too many comps of type "DSP48" found to fit this
device.
ERROR:Map:115 - The design is too large to fit the device. Please
check the
Design Summary section to see which resource requirement for your
design
exceeds the resources available in the device. In particular check
the
non-slice resources since the slice counts may reflect the early
termination
of the flow.
Design Summary:
Number of errors: 2
Number of warnings: 3
Logic Utilization:
Number of Slice Flip Flops: 9,993 out of 10,944 91%
Number of SLICEMs: 5,332 out of 2,736 194%
(OVERMAPPED)
(SLICEMs can only be placed in SLICEM sites.)
Number of 4 input LUTs: 2,028 out of 10,944 18%
Logic Distribution:
Number of occupied Slices: 8,764 out of
5,472 160%
(OVERMAPPED)
Number of Slices containing only related logic: 8,764 out of
8,764 100%
Number of Slices containing unrelated logic: 0 out of
8,764 0%
*See NOTES below for an explanation of the effects of unrelated
logic
Total Number of 4 input LUTs: 7,469 out of 10,944 68%
Number used as logic: 2,028
Number used as a route-thru: 109
Number used as Shift registers: 5,332
Number of bonded IOBs: 1 out of 320 1%
Number of BUFG/BUFGCTRLs: 3 out of 32 9%
Number used as BUFGs: 1
Number used as BUFGCTRLs: 2
Number of FIFO16/RAMB16s: 2 out of 36 5%
Number used as FIFO16s: 0
Number used as RAMB16s: 2
Number of DSP48s: 294 out of 32 918%
(OVERMAPPED)
Number of BSCAN_VIRTEX4s: 1 out of 4 25%
Article: 129167veriqiang@gmail.com wrote: > Is there > any kind soul who can advise me on ways to reduce the filter > resources? If you don't need high speed, you could try to serialize your filter, i.e. one multiply-add per clock. If you need it faster, then split it in larger blocks: for n FIR taps, calculate n/s taps per clock, with s=2, 3, 4, as large as small clk/s could be. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 129168
CPU: AM2 Athlon-64 X2 5600 RAM: 2GB DDR2 PC6400 (5-5-5-15) Mainboard: Asus M2A-VM (M690G with integrated graphics) FPGA-Test(Real) 326,19 fcdup8k@yahoo.com schrieb: > This is a benchmark test cd, to get performance data for a specific > computer setup. Please contribute by posting a followup with the > results from the 'real' column. > > It's a complete 227 MB zipped .iso file that needs to be written to a > cd and booted. Login as toor, type bench.sh, type the data in a > followup to this posting. > A complete collection of testdata can be found in the '/tmp/ > sHHMMSS.tbz' file. And it can be copied by running 'mnt_usb.pl && cp - > p /tmp/s??????.tbz /mountpount/usb0 && umount /mountpoint/usb0' or you > can simple type down the numbers for 'real' and type them here. > If you have any security concerns, please feel free to browse the cd > volume. > > Link to the bootcd: > http://www.eatlime.com/download.lc?sid=7F88C923-0B51-1E23-1EEC-53ED80BBA9BC > > http://tinyurl.com/2j8bor > > I hope this will shed some better light as to which computer > configurations that will perform better or worse for fpga synhtesis- > place-route process. > A Pentium-III 800 MHz takes approx 25m on the fpga test. Intel core2 > ~300s, AMD64 ~500s (free from memory). Please use exact numbers.Article: 129169
Hi, My Project title is "Serial RF Core for Multimedia Stream Transfer" I am using Xilinx Video Starter Kit, and I supposed to transfer a video stream over RF, using Bluetooth, I am totally confused , how to proceed, for this problem. May any body help me out for solving this problem, Do I need to first transfer a video stream over wire USB and and add some USB-Bluetooth Dongle. Please gurus help me our by giving some block diagrams or some guidance.Article: 129170
Hi c.a.f. folks for anyone wishing to say hello at Embedded, I am planning to be there on 28th afternoon, say will be around Xilinx booth at 16:00 Antti Lukats P.S. I hope I will have my handheld wi-fi enabled JTAG configurator with me to play with.Article: 129171
Frank Buss wrote: > veriqiang@gmail.com wrote: > >> Is there >> any kind soul who can advise me on ways to reduce the filter >> resources? > > If you don't need high speed, you could try to serialize your filter, > i.e. one multiply-add per clock. If you need it faster, then split it > in larger blocks: for n FIR taps, calculate n/s taps per clock, with > s=2, 3, 4, as large as small clk/s could be. Right. Take a look at http://andraka.com/distribu.htm to see how it's done! Also, even though your slices are 100% used, that doesn't mean disaster. The P&R tool spreads the LUTs out over the slices. The LUT count is a more meaniful measure of the 'fullness' of your design. Lastly, an FIR filter is often not the right solution for a notch filter, especially when the notch width is small compared to Fs/2. It will use an awful lot of resource. Perhaps you could consider an IIR filter for this function? More complex, but smaller footprint. Cheers, Syms.Article: 129172
On Sun, 17 Feb 2008 02:04:54 -0800 (PST), Narendra Sisodiya wrote: >Hi, My Project title is "Serial RF Core for Multimedia Stream >Transfer" >I am using Xilinx Video Starter Kit, and I supposed to transfer a >video stream over RF, using Bluetooth, >I am totally confused Thanks for being so honest :-) I think your first and by far your most important task is to have a long and open discussion with your prof about what the real objectives of this project should be. Like many technology tasks, it's something that you *could* do with off-the-shelf components and software. Somewhere, buried in all of it, there is an interesting project trying to get out. But if you were to try to do *all* of it as a project (undergraduate? masters?) then you are sure to fail horribly, because there is simply far too much in it. Let's look at the whole thing: * video source * video capture into memory * video compression (Bluetooth data rate is far too slow for raw video) * buffering for streaming * package the data in an appropriate form for delivery over Bluetooth * Bluetooth link * reversing the above steps to recover a useful video stream for display Which parts of this do you plan to do yourself? Bluetooth is pretty complicated at all levels, and no-one in their right mind would try to do it from scratch; you simply buy the modules. Every one of the other parts of the chain is similarly a solved problem. Some of it is best done in software, some is best done in hardware. Some parts of the problem make sense as an FPGA project (camera interface, compression) but are so common that it's just a matter of tailoring existing freely-available design examples. For me, the really tough parts would be the software (in particular, device drivers) but other folk would find that straightforward and would find other parts difficult. Choose your project focus, in collaboration with your prof. Agree with him/her what pre-built components you can use as a starting point. Learn about those pre-built components so that you can see what to do around them - how to interface to them, what data rates they support, that sort of thing. Look at the overall architecture that is required, and try to get an estimate of how much work is involved in each piece. Whatever you try to do first, make sure that you can test it stand- alone so that your project has *some* useful outcome even if it's never completed. PLAN and DISCUSS. And, as a last resort, don't be ashamed to ask your prof for a project that has a somewhat narrower scope. (Actually, the very last resort is a career change; but that's a bit drastic.) Good luck. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 129173
On Feb 17, 4:04 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > On Sun, 17 Feb 2008 02:04:54 -0800 (PST), Narendra Sisodiya wrote: > >Hi, My Project title is "Serial RF Core for Multimedia Stream > >Transfer" > >I am using Xilinx Video Starter Kit, and I supposed to transfer a > >video stream over RF, using Bluetooth, > >I am totally confused > > Thanks for being so honest :-) > > I think your first and by far your most important task is > to have a long and open discussion with your prof about > what the real objectives of this project should be. > Like many technology tasks, it's something that you *could* > do with off-the-shelf components and software. Somewhere, > buried in all of it, there is an interesting project > trying to get out. But if you were to try to do *all* > of it as a project (undergraduate? masters?) then you are > sure to fail horribly, because there is simply far too > much in it. Let's look at the whole thing: > > * video source > * video capture into memory > * video compression (Bluetooth data rate is > far too slow for raw video) > * buffering for streaming > * package the data in an appropriate form for > delivery over Bluetooth > * Bluetooth link > * reversing the above steps to recover a > useful video stream for display > > Which parts of this do you plan to do yourself? > Bluetooth is pretty complicated at all levels, > and no-one in their right mind would try to do > it from scratch; you simply buy the modules. > Every one of the other parts of the chain is > similarly a solved problem. Some of it is best > done in software, some is best done in hardware. > Some parts of the problem make sense as an FPGA > project (camera interface, compression) but are > so common that it's just a matter of tailoring > existing freely-available design examples. > > For me, the really tough parts would be the > software (in particular, device drivers) but > other folk would find that straightforward and > would find other parts difficult. > > Choose your project focus, in collaboration with > your prof. Agree with him/her what pre-built > components you can use as a starting point. Learn > about those pre-built components so that you can > see what to do around them - how to interface to > them, what data rates they support, that sort of > thing. Look at the overall architecture that is > required, and try to get an estimate of how much > work is involved in each piece. Whatever you try > to do first, make sure that you can test it stand- > alone so that your project has *some* useful outcome > even if it's never completed. > > PLAN and DISCUSS. And, as a last resort, don't be > ashamed to ask your prof for a project that has a > somewhat narrower scope. (Actually, the very last > resort is a career change; but that's a bit drastic.) > > Good luck. > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. Thanks for your kind guidance, Actually I started with ML310 board, and tried to install Linux on that. I was thinking I have use C++ libraries to capture and process the video stream and install some rtsp server kind of thing which will take care of streaming part. essentially it was streaming over internet protocol and at lower layer (1 -2 ), i was planning to use UWB chipsets. This idea was rejected as we do not have WUSB chip and kit. I have a old ericsson bluetooth toolkit which i a fear to connect with PC also. (many time my PC restart when I tried to execute demo application,) Now for the timings I am first trying to capture the video frame in some memory . I am new to this VSK kit (ML402), I unable to think which way to proceed. Initially i am also thinking to route the video stream to USB , but no idea what i am doing properly.Article: 129174
On Feb 15, 3:21=A0pm, John_H <newsgr...@johnhandwork.com> wrote: > On Feb 15, 10:53=A0am, FPGA <FPGA.unkn...@gmail.com> wrote: > > > > > > > On Feb 15, 12:45=A0pm, John_H <newsgr...@johnhandwork.com> wrote: > > > > On Feb 15, 8:11=A0am, FPGA <FPGA.unkn...@gmail.com> wrote: > > > > > I have written a process to generate sine wave. I am getting a > > > > distorted wave and not a pure sine wave. I am not sure if this has > > > > anything to do with the simulator. > > > > > two : process > > > > variable phase_temp,result : real; > > > > constant scale : real :=3D 2.0*real(bw); > > > > begin > > > > =A0 =A0 =A0 =A0 phase_temp :=3D phase_sin; --phase_sin; > > > > =A0 =A0 =A0 =A0 l1 : for i in 1 to samples_sin loop --number_of_samp= les loop > > > > =A0 =A0 =A0 =A0 result :=3D scale*(amp_sin*(sin(frq_sin + phase_temp= ))); > > > > =A0 =A0 =A0 =A0 sine_real <=3D (amp_sin*(sin(frq_sin + phase_temp)))= ; > > > > =A0 =A0 =A0 =A0 sinWave <=3D toSigned(result,bw); > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 phase_temp :=3D phase_temp+incr_sin;= > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 wait for 5 ns; > > > > =A0 =A0 =A0 =A0 end loop l1; > > > > > end process two; > > > > > generic value : =A0 phase_sin : real :=3D 0.0; =A0 samples_sin : int= eger :=3D > > > > 1000; =A0 incr_sin : real :=3D 1.0; > > > > =A0 frq_sin : real :=3D 1000.0; > > > > > I dont see the frequency of the wave change if the frq_sin is change= d. > > > > Same happens when samples_sin is changed. I am not sure what is goin= g > > > > wrong. Please help > > > > Your frq_sin value is actually just a phase offset. =A0There is no tim= e > > > associated with this constant to feed the sin(). =A0The phase_temp, on= > > > the other hand, is effectively t*incr_sin where t is a cycle count. > > > To see the frequency change, change the incr_sin value instead. > > > > In what way is your sine distorted? > > > > - John_H- Hide quoted text - > > > > - Show quoted text - > > > How can I pass time parameter to the sineWave? I was able to remove > > the distortion by reducing the incr_sin value. Still not clear on the > > frequency and time parameter that you are talking about.- Hide quoted te= xt - > > > - Show quoted text - > > Phase accumulators are used to mark the prograssion of time. =A0You want > sin(f*T) which is sin(f*n*deltaT) where deltaT is your clock period. > f*n*deltaT is the same as sum from 1 to n of f*deltaT, this last item > being a constant. > > That's what you're doing with the incr_sin, isn't it? =A0If you have an > increment of 1/100 of a sinusoidal period, the sum of 100 increments > will be one sinusoidal period bringing you right back to the > beginning. > > You *are* doing this for simulation only, aren't you? > > - John_H- Hide quoted text - > > - Show quoted text - This is for simulation only. Thanks for all your comments. I will make the suggested changes and let you guys know how it went.
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