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PFC wrote: (snip) > I don't know about the PHY you use, but usually after reset, an > Ethernet PHY needs to be talked to softly using the MII protocol, which > you then use to setup autonegociation, bring the link up, after which (snip) > Ah, and yeah, you'll need somse sort of CPU to go through that > initialization routine. Depending on the definition of CPU. It could presumably be done by a state machine which may or may not follow one's definition of CPU. -- glenArticle: 132651
PFC wrote: > So I thought about Spartan-3A DSP but it has a packaging problem : > 0.8mm BGA ! No way. 1mm is fine but not 0.8mm. What's the big deal? I'm no expert, but is 0.8mm that much more difficult to deal with than 1.0? > Also this board will be used as part of an open source project. > We'll make a board fab run and sell them so people can hack them. Interesting. Are you planning to sell blank boards or stuffed ones? Will the PCB database be open source, or just gerber files? What particular audio applications do you think people would use it for? > I would really prefer if those guys could use free (as in beer) > software and EDK is a problem there. But, so is the small collection of > free Altera cores... > > So, from my project description above, what could I do ?... What would your board bring to the table not available from the jillion of dev boards out there? multichannel audio I'm guessing. What if you made an interface board with a lot of audio on it and made it where it could connect to umpteen different boards already available. Then you could quickly adapt your IP designs to new generation devices next year and the year after. -JeffArticle: 132652
Ambreen Ashfaq Afridi wrote: > Now the issue is that how will i extract tcp and IP information from > the ethernet frame? What libraries would i include while coding it in > verilog? A little more detail would help. I would say you could extract UDP with a fairly simple state machine, but would want a real CPU of some kind for TCP. TCP has to be able to put the stream back together even when the data arrives out of order. (Technically you need to do fragment reassembly for IP, but maybe you can get out of that one.) TCP also needs to ACK for what has arrived, deal with multiple copies of data, and even more. Use UDP if you can. -- glenArticle: 132653
"PFC" <lists@peufeu.com> wrote in message news:op.ub8qcrlocigqcu@apollo13.peufeu.com... > > I have a few questions about Xilinx and Altera (actually Spartan-3E > versus Cyclone III) which relate to a particular project, so here are the > specifics. > <snip> > Also this board will be used as part of an open source project. We'll > make a board fab run and sell them so people can hack them. > I would really prefer if those guys could use free (as in beer) software > and EDK is a problem there. But, so is the small collection of free Altera > cores... > > So, from my project description above, what could I do ?... > 1. Benchmark both with something resembling the final design. You should have all the logic connected to at least drive all of the external output/inout pins and use all of the input to at least do 'something'. For the IP that you'll be developing you'll need to generate it in a vendor neutral way, which can usually be done (except for non-inferrable things like PLL/DLLs). Try out the vendor specific cores for things you're missing even if they won't necessarily be in the final design. 1a. Try not to get too wrapped around the axle about having everything functional before moving on. There is a bit of a risk but as long nothing is getting totally optomized away, you should be able to make a reasonable benchmark. 2. Run the designs through place and route. Pay attention to the reports about unneeded I/O, make sure nothing gets optomized away, make sure that IP blocks are consuming resources (an unconnected input or output in an internal block can make the whole thing disappear). 3. Decide on what metrics are important for your project (i.e. device cost, clock speed, packaging, bigger parts in the same package, tool hassles, etc.) and evaluate all the FPGA vendors based on those metrics...also may not necessarily want to exclude the 'other guys' beside brand A and X. They're the two biggest, not the only ones. Kevin JenningsArticle: 132654
PFC wrote: <snip> > Also this board will be used as part of an open source project. > We'll make a board fab run and sell them so people can hack them. > I would really prefer if those guys could use free (as in beer) > software and EDK is a problem there. But, so is the small collection of > free Altera cores... > > So, from my project description above, what could I do ?... Lattice have an open source, 32 bit processor core. Add that to your short list ? - this sounds fairly core-agnostic, so you could start with a Xilinx/Altera core, then move to lattice as the system is proven, and ready for wider deployment. -jgArticle: 132655
>> So I thought about Spartan-3A DSP but it has a packaging problem : >> 0.8mm BGA ! No way. 1mm is fine but not 0.8mm. > > What's the big deal? I'm no expert, but is 0.8mm that much more > difficult to deal with than 1.0? It adds a lot to board cost. This is a hobby project, lol. >> Also this board will be used as part of an open source project. >> We'll make a board fab run and sell them so people can hack them. > > Interesting. Are you planning to sell blank boards or stuffed ones? Will > the PCB database be open source, or just gerber files? What particular > audio applications do you think people would use it for? Stuffed, I doubt people would want to solder the BGA... Open source, And multichannel remote audio soundcard with DSP capabilities. One of the guys is more interested in recording capabilities and I'm more interested in playback, anyway the hardware is the same, only difference is the number of ADC/DACs in the daughterboard... But since it's an FPGA and the audio stuff will be on a separate (much cheaper to manufacture) board it could be pretty much anything else... The "remote" part will be either ethernet (currently prototyped) or FireWire with a DICE chip (this is under review). It is not very fixed at the moment. But since Ethernet adds little cost and can serve many purposes it is here to stay. > What would your board bring to the table not available from the jillion > of dev boards out there? Low noise/EMI, small, cheap, and ethernet that works without headaches. Believe it or not I found no such thing on the market. > Lattice have an open source, 32 bit processor core. > Add that to your short list ? - this sounds fairly core-agnostic, > so you could start with a Xilinx/Altera core, then move to lattice > as the system is proven, and ready for wider deployment. Chips are hard to obtain for a hobby project. DigiKey et al only stock X & A...Article: 132656
http://www.edn.com/article/CA6566989.htmlArticle: 132657
PFC wrote: >> Lattice have an open source, 32 bit processor core. >> Add that to your short list ? - this sounds fairly core-agnostic, >> so you could start with a Xilinx/Altera core, then move to lattice >> as the system is proven, and ready for wider deployment. > > > Chips are hard to obtain for a hobby project. DigiKey et al only > stock X & A... I was talking about the core, not the silicon. http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/index.cfm If this is an open-source project, it makes sense to use an open source core ? Also, Lattice Silicon is available from Mouser, and Jameco et al. -jgArticle: 132658
Hello, In the version of partial reconfiguration tools for ISE 9.1i SP2, Xilinx released several reference designs using the ML403 board which includes a virtex4 FPGA. I tryed to implement the lab3 that uses HWICAP for partial reconfiguration of Virtex4. I'm using EDK 9.1.02. However, when implementing this lab form scratch, I got errrors when starting the command "Build All User Applications". Xilinx also provided the solution files for each labs. When I tried to open the file system.xmp from the solution files for lab3 I was unable to open it. I got the following error: ERROR:Portability:90 - Command line error: Unexpected argument[2] "Reconf" found. Does anyone know something about this? or Has anybody implemented any of the PR Flow Design Examples Using ML403 and HWICAP? Thanks in advance.Article: 132659
Symon wrote: > http://www.edn.com/article/CA6566989.html > Saw that. Wonder if Austin will be along shortly, to claim Xilinx is (once again) leading the pack... ;) -jgArticle: 132660
Seems there is room for one more ? http://www.siliconbluetech.com/news.html This seems to push the low-power envelope a little higher in total gates (but still small, compared to the top-end FPGAs). What IS new, is the combination of 65nm process, and uA Icc numbers. They also have targeted 32Khz operation, a data point many others simply ignore. Look to be still in early-silicon stages.... Anyone actually got some devices/tools ? -jgArticle: 132661
MPMC and PLB can run at different frequencies. I don't think there is a need for a relation between them atleast from what I have read from the docs. Also are you using a GTP/GTX , then you need a 200Mhz clock for the GTP's and 125Mhz for the PHY. If not I am not sure why do you need a 200Mhz clock for the TEMAC... Also the other question I have is by a "clock generator", do you mean an external clock generator or just an clock generator IC. If you can provide more info, then probably I can help you out. You can also look at reference designs from Xilinx for ML505/ML506. --parag On Jun 3, 12:30 am, chrisde...@gmail.com wrote: > Hi, > does anybody have any experience in using Virtex 5 FPGA with > > 1) MPMC > 2) tr-mode ethernet MAC hard core with the xps_ll_temac and the > ll_fifo? > > The card I am working on has an input of 100 MHz. this is the problem > that I face, something which i am not sure: > > 1) MPMC has to run at a multiple of 133 MHz etc...thus the whole > microblaze PLB system has to run at 133 MHz? > 2) the xps_ll_temac requires some clocks like MGTCLK and GTX_CLK_0 at > 125 MHz and 200 MHz respectively. Can these clocks required by the > TEMAC be generated off the clock generator such that they are not > running at same frequency as the system clock (ie the PLB bus clock > SPB_Clk). > > does anyone have any idea? > > thanks! > ChrisArticle: 132662
On Jun 4, 6:42=A0pm, Jim Granville <no.s...@designtools.maps.co.nz> wrote: > Symon wrote: > >http://www.edn.com/article/CA6566989.html > > Saw that. > > Wonder if Austin will be along shortly, to claim Xilinx is > (once again) leading the pack... ;) > > -jg C'mon, be nice. This is not funny. It's the very first lay-off in the 25-year history of Xilinx. PeterArticle: 132663
>
> What's the big deal? I'm no expert, but is 0.8mm that much more
difficult to deal with than 1.0?
It adds a lot to board cost. This is a hobby project, lol.
I just did an ARM chip that had .65mm ball pitch. There aren't a lot of
guys that can laser drill and do a 3/3 technology. Yes, you pay, but get
used to it--things are getting smaller!!
PFC wrote:
>>> So I thought about Spartan-3A DSP but it has a packaging problem
>>> : 0.8mm BGA ! No way. 1mm is fine but not 0.8mm.
>>
>> What's the big deal? I'm no expert, but is 0.8mm that much more
>> difficult to deal with than 1.0?
>
> It adds a lot to board cost. This is a hobby project, lol.
>
>>> Also this board will be used as part of an open source project.
>>> We'll make a board fab run and sell them so people can hack them.
>>
>> Interesting. Are you planning to sell blank boards or stuffed ones?
>> Will the PCB database be open source, or just gerber files? What
>> particular audio applications do you think people would use it for?
>
> Stuffed, I doubt people would want to solder the BGA...
> Open source,
> And multichannel remote audio soundcard with DSP capabilities.
> One of the guys is more interested in recording capabilities and I'm
> more interested in playback, anyway the hardware is the same, only
> difference is the number of ADC/DACs in the daughterboard...
>
> But since it's an FPGA and the audio stuff will be on a separate
> (much cheaper to manufacture) board it could be pretty much anything
> else...
> The "remote" part will be either ethernet (currently prototyped) or
> FireWire with a DICE chip (this is under review). It is not very fixed
> at the moment. But since Ethernet adds little cost and can serve many
> purposes it is here to stay.
>
>> What would your board bring to the table not available from the
>> jillion of dev boards out there?
>
> Low noise/EMI, small, cheap, and ethernet that works without
> headaches. Believe it or not I found no such thing on the market.
>
>> Lattice have an open source, 32 bit processor core.
>> Add that to your short list ? - this sounds fairly core-agnostic,
>> so you could start with a Xilinx/Altera core, then move to lattice
>> as the system is proven, and ready for wider deployment.
>
> Chips are hard to obtain for a hobby project. DigiKey et al only
> stock X & A...
Article: 132664Hello, I have 2 boards, of which one has PPC core and other do not. [board1 /w PPC]-------uart-------[board2 /wo PPC] I want to use UART as a debug interface for board2. So,I am looking for a UART Master core that shall be Maser on the PLB/ OPB bus that I can use it in board2 FPGA. The Xilinx EDK library provide UART cores that has PLB/OPB interfaces as core side interfaces. But these interfaces are Slave interface. Do anyone has UART core (Master on PLB/OPB)? Is it advisable to go for such setup? Thank you. Best regards, MuthuArticle: 132665
On 4 Jun., 23:16, Stef <stef...@yahooI-N-V-A-L-I-D.com.invalid> wrote: > This works in both pre- and post-synthesis simulation and also in real > hardware. There is now an 8-bit comparator found for the compare line > and no more warning about constant values. > > So my question is: Is there a problem with comparing and updating a > value in the same state (clock)? No as a general problem. The code shown is IMHO synthesisable. Only strange thing I see is lastval beeing updatet again at the falling edge of clock, but the code shown here should work right. However I would change this code in case of trouble, as this code might easily mask problems resulting from other parts of the design (eg. if you have a module where clk and data change their order in timing). It might be also possible, that Xst struggles with this code even if it the overall design is correct. Try if other tools behave well with this code. bye ThomasArticle: 132666
On 2008-06-04, AchatesAVC <AchatesAVC@gmail.com> wrote: > To try to test his out I thought I would plug my computer and the > board into a router. I have a C program that I wrote which picks up > and prints UDP packets sent to the appropriate port. I put the IP > address of my computer as when plugged into the router and tried to > send the packets there. However, no data seems to be getting through. > Furthermore, the absence of link up lights on both the router and the > board seem to indicate that the bord is not able to link to the > router. At a first guess this seems like the PHY is still in reset. Doublecheck that you have setup the reset signal correctly in your design. (UCF file and polarity respectively.) If that seems ok you can try to talk to the PHY via the MII as another poster suggested. /AndreasArticle: 132667
Zorjak schrieb: > On Jun 4, 7:46 am, backhus <n...@nirgends.xyz> wrote: >> Hi Zoran, > Thank you very much for the help. > > Yes you were right. My code wasn't good. The stupid mistake in code. I > can't believe what I've wrote. But you must admit that warring that I > was getting from ISE were totally unasociative. That confused me > totally. :):) > > Thank you one more time for all your help > Zoran Hi Zoran, when there's a problem with code semantic, warnings are just indirect hints. Just before the sections where the warnings are generated you can read this: ========================================================================= * HDL Analysis * ========================================================================= Analyzing generic Entity <counter> in library <work> (Architecture <Behavioral>). width = 8 INFO:Xst:2679 - Register <Q_internal> in unit <counter> has a constant value of 00000000 during circuit operation. The register is replaced by logic. Entity <counter> analyzed. Unit <counter> generated. And the info tells you, that there is no counter anymore since the counter register has been replaced by a constant value. And at that point all alarms should ring that something went terribly wrong. (Unless you know what you did, and did it for a purpose.) So, even when you get no errors and warnings at all, always have a look at the infos and other messages in the synthesis report. Besides, a simulation should have shown you that your counter isn't working anyway. Have a nice synthesis EilertArticle: 132668
PFC wrote: > > Sorry about the title, everyone put down the flamethrowers, lol. > > I have a few questions about Xilinx and Altera (actually Spartan-3E > versus Cyclone III) which relate to a particular project, so here are > the specifics. > Currently the prototype system is on a Spartan-3E 500 to validate > the design, and it works. This was for development, though, as for the > final version a larger FPGA is needed ; the 500E is starting to feel a > bit tight. > > This FPGA system has : > > - Microblaze with caches (small caches) > - 16 bit SDRAM with mch_opb_sdram controller (without OPB actually) > - CPU connected to RAM through the MCH/XCL > - Ethernet LAN9117 MAC+PHY, with DMA to SDRAM via MCH/XCL > - IO peripheral, with DMA to SDRAM via MCH/XCL > - And lots of IOs (well not so many on PQ208 but final version will > have a larger FPGA). > > Here is what it does : > > - Receives data from PC over ethernet in UDP packets > - Buffer in SDRAM > - Output data in user's format of choice on the pins > - Read data from pins > - Buffer > - Send back to PC in UDP packets > > A simple protocol (not finished) will handle UDP retransmissions etc > a-la-TCP but with very low latency. > > Primary purpose is to transfer multichannel audio (up to about 8-9 > megabytes/s) but also digital scope (sample, buffer, send to PC) and > other data acquisition applications. > It will also need to do some DSP work on the audio (resampling, > dithering, and some complicated filtering, etc) and possibly DSP on the > acquired signals in a DAQ scenario. > > Now. Three problems. > > Everything is good with Xilinx except the DSP part, I guess the > logic would fit in a Spartan-E3 1200 with lots of room to spare except I > might be short on multipliers. Now that would be a problem to realize > that once the final board is made ! > > So I thought about Spartan-3A DSP but it has a packaging problem : > 0.8mm BGA ! No way. 1mm is fine but not 0.8mm. > > Second problem, this SDRAM is really crummy and so is mch_opb_sdram. > Granted, I get 90 MB/s from a 16 bit SDRAM running at 50 MHz which is > good. But it runs at 50 MHz !!! I should have put some DDR. > So the second requirement is an easy interface to a 16 bit DDR chip > with a FREE core that supports some good fast DMA like the mch_opb does. > I really like this way of accessing memory, the CPU doesn't even have to > touch it, my data IO core self-serves from memory, I like that. Ethernet > is slow (20 MB/s) but as I said I want to use it also for some data > acquisition which means writing lots of data very fast to the SDRAM, > since the sample rate of the converters will depend on the memory > bandwidth ! > > Third problem, most of my IO is 3.3V but I would like to use LVDS > for some signals. There are only 4 IO banks... > > Cyclone III (like EP3C40) on the other hand is cheap, has looots of > DSP power, the FPGA itself is faster than the Spartan 3, and it has 8 > banks which means I can dedicate 1/8 of the pins to LVDS and still have > enough for my 3.3V IO. > In other words it looks nice but I don't know anything about Altera. > I loaded up the free tools and played with them a bit without much > success... > > NIOS vs Microblaze ? I don't care, CPU utilization is far from 100% > anyway, so as long as it runs and has JTAG debug I'm happy. > I would like to avoid having to purchase cores, also. EDK which I > got on CD with a dev kit comes with a nice assortment of memory > controllers... I'm having problems decrypting the Altera licensing > stuff, like what is free, and what is not... > > Also this board will be used as part of an open source project. > We'll make a board fab run and sell them so people can hack them. > I would really prefer if those guys could use free (as in beer) > software and EDK is a problem there. But, so is the small collection of > free Altera cores... > > So, from my project description above, what could I do ?... > I am not an expert on Altera licensing, but as far as I can tell you use Quartus web edition and open core evaluation during development. This means you can use the DDR core (the sdram core is always free from Altera, and runs a lot more than 50 MHz, as is their dma core) and the NIOS core while connected to Quartus with by jtag. For stand-alone use, you have to buy a NIOS license and a DDR core license (in practice, you buy a licence for the full version of Q, and get the DDR core license along with it, as well as other cores - the FIR and FFT cores might be of interest). When you buy these, you get a year's worth of upgrades and support, and a perpetual license for the cores. Of course, it might work out cheaper (depending on your volumes, and development times and costs) just to use two SDRAM chips and a faster clock, saving you the need to buy Q. Similarly, you might find a different cpu core such as Lattice's free core, or something from opencores, will do the same job.Article: 132669
On Jun 5, 8:38 am, backhus <n...@nirgends.xyz> wrote: > Zorjak schrieb: > > > On Jun 4, 7:46 am, backhus <n...@nirgends.xyz> wrote: > >> Hi Zoran, > > Thank you very much for the help. > > > Yes you were right. My code wasn't good. The stupid mistake in code. I > > can't believe what I've wrote. But you must admit that warring that I > > was getting from ISE were totally unasociative. That confused me > > totally. :):) > > > Thank you one more time for all your help > > Zoran > > Hi Zoran, > when there's a problem with code semantic, warnings are just indirect > hints. Just before the sections where the warnings are generated you can > read this: > > ========================================================================= > * HDL Analysis * > ========================================================================= > Analyzing generic Entity <counter> in library <work> (Architecture > <Behavioral>). > width = 8 > INFO:Xst:2679 - Register <Q_internal> in unit <counter> has a constant > value of 00000000 during circuit operation. The register is replaced by > logic. > Entity <counter> analyzed. Unit <counter> generated. > > And the info tells you, that there is no counter anymore since the > counter register has been replaced by a constant value. > And at that point all alarms should ring that something went terribly > wrong. (Unless you know what you did, and did it for a purpose.) > > So, even when you get no errors and warnings at all, always have a look > at the infos and other messages in the synthesis report. > > Besides, a simulation should have shown you that your counter isn't > working anyway. > > Have a nice synthesis > Eilert Thanks for those tips Eliert. I've do sinthesis and impelmentation together and I knew that my counter isn't implemetned because nothing was ocupied. THe thing is that I started with Xilinx a while ago and i have just a little experience with Quartus form college. There if something like this happenes quartus would give me the warning that my Q has constant value. Somethng like this info you said me to read but there it would be warning. I think that this would be better but important is that I solve this problem and that I've learned something new. I'll get used on xilinx soon, I hope:) Thanks one more time for your help ZoranArticle: 132670
Hai, I am pretty clear about cutoff and sampling frequency of FIR filter. Wat r all the FIR filter constraints to be considered to set FPGA clock frequency before targetting to FPGA device? I guess i should consider maximum number of taps and maximum sampling frequency used by the FIR filter...am i correct? can i implement a FIR filter of 256-taps(all the taps clocked synchronously),1Ghz cutoff frequency,2.5GS/s with a input FPGA clock frequency of 250Mhz? pls clarify this. regards, fazaArticle: 132671
On Jun 4, 10:18 pm, PFC <li...@peufeu.com> wrote: > >> Ah, and yeah, you'll need somse sort of CPU to go through that > >> initialization routine. > > > Depending on the definition of CPU. It could presumably be done > > by a state machine which may or may not follow one's definition > > of CPU. > > > -- glen > > Actually I use Microblaze, but I was thinking if he doesn't need a CPU he > could use PicoBlaze, then I remembered he uses a chip with a PPC core... Does anybody out here know where to find a ethernet MAC implementation for Picoblaze? It would make a very lightweight eth. implementation, which would suit my Spartan3E starter kit board perfectly. Microblaze is a bit too resource-hungry for my project. BartArticle: 132672
> > Symon wrote: > > >http://www.edn.com/article/CA6566989.html > > > Saw that. > > > Wonder if Austin will be along shortly, to claim Xilinx is > > (once again) leading the pack... ;) > > > -jg > > C'mon, be nice. This is not funny. It's the very first lay-off in the > 25-year history of Xilinx. Profits up by 7% then staff down by 7%. Presumably will be followed by large executive level bonuses. How can your company still be advertising jobs?Article: 132673
I think the the problem lays on the TDO signal. The rising edge on TDO is abnormally slow and flat on the first pulse, here: http://img239.imageshack.us/my.php?image=jtagtdoprommh2.png . The TDO signal is connected directly from PROM to a Xilinx JTAG USB cable. Does somebody know why the signal is so flat? Thanks, JJArticle: 132674
On Thu, 5 Jun 2008 01:21:39 -0700 (PDT), fazulu deen wrote: >can i implement a FIR filter of 256-taps(all the taps clocked >synchronously),1Ghz cutoff frequency,2.5GS/s Can you spell "surface acoustic wave"? > with a input FPGA clock frequency of 250Mhz? So you plan to clock your FPGA at 1/10th the filter's sampling frequency. That means you must process ten samples on each clock cycle. Do you know how to do that? Since you plan for a cutoff frequency of 1GHz, you can't undersample the filter's output. So you not only need to process ten input samples on every clock, but also you must generate ten output samples on every clock. That would lead to "interesting" I/O requirements. There will also be "interesting" internal resource requirements, unless your filter coefficients are very sparse. Were the figures you gave us (Fclk=250MHz, Fs=2.5GHz, Fc=1GHz) intended to reflect a real problem? Or were they simply random numbers? -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.
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