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News: "As it seeks a buyer, MathStar said it plans to discontinue its field programmable object array (FPOA) chip development and its board-level systems development businesses." Did they ever get to fully working Silicon ? Anyone get to try ES silicon ? -jgArticle: 132451
Florian wrote:
> I have a very basic question. Xilinx permits me to initialize Block RAM
> with an external data file. The thing I am just wondering is, how do I
> download this file on the FPGA?
If the data is fixed,
it is easy to declare a vector array
in vhdl to infer a block rom.
No write interface required.
-- Mike Treseler
Article: 132452http://www.bizjournals.com/twincities/stories/2008/05/26/daily7.html http://www.startribune.com/business/19286524.html?location_refer=Business http://blog.oregonlive.com/business/2008/05/mathstar_calls_it_quits.html http://www.earthtimes.org/articles/show/mathstar-inc-to-discontinue-chip-development-and-systems-level-businesses,409002.shtml That is a surprise (to me). AustinArticle: 132453
>From their stock call on May 11, 2008: "First and foremost, the established lead-based programmable logic companies, like Altera and Xilinx, have had nearly 20 years to mature the software tools used by the customers to program their FPGA. MathStar has quality programming tools, but we haven’t yet developed the level of abstraction and automation that FPGA tools have attained. This is by far the biggest issue affecting MathStar’s ability to scale the business. Customers have struggled to become productive with the FPOA design tools, although our internal teams of application engineers and certified design engineers have become proficient with developing even the most complex video encoder designs using FPOAs." Seems it was tougher than it looked! The days when "if you build it, they will come" are long over. When the manufacturer has to do (all) the work to get the product into customer's sockets, that is a really, really, bad sign.... "scale the business" I suppose is how you say "make money" in this politically correct world? It appears they had silicon (90nm) and they had customers. They also had a lot of stock-holders now holding pretty worthless stock... AustinArticle: 132454
On May 27, 12:42=A0am, "MikeWhy" <boat042-nos...@yahoo.com> wrote: > "bish" <bishes...@gmail.com> wrote in message > > news:5df586c0-0126-48cc-9ff1-ee382f505221@u6g2000prc.googlegroups.com... > > > We have just bought a new Spartan 3a 1800a dsp board of Xilinx. We > > needed i/o pins to control motors and use various sensors and camera. > > The board contains EXP expansion slots, ( somewhere I found it is > > called QTE connector?). > > > We are confused as how to easily connect our sensors like optical > > encoder, camera and output for our motor drivers using these EXP > > slots? > > Somewhere we found that we need to use QSE connector but we are not > > clear about it. We need a low cost solution !!!!! Can we find the > > connectors to match with EXP slot at one end and have simple wires at > > the other end?? > > The S3ADSP starter kit board comes with Samtec QTE connectors. The > corresponding connectors are series their QSE. The user guide documents th= e > specific type. Samtec was nice enough to send a couple of the required > connectors as samples. These are SMT components; you'll have to build a > board to bring out the required signals. They also sell QSE terminated > cables, although I doubt these are cheap. They are shielded differential > pairs. You might look at daughterboards sold for the S3ADSP3400 kits. I > don't have experience with the 3400 board. Its accessories might or might > not fit the QTE connectors on the 1800 board. The Avnet EXP Proto module brings the I/Os out to headers. www.em.avnet.com/exp-prototypeArticle: 132455
austin wrote: > From their stock call on May 11, 2008: > > "First and foremost, the established lead-based programmable logic > companies, like Altera and Xilinx, have had nearly 20 years to mature > the software tools used by the customers to program their FPGA. MathStar > has quality programming tools, but we haven’t yet developed the level of > abstraction and automation that FPGA tools have attained. This is by far > the biggest issue affecting MathStar’s ability to scale the business. > > Customers have struggled to become productive with the FPOA design > tools, although our internal teams of application engineers and > certified design engineers have become proficient with developing even > the most complex video encoder designs using FPOAs." > > Seems it was tougher than it looked! > > The days when "if you build it, they will come" are long over. > > When the manufacturer has to do (all) the work to get the product into > customer's sockets, that is a really, really, bad sign.... > > "scale the business" I suppose is how you say "make money" in this > politically correct world? > > It appears they had silicon (90nm) and they had customers. They also > had a lot of stock-holders now holding pretty worthless stock... If they really DID have working silicon, and customers, then you don't pull the plug, Normally what happens then, is the second-iteration, (next generation) just fails to materialise. However, if you find your Silicon 'needs another pass', or the customer you thought you had, was Lassoed by the competition 'buying the socket'... - or the customer did the effort/return calculation, and saw the road map of other vendors, and made the decision themselves. [ aka Apple and Freescale/intel?] -jgArticle: 132456
sijo2000@googlemail.com wrote: (snip) > What is possible is to change the data in the configuration bit stream > so that when you configure the FPGA the RAM is initialised with the > data you require, without having to iterate through synthesis and PAR. > It's been a while since I did anything like this but I seem to > remember there is a tool included in the Picoblaze package from Xilinx > called Data2Mem that did exactly this to include the code for the > processor in the bit stream. Take a look at the flow this tool > required and you should be able to adapt it to your needs. Xylinx used to publish the information on where the LUT bits were stored in the configuration file, for the case of LUT based RAMs. (Among other reasons, so that comparisons with read-back data could be made.) Without that, you can compile different RAM initialization data and compare the bit streams. -- glenArticle: 132457
Jim Granville wrote:
> News: "As it seeks a buyer, MathStar said it plans to discontinue its
> field programmable object array (FPOA) chip development and its
> board-level systems development businesses."
>
> Did they ever get to fully working Silicon ?
Don't know, but here's the problem.
The mathstar faq says:
"The FPOA does not support synthesis
design flows at this time.
The design flow for the FPOA requires
the designer to map the algorithm to
FPOA objects, which may not be a familiar process."
May not be?
Sounds like the packet processor "threads" story all over again.
-- Mike Treseler
Article: 132458Does anyone have comparison table about Xilinx ISE WebPack 10.1i vs ISE Foundation 10.1i ? Because I was confused by their license and available features. Thank you.Article: 132459
On 2008-05-28, Pablo H <pablo.huerta@gmail.com> wrote: > This conferences are specially oriented to reconfigurable computing, > including FPGA technology: > > In America; > http://www.reconfig.org > http://www.splconf.org/spl09/ > > In Europe: > http://fpl.org/ > http://dcis.org/ > > In Spain: > http://www.jcraconf.org/ A nice list is also available at http://www.ece.ubc.ca/~stevew/conf.html /AndreasArticle: 132460
"Zorjak" <Zorjak@gmail.com> wrote in message news:275e239e-3045-4368-b0d1-8526ba3756e8@26g2000hsk.googlegroups.com... > > My core folder is located in the my ise > project directory. All I I included my vhd core file in to my ise > project. After you told me this I have copied all files from core > directory to my ise directory and i tried to start compilation again. > My result is the same. I am getting the same error. Two notes: 1. The help article you found about EDK pcores is totally irrelevant. Forget about EDK and MPD files. You are working with basic ISE and coregen and they have nothing to do with EDK. 2. The vhdl wrapper file generated by coregen is for simulation, not for synthesis. You don't need to add any vhdl files to your project to be able to use the core. What you need to add is the ngc file, although I believe it should find it even if you don't add it explicitly. Also, ISE GUI expects you to do this all differently. After you create a new project you can right click in the sources pane and choose new source, then choose IP in the new window which will open. This will start coregen and will let you generate your core. It will also attach an xco file to the project, which is a coregen config file for the specific core. Since you have already run the coregen you can add the existing xco file to the project. /MikhailArticle: 132461
On 27 Mai, 07:42, marts...@gmail.com wrote: > > For most FPGAs there is a global value for Powerup content that is > > valid before you use a reset. [..] > > Thanks for your input. But what I was trying to figure out is > that...If I am not using the reset, or not assign any values to > signal, what happens in that case? I do know how to fix it but I was > just curious to find out, why was this working for sometime but now > doesn't work with a different part (same mfg)? The normal synthesis result for the if clause would be y = x (wire). If x is never initialised, the wire could be removed and a FF driven by y won't be driven, so it could be removed, too. At any stage you will use the signal in a way, the synthesis stops removing and you might end with a FF without initialisation. You should tell more about, what synthesis did with your code. The synthesis resulf for the code above may be not deterministic for different synthesis runs. But the only chance for the code above to have one programming file giving different results on different devices is IMHO a latch or FF without initialisation used in a technology that provides no defined state at power-up. You shoudl ask your vendor, wheter your technology provides defined states at power-up. bye ThomasArticle: 132462
On May 28, 7:35 am, "MM" <mb...@yahoo.com> wrote: > "Zorjak" <Zor...@gmail.com> wrote in message > > news:275e239e-3045-4368-b0d1-8526ba3756e8@26g2000hsk.googlegroups.com... > > > > > My core folder is located in the my ise > > project directory. All I I included my vhd core file in to my ise > > project. After you told me this I have copied all files from core > > directory to my ise directory and i tried to start compilation again. > > My result is the same. I am getting the same error. > > Two notes: > 1. The help article you found about EDK pcores is totally irrelevant. Forget > about EDK and MPD files. You are working with basic ISE and coregen and they > have nothing to do with EDK. > > 2. The vhdl wrapper file generated by coregen is for simulation, not for > synthesis. You don't need to add any vhdl files to your project to be able > to use the core. What you need to add is the ngc file, although I believe it > should find it even if you don't add it explicitly. Also, ISE GUI expects > you to do this all differently. After you create a new project you can right > click in the sources pane and choose new source, then choose IP in the new > window which will open. This will start coregen and will let you generate > your core. It will also attach an xco file to the project, which is a > coregen config file for the specific core. Since you have already run the > coregen you can add the existing xco file to the project. > > /Mikhail Thanks Mikkhail I've included xco file in to my ise project and I haven't got any errors. My synthesis and implementation have passed. You helped me very much. Thank you a lot, Mikkhail ZoranArticle: 132463
This conferences are specially oriented to reconfigurable computing, including FPGA technology: In America; http://www.reconfig.org http://www.splconf.org/spl09/ In Europe: http://fpl.org/ http://dcis.org/ In Spain: http://www.jcraconf.org/ Can I ask you in which university are you working for the Ph.D degree?Article: 132464
Hi, I have the problem that I can't communicate with my Xilinx XCF04S PROM through JTAG. The circuit setup is a "3.3V Master-Serial Configuration with 3.3V and JTAG with Platform Flash Prom" as here: http://www.xilinx.com/support/answers/20477.htm. To reduce the sources of error, I disconnected the JTAG input signals TMS, TCK, TDO to the FPGA, and connected the TDO directly from the PROM to the connector, therefore bypassing the FPGA. According to the PROM datasheet, the only pins that matters additionaly to the JTAG signals is the #CE pin (this pin is always low) and power pins. I checked with an oscillator the JTAG signals: TCK http://img165.imageshack.us/my.php?image=jtagtcktes1hl8.png TDI http://img81.imageshack.us/my.php?image=jtagtdites1db4.png TDO http://img341.imageshack.us/my.php?image=jtagtdotes1fi0.png TMS http://img341.imageshack.us/my.php?image=jtagtmstes1io0.png All JTAG signals toggel (i measured on the IC and connector to exclude any soldering problems). I noticed that TDI and TCK look very similar, however there is not short-cut between them When I do an ID Check, i get this: INFO:iMPACT:1578 - '1': Device IDCODE : 00001111111111111111111111111111 INFO:iMPACT:1579 - '1': Expected IDCODE: 00000101000001000110000010010011 I would like to have your opinions what you think the error is? Thank you, JidanArticle: 132465
Hi , Everything works fine when i implement the unencrypted design , so what's the problem with the crypted one ?!Article: 132466
Sorry, Guys. We're not quite done yet with the quadrature encoder. I tried
to rewrite it as a synchronous process. The behavioral sim shows it working
as intended. The post-route sim and onboard test don't work. 'debouncing'
never changes state in the sim. The leds don't sequence when I twist the
magic knob.
Can someone please look at the following and comment? I suspect it may be a
mistiming on setting a_prev and b_prev. a_prev and b_prev are the sampled
states of 'a' and 'b' during the previous clock. The intended function is
that we test for a change in 'a'. If it's an active-edge change, it updates
the count according the direction indicated by 'b'. The other edge of 'a'
simply debounces to skip the noise. The next change in 'b' cancels the
debounce.
In general, is it always this difficult and fraught with peril? I write
>2000 lines/month in C++ with only minor misspelling mishaps. These 50 lines
have caused me more gray hairs than many whole systems.
Also, is there a way to tell XST to not treat reset as a clock? I haven't
fully read up on configuration, having spent way too much time on this
little time waster.
Last, .... is this really worth pursuing? I've been programming for 25
years, and know that the greatest leassons come after the greatest pain. But
there's also good pain, and just senseless injury. Is this not a suitable
first Zen parable to contemplate? I'm goaded forward by the belief that
there's a good lesson on synchronous systems lurking as the punchline.
(If it matters, the target is a Spartan-3A DSP starter kit board. ISE 10.1
tools.)
Thanks.
Mike.
=====================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
------------------
entity q_decode is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
leds : out std_logic_vector(7 downto 0));
end q_decode;
architecture Behavioral of q_decode is
signal debouncing : STD_LOGIC := '0';
signal a_prev, b_prev : STD_LOGIC := '0';
signal a_start : STD_LOGIC := '0';
signal count : std_logic_vector(3 downto 0) := "1001";
begin
process (clk, rst, a, b)
begin
if (rst = '1') then
a_start <= a;
a_prev <= a;
b_prev <= a;
debouncing <= '0';
count <= "0101";
elsif (clk'event and clk = '1') then
if (debouncing = '0') then
if (a /= a_prev) then
debouncing <= '1';
if (a /= a_start) then -- active edge of 'a'
if (b = '1') then
count <= count + 1;
else
count <= count - 1;
end if;
end if;
end if;
else -- debouncing = '1'
if (b /= b_prev) then -- b changed sense in this clock cycle.
debouncing <= '0';
end if;
end if;
-- save state of encoder pins for next clock cycle.
a_prev <= a;
b_prev <= b;
end if;
end process;
with count select
leds(7 downto 0) <=
"00000001" when "0000",
"00000011" when "0001",
"00000010" when "0010",
"00000110" when "0011",
"00000100" when "0100",
"00001100" when "0101",
"00001000" when "0110",
"00011000" when "0111",
"00010000" when "1000",
"00110000" when "1001",
"00100000" when "1010",
"01000000" when "1100",
"11000000" when "1101",
"10000000" when "1110",
"10000001" when others;
end Behavioral;
Article: 132467hi, does anyone know how to solve this error when selecting 'generate simulation hdl files' in xps (xilinx edk 9.1): ------------------------------------------------------------------ ... Analyzing file /pl/hardware/user-platforms/MySystemV5/fs-boot/executable.elf... INFO:MDT - BRAM lmb_bram will be initialized with ELF of processor microblaze_0 Running Data2Mem with the following command: data2mem -bm system_sim.bmm -bd /pl/hardware/user-platforms/MySystemV5/fs-boot/executable.elf tag microblaze_0 -u -o u tmpucf.ucf ERROR:MDT - Ucf2Vhdl Conversion Generated Errors. ERROR:MDT - Error creating memory initialization files make: *** [simulation/behavioral/system.do] Fehler 1 Done! ------------------------------------------------------------------- would be great if you could help me with this issue. i've googled and searched in the xilinx answer database but haven't found anything. i have successfully compiled the simulation libraries with xps and modelsim 6.1e. i'm using petalinux 0.30rc1 thanks sebastianArticle: 132468
On May 28, 6:50=A0am, "MikeWhy" <boat042-nos...@yahoo.com> wrote: > Sorry, Guys. We're not quite done yet with the quadrature encoder. I tried= > to rewrite it as a synchronous process. The behavioral sim shows it workin= g > as intended. The post-route sim and onboard test don't work. 'debouncing' > never changes state in the sim. The leds don't sequence when I twist the > magic knob. > This is always a symptom of a timing problem. In your particular case I suspect the timing of 'a' and 'b' relative to clk is not meeting the setup/hold time requirements of the device (from your report file). The signals 'a' and 'b' should be brought into only one flop, the output of that flop should be fed into a second flop, the output of that second flop can then be reliably used wherever you currently have 'a' and 'b'. > > In general, is it always this difficult and fraught with peril? I write > =A0>2000 lines/month in C++ with only minor misspelling mishaps. These 50 = lines > have caused me more gray hairs than many whole systems. > Hardware design (even if written in a software like language such as VHDL or Verilog) is not the same as software. You can be well skilled in the one discipline and at the same time be unskilled in the other. > Also, is there a way to tell XST to not treat reset as a clock? I haven't > fully read up on configuration, having spent way too much time on this > little time waster. What makes you think that it is using reset as a clock? > > Last, .... is this really worth pursuing? I've been programming for 25 > years, and know that the greatest leassons come after the greatest pain. B= ut > there's also good pain, and just senseless injury. Is this not a suitable > first Zen parable to contemplate? I'm goaded forward by the belief that > there's a good lesson on synchronous systems lurking as the punchline. > The punchline might be static timing analysis. Signals don't just 'happen' when you want them to, you need to guarantee by design that they arrive at the proper time relative to the clock. Kevin JenningsArticle: 132469
Main difference is devices supported. Details of wahat Webpack supports http://www.xilinx.com/ise/products/webpack_config.htm. John Adair Enterpoint Ltd. On May 28, 2:09=A0am, Eka <aan.wo...@gmail.com> wrote: > Does anyone have comparison table about Xilinx ISE WebPack 10.1i vs > ISE Foundation 10.1i ? Because I was confused by their license and > available features. Thank you.Article: 132470
MikeWhy wrote: > Sorry, Guys. We're not quite done yet with the quadrature encoder. I > tried to rewrite it as a synchronous process. The behavioral sim shows > it working as intended. The post-route sim and onboard test don't work. > 'debouncing' never changes state in the sim. The leds don't sequence > when I twist the magic knob. I like Ray's process here: http://groups.google.com/groups/search?q=quadrature+resolver+single+process I've added an entity here: http://mysite.verizon.net/miketreseler/quad_encode.vhd RTL view looks good, but untested. > In general, is it always this difficult and fraught with peril? I write >>2000 lines/month in C++ with only minor misspelling mishaps. These 50 > lines have caused me more gray hairs than many whole systems. How long did your first significant C++ project take? -- Mike TreselerArticle: 132471
Hi, I'm trying to build a system for a XC2V6000 FPGA. The problem I have is that I have to implement a PLB. But the PLB shipped with the EDK 10.1 is the PLB_v46 which doesn't support the virtex II, only V2Pro and V4. At the datasheets on the xilinx website I found that the PLB_v34 should support the V2 (see this link: http://www.xilinx.com/products/ipcenter/plb_v34.htm ). But there exist two versions of the datasheet. One on the xilinx website and one at the pcore directory. I got the pcore from the EDK 8.2 which includes the PLB_v34 in version 1.01a. The datasheet says that this version only supports V2Pro and V4. I just took that core and copied it to the pcore directory of my EDK 10.1 project and added it to the system. I ignored the warnings and started the build process but this was aborted with the reason that the Virtex2 isn't supported. Does that mean that the datasheet on the xilinx website is wrong? Did I something wrong? Has anyone tried to implement a PLB on a Virtex II system? Thanks.Article: 132472
Instead of posting code and asking us to look at it, why don't you debug the simulation??? That is what simulations are for. If you said it worked in pre and post layout simulation, but failed on real hardware, then it would be a sticky problem that could justify asking help. But if it is failing in simulation, you can dig in and see exactly why it is failing. I am very surprised that this is working in pre-layout sim and failing in post. That is usually a timing problem and I can't imagine that you have any timing problems. Although the synchronization issue that KJ mentioned is very valid. To simplify reading your code you might want to break out the different functions. Debounce is normally something done separate from the state machine you are implementing. So put it in a separate process and use a separate signal to drive the decoder process. Then you have a nice clean signal you can look at to see if the debounce process is working correctly. I am also not too sure of your decoder algorithm. It is a bit hard to read because of the number of indents and the formatting in this forum, but it looks like nothing is done with b transitions unless they are preceded by an a transition. I don't think that is an optimal approach for a decoder, but maybe this is because you want to handle higher speeds. But if you are getting transitions faster than the bounce settles, I don't think the encoder can be decoded. So none of this is clear to me. Rick On May 28, 6:50 am, "MikeWhy" <boat042-nos...@yahoo.com> wrote: > Sorry, Guys. We're not quite done yet with the quadrature encoder. I tried > to rewrite it as a synchronous process. The behavioral sim shows it working > as intended. The post-route sim and onboard test don't work. 'debouncing' > never changes state in the sim. The leds don't sequence when I twist the > magic knob. > > Can someone please look at the following and comment? I suspect it may be a > mistiming on setting a_prev and b_prev. a_prev and b_prev are the sampled > states of 'a' and 'b' during the previous clock. The intended function is > that we test for a change in 'a'. If it's an active-edge change, it updates > the count according the direction indicated by 'b'. The other edge of 'a' > simply debounces to skip the noise. The next change in 'b' cancels the > debounce. > > In general, is it always this difficult and fraught with peril? I write > >2000 lines/month in C++ with only minor misspelling mishaps. These 50 lines > have caused me more gray hairs than many whole systems. > > Also, is there a way to tell XST to not treat reset as a clock? I haven't > fully read up on configuration, having spent way too much time on this > little time waster. > > Last, .... is this really worth pursuing? I've been programming for 25 > years, and know that the greatest leassons come after the greatest pain. But > there's also good pain, and just senseless injury. Is this not a suitable > first Zen parable to contemplate? I'm goaded forward by the belief that > there's a good lesson on synchronous systems lurking as the punchline. > > (If it matters, the target is a Spartan-3A DSP starter kit board. ISE 10.1 > tools.) > > Thanks. > Mike. > > ===================================================== > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > ------------------ > entity q_decode is > Port ( a : in STD_LOGIC; > b : in STD_LOGIC; > clk : in STD_LOGIC; > rst : in STD_LOGIC; > leds : out std_logic_vector(7 downto 0)); > end q_decode; > > architecture Behavioral of q_decode is > signal debouncing : STD_LOGIC := '0'; > signal a_prev, b_prev : STD_LOGIC := '0'; > signal a_start : STD_LOGIC := '0'; > signal count : std_logic_vector(3 downto 0) := "1001"; > begin > process (clk, rst, a, b) > begin > if (rst = '1') then > a_start <= a; > a_prev <= a; > b_prev <= a; > debouncing <= '0'; > count <= "0101"; > elsif (clk'event and clk = '1') then > if (debouncing = '0') then > if (a /= a_prev) then > debouncing <= '1'; > if (a /= a_start) then -- active edge of 'a' > if (b = '1') then > count <= count + 1; > else > count <= count - 1; > end if; > end if; > end if; > else -- debouncing = '1' > if (b /= b_prev) then -- b changed sense in this clock cycle. > debouncing <= '0'; > end if; > end if; > -- save state of encoder pins for next clock cycle. > a_prev <= a; > b_prev <= b; > end if; > end process; > > with count select > leds(7 downto 0) <= > "00000001" when "0000", > "00000011" when "0001", > "00000010" when "0010", > "00000110" when "0011", > "00000100" when "0100", > "00001100" when "0101", > "00001000" when "0110", > "00011000" when "0111", > "00010000" when "1000", > "00110000" when "1001", > "00100000" when "1010", > "01000000" when "1100", > "11000000" when "1101", > "10000000" when "1110", > "10000001" when others; > > end Behavioral;Article: 132473
On May 27, 7:11=A0pm, morphiend <morphi...@gmail.com> wrote: > > EDK stores it's settings for the flow (or atleast used to in the 9.x, > I haven't tried 10.x yet) in the /etc directory. For me it's a file > called "fast_runtime.opt". In that file are all the command line > switches, separated by a new line, for each tool that is run in the > EDK flow. I don't use the EDK gui much, so I don't know if its > specifically possible or not to configure it from there. On the > flipside, ISE does support native EDK project building. You just > create a new ISE project and import the EDK xmp file as a source file. > That way you would have the entire ISE flow if you so wished. > > -- Mike Thanks. Found the options and got my project running. Also added some constraints that helped me complete the implementation with the Xflow (normal) script itself :) Raghu.Article: 132474
KJ wrote: > On May 28, 6:50 am, "MikeWhy" <boat042-nos...@yahoo.com> wrote: >> Sorry, Guys. We're not quite done yet with the quadrature encoder. I tried >> to rewrite it as a synchronous process. The behavioral sim shows it working >> as intended. The post-route sim and onboard test don't work. 'debouncing' >> never changes state in the sim. The leds don't sequence when I twist the >> magic knob. >> > > This is always a symptom of a timing problem. In your particular case > I suspect the timing of 'a' and 'b' relative to clk is not meeting the > setup/hold time requirements of the device (from your report file). > The signals 'a' and 'b' should be brought into only one flop, the > output of that flop should be fed into a second flop, the output of > that second flop can then be reliably used wherever you currently have > 'a' and 'b'. This very well could be a timing issue but another possible cause of this could be the writing of simulatable code but not synthesizable code. Looking at the code, I see the signals a and b in the sensitivity list of the process which could cause the else statement to get evaluated asynchronously in simulation however for synthesis, the sensitivity list is likely ignored (generally with a warning) and thus processed differently. I suggest removing the a and b signals from the sensitivity list and see if the behavioral simulation still works. My guess is that may reveal your issue however if that does not, then I do suggest looking more closely at the synthesis logs as well as timing analysis to ensure it is not another synthesis mis-match issue or timing issue. >> In general, is it always this difficult and fraught with peril? I write >> >2000 lines/month in C++ with only minor misspelling mishaps. These 50 lines >> have caused me more gray hairs than many whole systems. >> > > Hardware design (even if written in a software like language such as > VHDL or Verilog) is not the same as software. You can be well skilled > in the one discipline and at the same time be unskilled in the other. It is all what you are used to. I can not write C++ worth a lick so it would likely take me a long time to write a program using it however I feel I am very proficient with VHDL and Verilog. >> Also, is there a way to tell XST to not treat reset as a clock? I haven't >> fully read up on configuration, having spent way too much time on this >> little time waster. > > What makes you think that it is using reset as a clock? I imagine you are referring to XST using a global buffer for the reset signal. In general this should not cause any issues and many times can be the right thing to do but if you want to go to prevent that behavior, tell XST you want an IBUF on the reset signal by adding the following attribute: attribute BUFFER_TYPE : string; attribute BUFFER_TYPE of rst: signal is "IBUF"; This will force it to use a regular I/O instead of a global buffer. Hope this helps and do not get too discouraged. If you are just learning, I could also suggest you try Verilog over VHDL. I am not trying to start the holy wars of languages but many do feel it is less of a leap from C to Verilog than VHDL. Again, I am not trying to start a language debate so please leave do not let my statement start one. -- Brian >> Last, .... is this really worth pursuing? I've been programming for 25 >> years, and know that the greatest leassons come after the greatest pain. But >> there's also good pain, and just senseless injury. Is this not a suitable >> first Zen parable to contemplate? I'm goaded forward by the belief that >> there's a good lesson on synchronous systems lurking as the punchline. >> > > The punchline might be static timing analysis. Signals don't just > 'happen' when you want them to, you need to guarantee by design that > they arrive at the proper time relative to the clock. > > Kevin Jennings
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