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austin wrote: > There is always a clock present (FPGA design can only be done in a > synchronous system, I've successfully implemented several entirely asynchronous designs in Spartan-3 family parts. Only to see if it could be done, though; I wouldn't try to put one into production.Article: 132326
Eric Smith wrote: > austin wrote: >> There is always a clock present (FPGA design can only be done in a >> synchronous system, > > I've successfully implemented several entirely asynchronous designs in > Spartan-3 family parts. Only to see if it could be done, though; I wouldn't > try to put one into production. Why not use it in production? Is there any technical reason why not to use asynchronous designs? E.g. if I want to use Muller C-gates for an aynchronous design with FPGAs? http://en.wikipedia.org/wiki/C-element -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 132327
I wrote: > I've successfully implemented several entirely asynchronous designs in > Spartan-3 family parts. Only to see if it could be done, though; I wouldn't > try to put one into production. Frank Buss wrote: > Why not use it in production? Is there any technical reason why not to use > asynchronous designs? As far as I can tell, there isn't anything about the FPGA hardware that prevents it. The development tools, however, are all based on the idea of synchronous design, and will fight you every step of the way if you try to use any asynchronous feedback. You can beat the synthesis and P&R into submission, though they complain, but the static timing analyzer and the power estimator are particularly unsuited to async designs. You also might not be able to get any support for asynchronous design through official channels. (I'm only guessing, I haven't actually tried.) EricArticle: 132328
"Jon Elson" <elson@wustl.edu> wrote in message news:4834722D.7020006@wustl.edu... > > > Jim Granville wrote: >> >> Even with input registering, you should cover ALL states, >> (including the 'illegal' ones) in your state code. >> > That's pretty easy to do with binary coded states, but with one-hot, > and enumerating the type, how do you even SPECIFY the illegal states, > as those, by definition, would be the ones with two or more bits "hot"? > If you choose to use enumerated types in your source code you don't have a way to specify 'illegal' states. But that misses the point, which is that you should have a design that can not get into an 'illegal' state. In your case you got there by violating setup time by bringing your asynchronous input signal into more than one flop (i.e. the multiple flops that make up your state machine). > >> Can you clarify 'too frequently' ? >> With a 25ns clock, a couple of IPs and 5 choices, lets >> take a nice round 100ns IP sample rate. (10MHz) >> > The external signals, all two of them are from a mechanical system, > and change slowly. > The frequency of the signals from your mechanical system are irrelevant unless they are 0 Hz. That input signal will not be changing at any particular time relative to the clock of your state machine so you are guaranteed to have instances that do not meet the setup time requirements. It doesn't matter how frequently you think those things are changing, you have to meet setup/hold time requirements on each and every clock cycle. Kevin JenningsArticle: 132329
On 2008-05-22, fazulu deen <fazulu.vlsi@gmail.com> wrote: > So u mean to say both for loop & state machine will take same number > of clock cycles and resource utilization?? Depends on how you write it, and as another poster in this thread pointed out, some synthesizers can synthesize a process with multiple event control statements in it. But as I have repeatedly said, the synthesizer will unroll a for-loop. If you write for(i=0; i < 5; i = i + 1) begin a = f[i]+g[i] + a; end the synthesizer will replace it with a = f[0]+g[0] + a; a = f[1]+g[1] + a; // And so on... This should give you enough knowledge to answer your questions yourself. > Wat is the advantage i get interms of number of clocks,resources if i > have more number of states?? This sounds like a typical homework problem... /AndreasArticle: 132330
On May 21, 5:52=A0pm, Andreas Ehliar <ehliar-nos...@isy.liu.se> wrote: > On 2008-05-21, fazulu deen <fazulu.v...@gmail.com> wrote: > > > As per Andreas: =A0it is always advised that FOR loops =A0are not to be > > used in RTL coding > > Just to set the record straight: What I sad was that we recommend our > students in _introductory_ courses to avoid for-loops. The reason is > that we have seen too many cases of students who try to program in > VHDL or Verilog instead of designing hardware in VHDL or Verilog. > We believe that it is probably not a good idea to teach for-loops > before a student has grasped the basic concepts of hardware design > using RTL language. > > As I mentioned in an earlier posting, there is nothing magical about > for loops, the synthesizer will simply unroll the loop. For-loops > (especially in conjunction with generate) can be a great way to > minimize the amount of typing. > > /ANdreas hai, So u mean to say both for loop & state machine will take same number of clock cycles and resource utilization?? Wat is the advantage i get interms of number of clocks,resources if i have more number of states?? regards, fazArticle: 132331
Jon Elson wrote: > > > Jim Granville wrote: > >> That may have more to do with the implicit ELSE handling. >> ie One State engine locks solid, the other will recover >> in a few clocks (which means you may not notice, or have not >> yet noticed the effects!) >> >> Even with input registering, you should cover ALL states, >> (including the 'illegal' ones) in your state code. >> > That's pretty easy to do with binary coded states, but with one-hot, > and enumerating the type, how do you even SPECIFY the illegal states, > as those, by definition, would be the ones with two or more bits "hot"? True, it becomes more a tools issue. Out of interest, how did the resource/speed reports compare, with the two coding schemes ? > > >> Can you clarify 'too frequently' ? >> With a 25ns clock, a couple of IPs and 5 choices, lets >> take a nice round 100ns IP sample rate. (10MHz) >> > The external signals, all two of them are from a mechanical system, > and change slowly. but you should be able to do an aperture calculation, to see if your observed lock-ups, match the prediction (roughly). Do these IPs bounce ? -jgArticle: 132332
Dear Mike > If you have the core unlocked, it should show up as a core in the High- > Speed Communication 'folder' in the cores tree. In other words, there > isn't much you'd have to do to 'import' it into EDK. It should be > their auto-magically.- Hide quoted text - Got that part.... Once the core is in the repository in EDK, do I add it to my project through XPS as a peripheral (using the create/import peripheral option) or do i use the Add/Edit core option? after this, do i just download it to the board? thanks vikramArticle: 132333
On May 21, 2:54=A0pm, wzab <wza...@gmail.com> wrote: > > > How to identify the path generating the problem? > > > I can not run the timing analyzer, because the map fails. > > > -- > > > TIA & regards, > > > Wojtek Zabolotny > > > Hi Wojtek, > > In the ISE GUI (I'm using 8.2 at the moment; I hope your version is > > similar), find the 'Processes' window. Expand the section 'Implement > > Design', then expand 'Map', then 'Generate Post-Map Static Timing'. If y= ou > > double-click 'Analyze Post-Map Static Timing', it'll churn away and > > eventually open the timing analyser. You can then find what path is fail= ing. > > The key insight is to run the timing analyser on the map results, before= you > > enter the P&R phase. > > HTH, Syms. > > The problem is, that I can not 'Generate Post-Map Static Timing', > because the map fails! > -- > Wojtek Here one point is not clear to me. How a timing constraint forces the map to fail.If every thing (in the design) is correct then it passes the map with timing errors.I think there is some problem in the design which is forcing the map to fail.Article: 132334
Brian Drummond wrote: > On Wed, 21 May 2008 02:54:02 -0700 (PDT), wzab <wzab01@gmail.com> wrote: > >>>> How to identify the path generating the problem? >>>> I can not run the timing analyzer, because the map fails. >>>> -- >>>> TIA & regards, >>>> Wojtek Zabolotny >>> double-click 'Analyze Post-Map Static Timing', it'll churn away and >>> eventually open the timing analyser. You can then find what path is failing. >>> The key insight is to run the timing analyser on the map results, before you >>> enter the P&R phase. >>> HTH, Syms. >> The problem is, that I can not 'Generate Post-Map Static Timing', >> because the map fails! > > Relax the timing until it maps, then you can find the slowest paths (at > PAR if necessary). Fix these and retry. Then tighten the timings a bit. > Repeat until done. I've seen a similar issue, but it wasn't related to clock period constraints. The offset in constraint was applied to input pins that had some combinatorial logic before getting latched by a flop. The offset in wasn't too tight by itself, but the extra combinatorial cloud was making it impossible to meet, hence a similar error. Start looking at offset in/out constraints, since it sounds like your clock constraints are relaxed enough. HTH, -P@Article: 132335
"Eric Smith" <eric@brouhaha.com> wrote in message news:m3fxsbnm6g.fsf@donnybrook.brouhaha.com... >I wrote: >> I've successfully implemented several entirely asynchronous designs in >> Spartan-3 family parts. Only to see if it could be done, though; I >> wouldn't >> try to put one into production. > > Frank Buss wrote: >> Why not use it in production? Is there any technical reason why not to >> use >> asynchronous designs? > > As far as I can tell, there isn't anything about the FPGA hardware > that prevents it. The development tools, however, are all based on > the idea of synchronous design, and will fight you every step of the > way if you try to use any asynchronous feedback. You can beat the > synthesis and P&R into submission, though they complain, but the static > timing analyzer and the power estimator are particularly unsuited to async > designs. > > You also might not be able to get any support for asynchronous design > through official channels. (I'm only guessing, I haven't actually > tried.) It put a BUFG on an encoder input and routed it to heck and back first. Aside from that, it almost works. Now I can get on with my life. The final outcome: 6 slices, 6 flipflops, and a GCLK. Thanks all for the help and the discussion. It wasn't immediately clear in my reading why some things are done the way they are. ========================================================================= * Final Report * ========================================================================= Final Results RTL Top Level Output File Name : rot_lights.ngr Top Level Output File Name : rot_lights Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO Design Statistics # IOs : 11 Cell Usage : # BELS : 14 # AND2 : 1 # INV : 1 # LUT3 : 9 # LUT4 : 1 # VCC : 1 # XOR2 : 1 # FlipFlops/Latches : 6 # FD : 1 # FDC : 2 # FDE_1 : 1 # FDP : 1 # FDPE : 1 # Clock Buffers : 1 # BUFG : 1 # IO Buffers : 11 # IBUF : 3 # OBUF : 8 =========================================================================Article: 132336
"wzab" <wzab01@gmail.com> wrote in message news:7572b54b-1e31-433c-8c08-cd96f69d8351@k37g2000hsf.googlegroups.com... >> > How to identify the path generating the problem? >> > I can not run the timing analyzer, because the map fails. >> > -- >> > TIA & regards, >> > Wojtek Zabolotny >> >> Hi Wojtek, >> In the ISE GUI (I'm using 8.2 at the moment; I hope your version is >> similar), find the 'Processes' window. Expand the section 'Implement >> Design', then expand 'Map', then 'Generate Post-Map Static Timing'. If >> you >> double-click 'Analyze Post-Map Static Timing', it'll churn away and >> eventually open the timing analyser. You can then find what path is >> failing. >> The key insight is to run the timing analyser on the map results, before >> you >> enter the P&R phase. >> HTH, Syms. > > The problem is, that I can not 'Generate Post-Map Static Timing', > because the map fails! > -- > Wojtek Try this environmental variable before running P&R set XIL_TIMING_ALLOW_IMPOSSIBLE=1 Hans www.ht-lab.comArticle: 132337
hi,
Has anybody written ever an user_logic core for some device which is
interfaced to a microblaze? I don't know what's wrong with the following:
I used the wizard to generate a simple 8 bit led_port core with a few 32
bits registers. In C I write the following:
LedPortPtr = (Xuint32 *)XPAR_LED_PORT_0_BASEADDR;
while(1){
*(LedPortPtr) = 0xF3111111;
//print ("1");
*(LedPortPtr) = 0x0
//print("0");
}
The problem is that if I remove the print statements like above the port
doesn't show a square wave on an oscilloscope on one of the outputs. With
the print state it does.
With a dummy (volatile declared) delay loop it doesn't.
Readback of registers works fine.
the user_logic.vhd looks super simple:
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
else
case slv_reg_write_sel is
when "1000" =>
>>>>> LED_Out <= Bus2IP_Data(0 to 7);
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
The arrows show the only added line, except for the port declarations. Looks
like the serial print finishes some bus acknowledge or whatever. Any
examples somewhere of such a super simple core? I mean something which
actually outputs something.
Taco
Article: 132338taco wrote: sorry, I solved my question. For archive reasons: Need to use XIo_Out32(baseaddress + regoffset, data); The error was the result of a wrong impression based on a document from illinois institute of technology from internet which was doing as I described/Article: 132339
On 21 Mai, 21:40, Jim Granville <no.s...@designtools.maps.co.nz> wrote: > Antti wrote: > > On 21 Mai, 08:07, Peter Alfke <al...@sbcglobal.net> wrote: > > >>On May 20, 10:17 pm, Kim Enkovaara <kim.enkova...@iki.fi> wrote: > > >>Let's not turn this into a marketing slugfest. > >>It does not take a genius to figure out why Altera was forced to > >>embark on such a risky gamble... > >>"We live in interesting times" > >>Peter Alfke > > > waiting for Spartan-4 is boring.. not interesting :( > > I'm left wondering whatever happened to Altera's MAX III > devices ? ;) > > Seems to be 'missing in action' ? > > -jg I bet Lattice XP2 have killed MAX3 already the pricing for XP2 looks nice too :) AnttiArticle: 132340
Hi, we need to input a continous stream of 32 LVDS data bits at 1.25gbps per pin into a Virtex-5. There is a clock provided for each byte (source synchronous). There was a news item by Xilinx that says this is possible. But how many loops do I need to jump through to make it work? - What speedgrade do we need? - Is there a difference in timing between LXT, FXT and SXT for LVDS inputs? - Are there any constraints regarding the placement of the pins? Has anyone in this group done speeds like this before? Thanks, Kolja SulimmaArticle: 132341
I would like to erase and program these ROMs from a dedicated interface. Is there any data on how to do this using the JTAG pins? I've found some example code but not a device datasheet outlining the instructons etc.Article: 132342
I am unable to open a design for read/write editing in FPGA Editor 10.1. Does anyone know if this is the expected result ?Article: 132343
Kolja, I suggest you work with your FAE. It is challenging (for the signal integrity alone, not even considering the FPGA). The V5 has serdes capability built in per pin (pair), so this is what gets used (the fabric doesn't have to run this fast -- it can not). LXT, SXT, FXT all have identical LVDS. Speed grade does no apply to LVDS (they are all graded the same). How the design is done will determine what speed grade is required. I suspect you meant "how many hoops do I have to jump through" (not loops). I do not have an answer for you, other than people are doing this sort of thing. Austin Kolja Sulimma wrote: > Hi, > > we need to input a continous stream of 32 LVDS data bits at 1.25gbps > per pin into a Virtex-5. > There is a clock provided for each byte (source synchronous). > > There was a news item by Xilinx that says this is possible. But how > many loops do I need > to jump through to make it work? > > - What speedgrade do we need? > - Is there a difference in timing between LXT, FXT and SXT for LVDS > inputs? > - Are there any constraints regarding the placement of the pins? > > Has anyone in this group done speeds like this before? > > Thanks, > > Kolja SulimmaArticle: 132344
HT-Lab wrote: > Try this environmental variable before running P&R > > set XIL_TIMING_ALLOW_IMPOSSIBLE=1 > > Hans > www.ht-lab.com > > Can I mention the deep and abiding love I have for whoever decided that the options to MAP needed to be passed through a combination of command line arguments, settings files, and nearly undocumented environment variables, with any given setting only accessible through one of those? That hasn't complicated my build chain one tiny bit, nosireebob. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 132345
On Thu, 22 May 2008 08:12:14 +0100, "HT-Lab" wrote: >set XIL_TIMING_ALLOW_IMPOSSIBLE=1 Hey, that's not fair... When I want to do a "never ifdef" by testing an env var or macro that is sure to be absent, I usually use IMPOSSIBLE_THINGS_BEFORE_BREAKFAST - and that one is getting awfully, awfully close :-) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 132346
"John_H" <newsgroup@johnhandwork.com> wrote in message news:MYidnZvJYuCa5bfVnZ2dnUVZ_sjinZ2d@comcast.com... > Aren't we? :-) The code's locked away, but I'm thinking to add it to the multi-boot. There's something remarkably therapeutic about just idly twisting the simple do-nothing knob.Article: 132347
Hi All, I have to develop a fast data logger in FPGA, which stores the data in CY7C1386C memory. Unfortunately, the author of the board has connected only the ADNP signal, not the ADNC signal. In the datasheet ( http://eicom.ru/downloads/?pdf=/Cypress_PDFs/CY7C1386C1387C/CY7C1386C1387C.pdf ) on the page 27, there is only an example of extending the write burst with the ADNC signal. 1. Is it possible to use ADNP too extend the burst? 2. Do I need to lose one cycle for initiating the next burst? -- TIA & regards, Wojtek ZabolotnyArticle: 132348
Hi, I am looking for some tool / ip that can give me approximate gate count of mapper/demapper. Any helpful hint is greatly welcome. Thanks, VijayantArticle: 132349
<vijayant.rutgers@gmail.com> wrote in message news:57662a9c-7a37-4470-9468-faf94a5422f7@8g2000hse.googlegroups.com... > Hi, > I am looking for some tool / ip that can give me approximate gate > count of mapper/demapper. Any helpful hint is greatly welcome. > > Thanks, > Vijayant To get a gate count ... you have to synthesize it, the synthesis will give you an area and typical a "gate" is a 2 input NAND gate. So divide you're total area by the area of the NAND gate and that is your gate count. Mike
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