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I also checked the DCM output with Xilinx Coregen wizard. Except that Coregen infers DCM_SP for dcm, than DCM, the simulation outputs of Bob code and coregen inferred code are same. 8 MHz output is coming on clkout2. Bob, this may be the problem with Hardware. Please check whether ther is any short on the board of clock output pin with VCC. Regards, JKArticle: 129526
On 27 helmi, 00:45, George <whuste...@gmail.com> wrote: > I really appreciate if anyone can tell. Thanks > George > Why you don't convert your source files (VHDL, Verilog) to Xilinx? AnttiArticle: 129527
In a situation where it is necessary to cross between two clock domains within an FPGA, I might use logic that produces an output toggle (toggle_out) on the 2nd clock in response to a single-cycle pulse (pulse_in) on the 1st clock, using two processes and double buffering to mitigate metastability. In VHDL, it might look like this: signal t1, t2, toggle : std_logic; process(first_clk) begin if rising_edge(first_clk) if pulse_in = '1' then -- detect pulse on first_clk t1 <= not(t1); -- toggle signal t1 (on first_clk) end if; end if; end process; process(second_clk) variable t1_old, t2_old : std_logic; begin if rising_edge(second_clk) if t1 = not(t1_old) then -- detect toggle on t1 (domain cross here) t2 <= not(t2); -- then toggle t2 (on second_clk) end if; if t2 = not(t2_old) then -- detect toggle of t2 (double buffer) toggle <= not(toggle); -- toggle pulse end if; t1_old := t1; t2_old := t2; end if; end process; toggle_out <= toggle; The reset logic has been left out for clarity. In the second process, t1 is compared to its previous value (t1_old) to see if it has toggled. However, since the lines: a) if t1 = not(t1_old) b) t1_old := t1 occur sequentially, and t1 is asynchronous to second_clk (since the domain crossing occurs here), t1 could change between (a) and (b). I could insert an additional variable at the start of the process to register t1 so that it is only read once, but even that could be removed by the synthesizer during optimization. Alternatively, the synthesizer could decide to replicate logic anyway. Is there some way to tell the synthesizer (I use Xilinx XST) not to do any optimization or replication just on this module, or some other way to prevent this potential problem? Many thanks TomArticle: 129528
sdf wrote: > On Feb 27, 1:52 am, "Dwayne Dilbeck" <ddilb...@yahoo.com> wrote: > >>There are multiple way of doing this. In college 10 years ago, I wrote a C >>program to do this based on my engineering coarse at the time. Most >>synthesizers can do this to some extent. They will optimize it to fit in >>their target library. If the FPGA has a ram that it fits, The code may not >>be optimized becuase the fpga can just use the memory. > > > Yes, but I still don't know, what will be better in my case: generated > logic or just usual RAM blocks in FPGA. > It's interesting to see your work too, but is there anything already > incorporated into well-known EDA tools? Or, for example, Altera > Quartus, do this in automated way so I can free my mind from this? Depends how big 'big' is, and what the average bit density, and randomness is. You can certainly fit FONT roms, like 7 segment and Sine or palette tables into Logic - but I'd call those small tables. I've seen tools that map into Wide AND. OR (ie CPLD cells), but not ones that go a step further and use multiple layers of logic, with intermediate merge nodes. RAM is likely to be faster, and more deterministic. Code it as both, and see what the tools report ? -jgArticle: 129529
Sylvain Munaut wrote: > Hi, > > I wasn't very satisfied with the available assembler, so a few month > ago I wrote a new compiler for the Picobaze during my spare > weekends ... I think you mean a New Assembler ? > > I just though I'd share it if anyone is interested .... > > It's available there : > http://www.246tnt.com/files/PBAsm_20080225.tar.bz2 > > Example usage: > python ./Codegen.py example.S out.mem > > WARNING: The last file on the command line is the output ... so if you > forget it, it will overwrite your last source file ... > > What are the pro and cons: > > pros: > - Cross platform > - It supports local label, so for labels that don't really deserve a > name you can do things like > > load s0, 15 > 1: > sub s0, 1 > jump nz, 1b > > And the '1b' reference says to find the first label named 1 when > going 'back' (1f would be forward...). > Local labels are just a single digit. Hmmm - could be dangerous for maintenance. Another scheme is to use '?' or similar prefix to mean local label. > About the hw mods to the hw : > - I removed the ScratchPad distributed RAM and used the second port > on the BRAM as scratch pad. The second port is configured as 8 bit > width and with upper address lines mapped to 1 so that the SP is > located at the end of the BRAM. (Be careful when playing with this and > interruptions, the last 2 bytes of the scratch pad is the interrupt > vector ...) And the bonus is a 256 byte scratch pad, just sacrificing > 128 instruction words ... (adjust mapping for other tradeoffs) Have you looked at the Lattice Mico8 - Quite similar to the Picoblaze, but more formally opensource, and they have just extended it to make it more 'HLL ready'. Have a look and see if your opcode extensions can fit into their decode ? -jgArticle: 129530
Hi everybody, I work with a VirtexIIPro in a design with PowerPC processor. I have some problems with the opb_mdm to work as uart. My board has not RS232 peripheral, so I used a OPB_MDM and a PLB2OPB bridge. This solution does not seem to be enough and I receive quite a lot error message such as "Unable to connect processor" in my XMDSTUB console. I explain what I do when I download the bootloop application and Init my xmdstub console: connect mdm -uart read_uart dow executable.elf con My best regardsArticle: 129531
How can the RTL schematic of a VHDL design be viewed in Xilinx ISE 9.2? I just upgraded from 8.2 because I couldn't find it there (and the upgrade was long due anyway), but I still have not found it. I have searched the web and all references to viewing RTL schematic seem to point to 7.x documentation. Using that method is not possible because the options are not there anymore in 8.2/9.2. -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail) "Computers in the future may weigh no more than 1.5 tons." (Popular Mechanics, 1949)Article: 129532
On Tue, 26 Feb 2008 12:59:11 -0800, Brad Smallridge wrote: >Listed below is a simple NoBL SRAM model that >I use to help me debug. Recently, I've been >getting a ModelSim error numstd_conv_unsigned_nu >Natural arg value is negative. [snip model] You've used an array of integers to model the memory's storage. This is a neat idea - efficient for simulation - BUT your memory is 36 bits wide, which won't fit into an integer! The specific problem you're seeing is almost certainly that you are reading from an unwritten location. For example, on the first few clock cycles the memory will do reads from location 0 which hasn't yet been written, because the X/U values on address will be converted to zero by the numeric_std.to_integer() conversion on the address. (Did you see warnings for that, or did you suppress them?) Unwritten (uninitialised) integers in your memory array will start life at the most negative possible value. The fix to your immediate problem is to declare the memory storage as an array of natural rather than integer, so that its contents initialise to zero. This will stop the conversion overflows, but will still leave you unable to represent more than 31 bits in each integer data word. Another possible hack is to keep the integers, and detect value<0 to indicate that the memory has never been written at that location; you can then put out X values on the std_logic_vector read data. The better fix (especially since you're keeping the memory size fairly small) is to represent the memory as an array of std_logic_vector to match the read and write data ports. Or, perhaps, to split the memory into two 18-bit halves (internally) and use integers for each half, again using negative values to represent uninitialised or unknown conditions. HTH -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 129533
Hello Techies, I would like to use an off the shelf FPGA which I would be develpoing to test an ASIC or other FPGA. My questions is, 1. How do we connect the Output of FPGAs as Input of the ASIC and vice versa? 2. The FPGA has to check various protocols like SPI, UART and other things? I need to know various methods by which this can be done. Any answers on this will be greatly apprecaited. Thanks in advance. Regards Hariharan K Srinivasan.Article: 129534
usually a tool called "soldering iron" must be used. Antti On 27 Feb., 10:42, harisr...@gmail.com wrote: > Hello Techies, > I would like to use an off the shelf FPGA which I would be develpoing > to test an ASIC or other FPGA. My questions is, > 1. How do we connect the Output of FPGAs as Input of the ASIC and vice > versa? > 2. The FPGA has to check various protocols like SPI, UART and other > things? > > I need to know various methods by which this can be done. Any answers > on this will be greatly apprecaited. > > Thanks in advance. > > Regards > Hariharan K Srinivasan.Article: 129535
On Wed, 27 Feb 2008 02:08:34 -0800 (PST), Antti wrote: >usually a tool called "soldering iron" must be used. LOL. Antti, that's unfair.... In the interests of public safety, you should at least have explained which end of it he should pick up. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 129536
On 27 Feb., 12:18, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > On Wed, 27 Feb 2008 02:08:34 -0800 (PST), Antti wrote: > >usually a tool called "soldering iron" must be used. > > LOL. > > Antti, that's unfair.... In the interests of public > safety, you should at least have explained which > end of it he should pick up. > -- > Jonathan Bromley, Consultant > Hmm let me think... I think must pick ASIC end first? AnttiArticle: 129537
Will it be possible to use indirect programming of an SPI flash for Spartan 3E in future releases of ISE ? Im using 9.2, and if i choose "Enable programming of SPI flash device attached to this FPGA" in the assign new configuration file i get a message : "The device selected does not support the BPI or SPI external programming option" So does anyone know if this feature will be available to Spartan3E in the future?Article: 129538
> How can the RTL schematic of a VHDL design be viewed in Xilinx ISE 9.2? > I just upgraded from 8.2 because I couldn't find it there (and the > upgrade was long due anyway), but I still have not found it. In the Sources window select the desired module. In the Processes window run "View RTL Schematic". This will generate a top level symbol in which you can "Push into the Selected Instance" or "Pop to the Calling Schematic" by double clicking or using the context menu. Randy HaasArticle: 129539
On 27 Feb., 13:13, kislo <kisl...@student.sdu.dk> wrote: > Will it be possible to use indirect programming of an SPI flash for > Spartan 3E in future releases of ISE ? Im using 9.2, and if i choose > "Enable programming of SPI flash device attached to this FPGA" in the > assign new configuration file i get a message : "The device selected > does not support the BPI or SPI external programming option" > So does anyone know if this feature will be available to Spartan3E in > the future? I think not from Xilinx I use my own tools for S3e AnttiArticle: 129540
In comp.arch.fpga, randallchaas@sbcglobal.net <randallchaas@sbcglobal.net> wrote: >> How can the RTL schematic of a VHDL design be viewed in Xilinx ISE 9.2? >> I just upgraded from 8.2 because I couldn't find it there (and the >> upgrade was long due anyway), but I still have not found it. > > In the Sources window select the desired module. In the Processes > window run "View RTL Schematic". This will generate a top level symbol > in which you can "Push into the Selected Instance" or "Pop to the > Calling Schematic" by double clicking or using the context menu. > Randy Haas That is the what all docs I found tell me as well, but cant find it. :-( I finally figured it out! I start ISE from Modelsim designer, and then ISE only shows a top-level design.ngc file, no vhdl sources. This has no "View RTL Schematic" in the process window. Double clicking it gives a TCL error, but if I choose file->open and then open design.ngc (or design.ngr, they are different), then I finally see the RTL schematic. Thank you all for listening. -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail) "Computers in the future may weigh no more than 1.5 tons." (Popular Mechanics, 1949)Article: 129541
On Feb 27, 1:22 am, antti.tyrvai...@luukku.com wrote: > On 27 helmi, 00:45, George <whuste...@gmail.com> wrote: > > > I really appreciate if anyone can tell. Thanks > > George > > Why you don't convert your source files (VHDL, Verilog) to Xilinx? > > Antti My situation is I don't have the source files. I just want to deal with the P&R circuit.Article: 129542
The new Cortex A8 OMAP from TI has an entertainingly solderable package for the DIY enthusiast: 5l5-pin PBGA Package, 0.5mm Ball Pitch (Top), 0.4mm Ball Pitch (Bottom) Still, at 14x14mm, the package gives you room to work. A good test for a toaster oven....Article: 129543
Symon wrote: > checo wrote: >> On Feb 26, 10:22 am, Philip Potter <p...@doc.ic.ac.uk> wrote: >>> Symon wrote: >>>> Philip Potter wrote: >>>>> Nico Coesel wrote: >>>>>> "Symon" <symon_bre...@hotmail.com> wrote: >>>>>>> Nico Coesel wrote: >>>>>>>> The best answer to all these questions is a question. >>>>>>> Is it? >>>>>> Ofcourse. Interview questions are designed to start a technical >>>>>> debate in order to reveal the applicant's knowledge (or lack >>>>>> thereof). >>>>> Is that the only purpose? >>>> What other purpose could there be? >>> What are you suggesting? >> Isn't it obvious? > To whom? Hasn't this gone on long enough? :)Article: 129544
Hi I was not sure if i can get a working demo ready but it looks it I did: http://xiltendo.com it just shows a handheld device running embedded XSVF player executing some XSVF file from micro-SD card. Wi-fi support is not included, but is defenetly possible as well. I hope to be tomorow at Embedded, so if maybe can show the configurator in action, if anyone interested, will be around Xilinx stand in the afternoon (1600?), and maybe also at stand 12.536 at some times or moving around http://www.antti-brain.com the above for face recognition :) AnttiArticle: 129545
"Philip Potter" <pgp@doc.ic.ac.uk> wrote in message news:fq41e6$889$1@aioe.org... > Symon wrote: >> checo wrote: >>> On Feb 26, 10:22 am, Philip Potter <p...@doc.ic.ac.uk> wrote: >>>> Symon wrote: >>>>> Philip Potter wrote: >>>>>> Nico Coesel wrote: >>>>>>> "Symon" <symon_bre...@hotmail.com> wrote: >>>>>>>> Nico Coesel wrote: >>>>>>>>> The best answer to all these questions is a question. >>>>>>>> Is it? >>>>>>> Ofcourse. Interview questions are designed to start a technical >>>>>>> debate in order to reveal the applicant's knowledge (or lack >>>>>>> thereof). >>>>>> Is that the only purpose? >>>>> What other purpose could there be? >>>> What are you suggesting? >>> Isn't it obvious? >> To whom? > Hasn't this gone on long enough? :) noArticle: 129546
Hi,
I have implemented a Microblaze v7.00.b with EDK 9.2 on a Virtex 4
fx12. A timer (xps_timer v1.00.a) generates an interrupt which is
relayed by an interrupt controller (xps_intc v1.00.a) to the interrupt
pin of the Microblaze. The code uses the standalone library.
The piece of code that handles this interrupt only increment a
variable and display it using "xil_printf" instruction.
If i put an infinite loop "while(1)", at the end of the initialisation
of the timer and the interrupt controller, the interrupt is normaly
handled each time it occurs unless there is a rand() or srand()
instruction in the code just before the "while(1)". When a rand() or
srand() instruction is used, the interrupt that occurs just after is
not handled, the microblaze is then frozen and a reset does not allow
to re-run the programm as if it has been corrupted.
The code of the handler:
void TimerCounterHandler(void *CallBackRef, Xuint8 TmrCtrNumber)
{
Counter +=3D 1;
xil_printf("\r\ntime: %d s",Counter);
}
The setup of the timer and the interrupt controller:
XStatus Status;
//Initialize the timer counter
Status =3D XTmrCtr_Initialize(&my_timer, TIMER_DEVICE_ID);
//Initialize the interrupt controller driver
Status =3D XIntc_Initialize(&my_int_controller, INTC_DEVICE_ID);
//Connect the interrupt controller to the timer
Status =3D XIntc_Connect( &my_int_controller, TIMER_INTERRUPT_ID,
(XInterruptHandler)XTmrCtr_InterruptHandler,
(void *)&my_timer);
//Start the interrupt controller in real mode
Status =3D XIntc_Start(&my_int_controller, XIN_REAL_MODE);
//Enable the interrupt for the timer
XIntc_Enable(&my_int_controller, INTC_DEVICE_ID);
//Enable the interrupts on the Microblaze
microblaze_enable_interrupts();
//Set the handler to call when the timer is expired
XTmrCtr_SetHandler( &my_timer,
TimerCounterHandler,
&my_timer);
//set the timer to autoreload mode and decreasing mode (increase is
the default mode)
XTmrCtr_SetOptions( &my_timer,
TIMER_NBR_0,
XTC_INT_MODE_OPTION |
XTC_AUTO_RELOAD_OPTION );
XTmrCtr_SetResetValue( &my_timer,
TIMER_NBR_0,
RESET_VALUE);
//Start the timer counter
XTmrCtr_Start( &my_timer,TIMER_NBR_0);
/**********************************
*
* this one works
***********************************/
//int i;
//i =3D rand()%1000;
while(1)
{
// the interrupt occurs and is handled.
}
/**********************************
*
* this one does not work
***********************************/
int i;
i =3D rand()%1000;
while(1)
{
// freeze of the microblaze when the interrupt occurs.
}
Regards,
R=E9my
Article: 129547Mike Lewis schrieb: > "Philip Potter" <pgp@doc.ic.ac.uk> wrote in message >> Symon wrote: >>> checo wrote: >>>> On Feb 26, 10:22 am, Philip Potter <p...@doc.ic.ac.uk> wrote: >>>>> Symon wrote: >>>>>> Philip Potter wrote: >>>>>>> Nico Coesel wrote: >>>>>>>> "Symon" <symon_bre...@hotmail.com> wrote: >>>>>>>>> Nico Coesel wrote: >>>>>>>>>> The best answer to all these questions is a question. >>>>>>>>> Is it? >>>>>>>> Ofcourse. Interview questions are designed to start a technical >>>>>>>> debate in order to reveal the applicant's knowledge (or lack >>>>>>>> thereof). >>>>>>> Is that the only purpose? >>>>>> What other purpose could there be? >>>>> What are you suggesting? >>>> Isn't it obvious? >>> To whom? >> Hasn't this gone on long enough? :) > no Warning! Approaching quote recursion overflow! ;-)Article: 129548
> > I wasn't very satisfied with the available assembler, so a few month > > ago I wrote a new compiler for the Picobaze during my spare > > weekends ... > > I think you mean a New Assembler ? Yes :) I was careful in the subject but that one slipped. > > - It supports local label, so for labels that don't really deserve a > > name you can do things like > > > load s0, 15 > > 1: > > sub s0, 1 > > jump nz, 1b > > > And the '1b' reference says to find the first label named 1 when > > going 'back' (1f would be forward...). > > Local labels are just a single digit. > > Hmmm - could be dangerous for maintenance. Another scheme is to use '?' > or similar prefix to mean local label. I've used the same convention as the GNU assembler. I've modelled the syntax after theirs, but making sure it's easy to parse with Lex / YACC. As it was my first lex/yacc experience I didn't want to take too much time to make it work. Especially since I needed that compiler to ease my work for a commercial project with an approaching dead line :) > Have you looked at the Lattice Mico8 - Quite similar to the Picoblaze, > but more formally opensource, and they have just extended it to make it > more 'HLL ready'. > > Have a look and see if your opcode extensions can fit into their > decode ? I had a look at the Lattrice Mico8. But since my target was Xilinx, the picoblaze seemed like a better choice (smaller and faster ...) I didn't investigate further and just coded this assembler to have an easier time when programming it. I'm not that interested in HLL because when I uses theses. But a macro preprocessor would be nice :) SylvainArticle: 129549
> Of course, you're working on the simulator now, right? :)
I don't think so ... I rarely used the one that are available because
the code on the picoblaze is often so dependent on the hw around it
that it just doesn't do anything meaning full without it ...
What I did is that my assembler output a symbol table and so in the
modelsim you can get it to display :
uart_print_str + 0x00, uart_print_str + 0x01 .... instead of the
addesses in the code, and also the variable name instead of address in
the scratch pad. Very useful to trace what's going on.
Sylvain
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