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On Jun 8, 11:26 am, Antti <Antti.Luk...@googlemail.com> wrote: > Ed McGettigan schrieb: > > > > > Antti wrote: > > >http://www.zylogic.com.cn/english/products04.htm > > > > I wonder what that is? > > > it looks like the product Triscend never announced, but maybe its a > > > hoax, > > > still funny at least the spec are known now what Triscend was about to > > > announce > > > just before it was purchased by Xilinx > > > > Antti > > > Zylogic and Rochester were handling the end-of-life commitments > > that were in place for the Triscend parts. I would be a bit > > shocked if they would even take an order at this point unless > > they still had some parts in stock. > > > Ed McGettigan > > -- > > Xilinx Inc. > > me too :) > > was just surprised those pages are still online!! > maybe its some "time freeze zone" ;) > > Antti Its a chinese website. Check out "About" the company.Article: 120551
Hi,
since I want to start with my brand new xilinx Spartan 3e board on linux
I followed the Answer Record #22648 for the linux 2.6.21 kernel and
ISE9.1 at
http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=22648
Compiling the debian kernel I followed one of the howtos on net
(http://www.falkotimme.com/howtos/debian_kernel2.6_compile/).
Anyway, compiling of the driver failed:
tuxler:/usr/src/xilinx-usb-driver/install_drivers# ./install_drivers
--Kernel version = 2.6.21-1-686.
--Arch = i686.
--Installer version = 1029
--User has root permission.
--File /lib/modules/misc/install_windrvr6 does not exist.
--Installing windrvr6---------------------------------------------
loading cache ./config.cache
checking for cpu architecture... i386
checking for WinDriver root directory...
/usr/src/xilinx-usb-driver/install_drivers/linux_drivers/windriver32
checking for linux kernel source... found at /lib/modules/2.6.21-1-686/build
checking for lib directory... /usr/lib
checking which directories to include...
-I/lib/modules/2.6.21-1-686/build/include
-I/lib/modules/2.6.21-1-686/build/include/asm/mach-default
checking linux kernel version... ./configure: line 651: test: too many
arguments
int init_module(void) { char *jsver = UTS_RELEASE; return 0; }
checking for modules installation directory... ./configure: line 659:
test: too many arguments
/lib/modules/misc
checking for gcc kernel version... 4
checking output directory... LINUX.int init_module(void) { char *jsver =
UTS_RELEASE; return 0; }.i386
checking target... LINUX.int init_module(void) { char *jsver =
UTS_RELEASE; return 0; }.i386/windrvr6.o
checking for usb support... yes
checking for right linked object... windrvr_gcc_v3.a
creating ./config.status
creating makefile
makefile:25: *** missing separator. Schluss.
makefile:25: *** missing separator. Schluss.
--make windrvr rc = 2
--install_windrvr6 rc = 2
--Installing USB drivers------------------------------------------
--Using udev.
--File /usr/share/xusbdfwu.hex exists.
--File /usr/share/xusbdfwu.hex version = 1025
--File xusbdfwu.hex exists.
--File xusbdfwu.hex version = 1025
--File xusbdfwu.hex is already updated.
--File /etc/udev/rules.d/xusbdfwu.rules exists.
--File /etc/udev/rules.d/xusbdfwu.rules version = 0001
--File xusbdfwu.rules exists.
--File xusbdfwu.rules version = 0001
--File xusbdfwu.rules is already updated.
--File /sbin/fxload exists.
--install_pcusb rc = 0
--Module windrvr6 is not running.
--Module xpc4drvr is not running.
--Note: By default, the file permission of /dev/windrvr6 is enabled for
the root user only
and must be changed to allow access to other users.
Any ideas what is going on here?
Thanks
Olaf
Article: 120552
Hi,
did some more tries. Writing the Firmware to the USB Controller using
fxload got:
# /sbin/fxload -v -t fx2 -I /opt/Xilinx91i/bin/lin/xusbdfwu.hex -D
/proc/bus/usb/004/010
microcontroller type: fx2
single stage: load on-chip memory
open RAM hexfile image /opt/Xilinx91i/bin/lin/xusbdfwu.hex
stop CPU
write on-chip, addr 0x1d29 len 10 (0x000a)
write on-chip, addr 0x06d9 len 12 (0x000c)
write on-chip, addr 0x170d len 81 (0x0051)
write on-chip, addr 0x0c4c len 536 (0x0218)
write on-chip, addr 0x156e len 120 (0x0078)
write on-chip, addr 0x1c59 len 23 (0x0017)
write on-chip, addr 0x0090 len 232 (0x00e8)
write on-chip, addr 0x06e5 len 584 (0x0248)
write on-chip, addr 0x15e6 len 112 (0x0070)
write on-chip, addr 0x1d44 len 6 (0x0006)
write on-chip, addr 0x1c9c len 21 (0x0015)
write on-chip, addr 0x175e len 73 (0x0049)
write on-chip, addr 0x1cb1 len 20 (0x0014)
write on-chip, addr 0x1962 len 65 (0x0041)
write on-chip, addr 0x1af5 len 46 (0x002e)
write on-chip, addr 0x1000 len 475 (0x01db)
write on-chip, addr 0x12fd len 3 (0x0003)
write on-chip, addr 0x092d len 5 (0x0005)
write on-chip, addr 0x19bb len 59 (0x003b)
write on-chip, addr 0x1cfa len 13 (0x000d)
write on-chip, addr 0x12ab len 82 (0x0052)
write on-chip, addr 0x1cc5 len 18 (0x0012)
write on-chip, addr 0x1d13 len 11 (0x000b)
write on-chip, addr 0x1cd7 len 18 (0x0012)
write on-chip, addr 0x1d50 len 5 (0x0005)
write on-chip, addr 0x0178 len 1008 (0x03f0)
write on-chip, addr 0x0568 len 369 (0x0171)
write on-chip, addr 0x1b23 len 44 (0x002c)
write on-chip, addr 0x1c1c len 20 (0x0014)
write on-chip, addr 0x1ac6 len 47 (0x002f)
write on-chip, addr 0x1b4f len 44 (0x002c)
write on-chip, addr 0x18d8 len 70 (0x0046)
write on-chip, addr 0x1c30 len 17 (0x0011)
write on-chip, addr 0x0043 len 3 (0x0003)
write on-chip, addr 0x0053 len 3 (0x0003)
write on-chip, addr 0x1300 len 184 (0x00b8)
write on-chip, addr 0x0932 len 2 (0x0002)
write on-chip, addr 0x1bf6 len 38 (0x0026)
write on-chip, addr 0x1c41 len 24 (0x0018)
write on-chip, addr 0x19a3 len 22 (0x0016)
write on-chip, addr 0x1c70 len 22 (0x0016)
write on-chip, addr 0x1800 len 144 (0x0090)
write on-chip, addr 0x0ffe len 2 (0x0002)
write on-chip, addr 0x17fe len 2 (0x0002)
write on-chip, addr 0x1d5d len 31 (0x001f)
write on-chip, addr 0x1a96 len 48 (0x0030)
write on-chip, addr 0x19b9 len 2 (0x0002)
write on-chip, addr 0x0934 len 4 (0x0004)
write on-chip, addr 0x1890 len 72 (0x0048)
write on-chip, addr 0x1ba5 len 41 (0x0029)
write on-chip, addr 0x17f0 len 14 (0x000e)
write on-chip, addr 0x1b7b len 42 (0x002a)
write on-chip, addr 0x17a7 len 73 (0x0049)
write on-chip, addr 0x19f6 len 56 (0x0038)
write on-chip, addr 0x1d3c len 8 (0x0008)
write on-chip, addr 0x1d4a len 6 (0x0006)
write on-chip, addr 0x0080 len 16 (0x0010)
write on-chip, addr 0x1d07 len 12 (0x000c)
write on-chip, addr 0x1d1e len 11 (0x000b)
write on-chip, addr 0x1d33 len 9 (0x0009)
write on-chip, addr 0x0938 len 4 (0x0004)
write on-chip, addr 0x000b len 3 (0x0003)
write on-chip, addr 0x1a2e len 52 (0x0034)
write on-chip, addr 0x0033 len 3 (0x0003)
write on-chip, addr 0x1d55 len 4 (0x0004)
write on-chip, addr 0x093c len 149 (0x0095)
write on-chip, addr 0x13b8 len 156 (0x009c)
write on-chip, addr 0x1bce len 40 (0x0028)
write on-chip, addr 0x16b3 len 90 (0x005a)
write on-chip, addr 0x1c86 len 22 (0x0016)
write on-chip, addr 0x1a62 len 52 (0x0034)
write on-chip, addr 0x1656 len 93 (0x005d)
write on-chip, addr 0x1d59 len 4 (0x0004)
write on-chip, addr 0x1ce9 len 17 (0x0011)
write on-chip, addr 0x191e len 68 (0x0044)
write on-chip, addr 0x11db len 208 (0x00d0)
write on-chip, addr 0x1454 len 142 (0x008e)
write on-chip, addr 0x0f98 len 102 (0x0066)
write on-chip, addr 0x0e64 len 308 (0x0134)
write on-chip, addr 0x0000 len 3 (0x0003)
write on-chip, addr 0x14e2 len 12 (0x000c)
write on-chip, addr 0x09d2 len 555 (0x022b)
write on-chip, addr 0x14ee len 128 (0x0080)
write on-chip, addr 0x09d1 len 1 (0x0001)
write on-chip, addr 0x0bfd len 79 (0x004f)
... WROTE: 7435 bytes, 85 segments, avg 87
reset CPU
Writing the firmware on windows flash the USB LED red, at this LED off
for about 2 sec and green again. As I understood udev on linux this
should be called automatically if the vendor ID on bus appeared:
SYSFS{idVendor}=="03fd", SYSFS{idProduct}=="0008", NAME="windrvr6"
BUS=="usb", ACTION=="add", SYSFS{idVendor}=="03fd",
SYSFS{idProduct}=="0007", RUN+="/sbin/fxload -v -t fx2 -I
/opt/Xilinx91i/bin/lin/xusbdfwu.hex -D $TEMPNODE"
BUS=="usb", ACTION=="add", SYSFS{idVendor}=="03fd",
SYSFS{idProduct}=="0009", RUN+="/sbin/fxload -v -t fx2 -I
/opt/Xilinx91i/bin/lin/xusbdfwu.hex -D $TEMPNODE"
BUS=="usb", ACTION=="add", SYSFS{idVendor}=="03fd",
SYSFS{idProduct}=="000b", RUN+="/sbin/fxload -v -t fx2 -I
/opt/Xilinx91i/bin/lin/xusbdfwu.hex -D $TEMPNODE"
BUS=="usb", ACTION=="add", SYSFS{idVendor}=="03fd",
SYSFS{idProduct}=="000d", RUN+="/sbin/fxload -v -t fx2 -I
/opt/Xilinx91i/bin/lin/xusbdfwu.hex -D $TEMPNODE"
BUS=="usb", ACTION=="add", SYSFS{idVendor}=="03fd",
SYSFS{idProduct}=="000f", RUN+="/sbin/fxload -v -t fx2 -I
/opt/Xilinx91i/bin/lin/xusbdfwu.hex -D $TEMPNODE"
Something wrong?
Thanks
Olaf
Article: 120553
> SYSFS{idVendor}=="03fd", SYSFS{idProduct}=="0008", NAME="windrvr6"
> BUS=="usb", ACTION=="add", SYSFS{idVendor}=="03fd",
> SYSFS{idProduct}=="0007", RUN+="/sbin/fxload -v -t fx2 -I
> /opt/Xilinx91i/bin/lin/xusbdfwu.hex -D $TEMPNODE"
> BUS=="usb", ACTION=="add", SYSFS{idVendor}=="03fd",
> SYSFS{idProduct}=="0009", RUN+="/sbin/fxload -v -t fx2 -I
> /opt/Xilinx91i/bin/lin/xusbdfwu.hex -D $TEMPNODE"
> BUS=="usb", ACTION=="add", SYSFS{idVendor}=="03fd",
> SYSFS{idProduct}=="000b", RUN+="/sbin/fxload -v -t fx2 -I
> /opt/Xilinx91i/bin/lin/xusbdfwu.hex -D $TEMPNODE"
> BUS=="usb", ACTION=="add", SYSFS{idVendor}=="03fd",
> SYSFS{idProduct}=="000d", RUN+="/sbin/fxload -v -t fx2 -I
> /opt/Xilinx91i/bin/lin/xusbdfwu.hex -D $TEMPNODE"
> BUS=="usb", ACTION=="add", SYSFS{idVendor}=="03fd",
> SYSFS{idProduct}=="000f", RUN+="/sbin/fxload -v -t fx2 -I
> /opt/Xilinx91i/bin/lin/xusbdfwu.hex -D $TEMPNODE"
>
> Something wrong?
Yes, as the README says, the line
ACTION=="add", BUS=="usb", SYSFS{idVendor}=="03fd", MODE="666"
is required! Now it works, huray!
Thanks
Olaf
Article: 120554Hi, On Sat, 09 Jun 2007 08:46:31 +0200, Olaf wrote: > usb 4-5.4: new full speed USB device using ehci_hcd and address 5 > usb 4-5.4: not running at top speed; connect to a high speed hub > usb 4-5.4: configuration #3 chosen from 1 choice > > The green LED is on. Green on a S3E starter kit means that the cypress usb firmware is running. Did you connect the board on windows and booted to linux without power-cycling the board? > lsubs got: > Bus 004 Device 002: ID 04b4:6560 Cypress Semiconductor Corp. CY7C65640 > USB-2.0 "TetraHub" > Bus 004 Device 001: ID 0000:0000 Did you connect the board to a hub? If so, try it without the hub. It should show up the following when the green led is off: Bus 002 Device 009: ID 03fd:000d Xilinx, Inc. And when the firmware is loaded (green led on): Bus 002 Device 012: ID 03fd:0008 Xilinx, Inc. > Connecting to cable (Usb Port - USB21). > Checking cable driver. > Cable autodetection failed. Impact is specifically looking for an USB device with the ID 03fd:0008 and can't find it. The flashing with red led you described in your other post is downloading the cpld image and should only happen when you upgrade ISE and there is a new version available. > Kernel is 2.6.21 (debian/testing), Impact 9.1.03i. Should work. > Compiling the xilinx stuff suffers/fails from wrong kernel version depency. And won't help if you do not see the download cable in the lsusb-output. Regards, MichaelArticle: 120555
Antti wrote: > > yes I am sure silicon samples are available, I was more refereffing to > those > lattice evaluation kits that are "contact lattice" those are usually > not for sale, > but only to lease.. this is STUPID STUPID... i have tried to purchase > some > lattice boards, only to get offer to lease the board. :( Maybe that's driven by some 3rd party SW license issue - seems a silly idea for hardware, and it has to cost them more to admin that, than a straight sale ? -jgArticle: 120556
On Jun 7, 5:16 pm, willwestw...@gmail.com wrote:
> On Jun 7, 3:54 pm, Eric Smith <e...@brouhaha.com> wrote:
>
> > willwestw...@gmail.com writes:
> > > I hope I explained ok here. I'm having trouble putting this behavior
> > > into codes in VHDL. Someone has any idea?
>
> > How would you design it with logic gates (and flip-flops, if required)?
>
> > Once you know that, you can just do the same thing in VHDL.
>
> Yes you can do it in logic gates, but I want behavior modeling. If
> using FF and logic gates, it would make this totally a netlist
> coding.
>
> Here is the Requset, Reset, and Acknowledge again:
>
> Request(0 to 3): 0000 1010 0110 1101 0010 1001 0001 1000 1011 1011
> 1000 0101 1001
> Reset:
> HHHHLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLHHHHLLLLLLLLLLLLLLLLLLLLL
> Ack(0 to 3): 0000 1000 0010 0100 0010 1000 0001 1000 0000 1000
> 1000 0100 0001
>
> I also plan to convert this code into Verilog, C or C++ later on, so
> if you have algorithm or codes in those languages, it's fine too.
Here is my code. There's a problem, the acknowledge only changes on
reset='1' and request='1111'. How can I fix this so it will give the
right output like the behavior given earlier?
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
entity rrarbiter is
port ( request : in std_logic_vector(0 to 3);
reset : in std_logic;
acknowledge : inout std_logic_vector(0 to 3)
);
end entity rrarbiter;
architecture rrobin_behave of rrarbiter is
signal reg_ack: std_logic_vector(0 to 3); --:=std_logic_vector'(B"0000");
begin
behavior: process(reset, request)
begin
if reset = '1' then
acknowledge <= std_logic_vector'("0000");
------IF BIT IN ACKNOWLEDGE IS NOT IN REQUEST THEN
acknowledge<=MSB SET OF acknowledge----
elsif NOT(request(0)=reg_ack(0) or
request(1)=reg_ack(1) or request(2)=reg_ack(2) or
request(3)=reg_ack(3)) then
if request(0)='1' then
acknowledge<= std_logic_vector'("1000");
elsif request(1)='1' then
acknowledge<= std_logic_vector'("0100");
elsif request(2)='1' then
acknowledge<= std_logic_vector'("0010");
elsif request(3)='1' then
acknowledge<= std_logic_vector'("0001");
end if;
-----A BIT IN REQUEST IS ALSO IN acknowledge THEN
acknowledge<=REG_ACK----
elsif (request(0)=reg_ack(0) or
request(1)=reg_ack(1) or request(2)=reg_ack(2) or
request(3)=reg_ack(3)) then
if request(0)='1' and reg_ack(0)='1'then
acknowledge <= std_logic_vector'("1000");
elsif request(1)='1' and reg_ack(1)='1' then
acknowledge<= std_logic_vector'("0100");
elsif request(2)='1' and reg_ack(2)='1' then
acknowledge<= std_logic_vector'("0010");
elsif request(3)='1' and reg_ack(3)='1' then
acknowledge<= std_logic_vector'("0001");
end if;
end if;
end process;
reg_ack <= acknowledge;
end rrobin_behave;
Article: 120557
Olaf,
Check out the userspace drivers:
http://www.rmdir.de/~michael/xilinx/
I think you can save yourself a lot of grief, especially every time you
update your kernel...
ken
Olaf wrote:
> Hi,
>
> since I want to start with my brand new xilinx Spartan 3e board on linux
> I followed the Answer Record #22648 for the linux 2.6.21 kernel and
> ISE9.1 at
> http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=22648
>
> Compiling the debian kernel I followed one of the howtos on net
> (http://www.falkotimme.com/howtos/debian_kernel2.6_compile/).
>
> Anyway, compiling of the driver failed:
>
> tuxler:/usr/src/xilinx-usb-driver/install_drivers# ./install_drivers
> --Kernel version = 2.6.21-1-686.
> --Arch = i686.
> --Installer version = 1029
> --User has root permission.
> --File /lib/modules/misc/install_windrvr6 does not exist.
> --Installing windrvr6---------------------------------------------
> loading cache ./config.cache
> checking for cpu architecture... i386
> checking for WinDriver root directory...
> /usr/src/xilinx-usb-driver/install_drivers/linux_drivers/windriver32
> checking for linux kernel source... found at /lib/modules/2.6.21-1-686/build
> checking for lib directory... /usr/lib
> checking which directories to include...
> -I/lib/modules/2.6.21-1-686/build/include
> -I/lib/modules/2.6.21-1-686/build/include/asm/mach-default
> checking linux kernel version... ./configure: line 651: test: too many
> arguments
> int init_module(void) { char *jsver = UTS_RELEASE; return 0; }
> checking for modules installation directory... ./configure: line 659:
> test: too many arguments
> /lib/modules/misc
> checking for gcc kernel version... 4
> checking output directory... LINUX.int init_module(void) { char *jsver =
> UTS_RELEASE; return 0; }.i386
> checking target... LINUX.int init_module(void) { char *jsver =
> UTS_RELEASE; return 0; }.i386/windrvr6.o
> checking for usb support... yes
> checking for right linked object... windrvr_gcc_v3.a
> creating ./config.status
> creating makefile
> makefile:25: *** missing separator. Schluss.
> makefile:25: *** missing separator. Schluss.
> --make windrvr rc = 2
> --install_windrvr6 rc = 2
> --Installing USB drivers------------------------------------------
> --Using udev.
> --File /usr/share/xusbdfwu.hex exists.
> --File /usr/share/xusbdfwu.hex version = 1025
> --File xusbdfwu.hex exists.
> --File xusbdfwu.hex version = 1025
> --File xusbdfwu.hex is already updated.
> --File /etc/udev/rules.d/xusbdfwu.rules exists.
> --File /etc/udev/rules.d/xusbdfwu.rules version = 0001
> --File xusbdfwu.rules exists.
> --File xusbdfwu.rules version = 0001
> --File xusbdfwu.rules is already updated.
> --File /sbin/fxload exists.
> --install_pcusb rc = 0
> --Module windrvr6 is not running.
> --Module xpc4drvr is not running.
> --Note: By default, the file permission of /dev/windrvr6 is enabled for
> the root user only
> and must be changed to allow access to other users.
>
> Any ideas what is going on here?
>
> Thanks
> Olaf
Article: 120558Hello Michael, now it works, the problem was I thought that the mentioned udev line in the readme is optional, which isn't. After adding the line it works. Thanks OlafArticle: 120559
Jim Granville schrieb: > Antti wrote: > > > > yes I am sure silicon samples are available, I was more refereffing to > > those > > lattice evaluation kits that are "contact lattice" those are usually > > not for sale, > > but only to lease.. this is STUPID STUPID... i have tried to purchase > > some > > lattice boards, only to get offer to lease the board. :( > > Maybe that's driven by some 3rd party SW license issue - seems a silly > idea for hardware, and it has to cost them more to admin that, than a > straight sale ? > > -jg nono I think they only get very little yield on first batch of silicon so they only make maybe 20 boards - so those are not for sale only to lease... AnttiArticle: 120560
Eric Smith wrote: > Mark McDougall wrote: >> I've actually implemented a read-only (state machine) emulation of the >> WDC-1793 in an FPGA which sources data from a serial flash device. > Cool! Have you made that publicly available? It will soon be. There's not a lot to it... >> IIUC the WDC 1793 did actually have a (purpose-built?) microprocessor. > It had a state machine. Hmmm, I'm sure I've seen _some_ disk controller datasheet that mentions an internal processor... wonder where that was... ? Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 120561
>"cutemonster" <ckh827@hotmail.com> wrote in message >news:RoGdndnLdPZkYvXb4p2dnAA@giganews.com... >> >> My question is, do I need a adaptive filter > >Nobody will tell you what you need unless you explain what you are trying to >do. What is your application? If you are measuring DC why are you sampling >at 50 MHz? > >/Mikhail > > > Hi, thanks for the reply. I'm converting a stroke signal to raster signal. There are actually 2 adc. one for x channel and the other one for y channel. Imagine like a xy graph, depends on the voltage level of each channel, it tells where to draw the pixels. So, for 10 bit, it can display 1024 x 768 resolution. The signal runs at around 10mhz. I don't know if I make my question clear enough, please let me know. I really appreciate it.Article: 120562
Once again we are producting some new development board products this time around the Spartan3A-DSP family. Given the positioning of this chip I would be interested in what you guys out there would like to see incorporated into the product, or products, in terms of features. As always we have our target set of features for the first product release but it's your chance now to influence the board specification. Replies to the news group or one one of normal emails. Please don't use the g1@ account as it goes straight to delete due to the amount of spam it attracts. We will be releasing the board name, specification and the production roll out schedule in the coming weeks. John Adair Enterpoint Ltd.Article: 120563
On Jun 10, 4:44 am, "cutemonster" <ckh...@hotmail.com> wrote: > >"cutemonster" <ckh...@hotmail.com> wrote in message > >news:RoGdndnLdPZkYvXb4p2dnAA@giganews.com... > > >> My question is, do I need a adaptive filter > > >Nobody will tell you what you need unless you explain what you are trying > to > >do. What is your application? If you are measuring DC why are you > sampling > >at 50 MHz? > > >/Mikhail > > Hi, thanks for the reply. I'm converting a stroke signal to raster signal. > There are actually 2 adc. one for x channel and the other one for y > channel. Imagine like a xy graph, depends on the voltage level of each > channel, it tells where to draw the pixels. So, for 10 bit, it can display > 1024 x 768 resolution. The signal runs at around 10mhz. I don't know if I > make my question clear enough, please let me know. I really appreciate > it. So you want to display a stroke signal on monitor? Why you need to sample the X? Is it time dimension? Is it a constant ramping, or ramping with retrace, or random?Article: 120564
>So you want to display a stroke signal on monitor? >Why you need to sample the X? Is it time dimension? Is it a constant >ramping, or ramping with retrace, or random? > > I have to sample x and y because it doesn't work like raster signal. It's voltage varies in time. There is another signal input called Unblank(TTL). It turn on and off of XY signal.Article: 120565
On 17 May, 20:35, fpgabuilder <fpgabuilder-gro...@yahoo.com> wrote: > Hi Folks, > > I need to put in DDR or DD2 interfaces. I need about 1.2GB/s > bandwidth. As I am targetting a low end fpga, I am limited by the max > bitrate on the i/o. (DDR333 or DDR2-400). > > What will be a better alternative go with DDR333 or DDR2-400? My main > considerations are - power and ability to hide the latencies during > accesses. From what I see on the usual memory vendors - > > 1. Mobile DDR available in x32 organization in one package > 2. DDR2 available in x16 but significantly lower power at IDD7. > > I would love to hear your thoughts. > > Thank you. > Best regards, > Sanjay You could be opening up a can of worms here. What about refreshing the DRAM ?Article: 120566
"Alex Gibson" <news@alxx.org> wrote: >I am after a pcie card where the ip doesn't cost an arm and a leg >unlike that for xilinx's s3 pcie starter kit > >Got quoted > $15,000 for the pcie core(End point pipe) by the local >distributor >who was trying to push us towards >Virtex-5 ML555 PCI Express Board HW-V5-ML555-G >which is overkill for what we need. > >Looking for a card that has drivers and examples for windows and linux >and includes the ipcores needed(board license is fine) > >Basically uni research project to prove a design concept (one off) >1x is fine. > >Doesn't have to be xilinx based even though that would be easier as we have >all the software.. > >Has any here used the Lattice pcie cards and cores ? > If PCIe isn't really a part of the project but just an interface, you may be better of putting a board together with a PLX bridge chip and an FPGA. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 120567
> Split the resets up yourself, before XST gets to them?
>
> Assign the main reset to a second signal, and apply that to the critical
> ones ONLY (or all within this localised block) - you may have to apply
> a KEEP attribute to the second reset signal.
>
> - Brian
I had exactly this problem with XST.
Because of the high fan out of the reset net XST is duplicating it and then
cannot pack the flops.
Add these attributes to the top level :
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of por_whatever : signal is "10000";
attribute MAX_FANOUT of por_whatever_else : signal is "10000";
I try not to use a global reset anymore, instead each module takes a
re-clocked synchronous reset and uses that on the control path where
necessary.
Don't reset something if you don't need to (data path usually) as it takes
routing resources.
Regards,
/Mike
p.s. you could use a generate loop on your instantiations to save some
typing.
something like
flops : for i in 0 to 3 generate
begin
ff_wr_addrp : fdc
port map (d => wr_addrp_d(i), c => lxclk, clr => rst, q =>
wr_addrp(i));
end generate;
you will have to change your loc constraints of course.
Article: 120568
Atom is a high-level hardware description language embedded in Haskell
that compiles conditional term rewriting systems into conventional
HDL.
New in this release:
- User guided rule scheduling to help the compiler build the optimal
scheduler.
- Rule schedule visualization with Graphviz.
gray edges: sequential composable rules
red edges: feedback arcs (bad)
blue edges: user defined scheduling constraints
- Bug fix affecting "alwayActiveWhenEnabled" performance constraint.
Enjoy!
http://www.funhdl.org/
-Tom
Article: 120569
Can someone help?
"lyra" <ss_chen@csmsc.com> 写入消息新闻:f4ai3m$5av$1@news.cn99.com...
> Hi, All,
>
> I face a program error and can not solve it. Pls you help me if you know
> how.
>
> Below is detailed info and you can see attachment for screenshot. Thank
> you.
> { chip:Stratix 2--EP2S15F484I4
> Hardware Setup: ByteBlaster[LPT1] Mode:Active Serial Programming
> error information:current programming hardware does not support Active
> Serial Programming programming mode}
>
> Best Regards
> Peter
>
>
Article: 120570Mavrick wrote: > > I would like to use Virtex5 FPGA to output 16 differential channels at 800Mbps > Don't use the Xilinx pseudo-differential LVPECL output drivers at 800 Mbps, use the LVDS current mode output drivers instead. If your external device has LVPECL inputs with sufficient common mode input range, you may be able to drive it directly from the FPGA drivers. For LVDS <-> LVPECL interfacing notes, see: http://www.onsemi.com/pub/Collateral/AN1568-D.PDF Chapter 4 of XAPP707 discusses I/O clocking in V4, not sure if there's a V5 equivalent document yet; anyone thinking of using ChipSync at 800Mbps input rates should also have a good look at XAPP707, particularly figures 2-5, 2-7, and table 3-22 BrianArticle: 120571
Alex, send me an email and I can reply with some more options. Regards, Colin Hankins "Alex Gibson" <news@alxx.org> wrote in message news:5cv3u3F32d0pvU1@mid.individual.net... >I am after a pcie card where the ip doesn't cost an arm and a leg > unlike that for xilinx's s3 pcie starter kit > > Got quoted > $15,000 for the pcie core(End point pipe) by the local > distributor > who was trying to push us towards > Virtex-5 ML555 PCI Express Board HW-V5-ML555-G > which is overkill for what we need. > > Looking for a card that has drivers and examples for windows and linux > and includes the ipcores needed(board license is fine) > > Basically uni research project to prove a design concept (one off) > 1x is fine. > > Doesn't have to be xilinx based even though that would be easier as we > have all the software.. > > Has any here used the Lattice pcie cards and cores ? > > Alex >Article: 120572
MikeJ wrote: > > flops : for i in 0 to 3 generate > begin > ff_wr_addrp : fdc > port map (d => wr_addrp_d(i), c => lxclk, clr => rst, q => > wr_addrp(i)); > end generate; > > you will have to change your loc constraints of course. > As a p.p.s: XST allows indexing into arrays of constant strings for the LOC constraints, so the LOC's can be defined up top as a constant array, then referenced by an attribute just before the 'begin' of the generate, i.e.: attribute LOC of ff_wr_addrp : label is my_loc_array(i); ( pad the strings with spaces to make them fixed length when defining the constant array ) BrianArticle: 120573
Mavrickwrote: > > I would like to know how well designed Lattice SC Pure-speed I/O > is for source synchronous application. I do not see a lot of > disccussion surrounding this but if it is truely that fast > then that is great. > I haven't designed anything with these yet, but things that I thought looked interesting in the datasheets were : - alternate input termination modes - termination to VTT - center tap termination - somewhat lower Cin on the general purpose I/O than equivalent Xilinx parts - on-chip terminations stay linear vs. input common mode voltage - controlled slew rate drivers IIRC, the I/O banking restrictions were mild, unless you need lots of 3.3V I/O: - differential inputs on all banks - 3.3V I/O restricted to top/bottom banks - 2.5V I/O on left/right banks - current mode output drivers left/right sides only ( most Xilinx parts require you to be in a 2.5V bank anyway for LVDS drivers and input terminations ) BrianArticle: 120574
MikeJ wrote: > > Also interesting is the other outputs (Address, data etc) show a much > smaller jitter increase. > My recall of QDR is a little fuzzy- do your address outputs also use the FPGA DDR output registers, or is only the clock/data done on both edges with a DDR flop? Is this all done with global clocks, or are you using regional/local clocks? If this were V2, I'd ask if you were using internal DDR clock inversion for the DDR 180 degree clock phase, or using two BUFGs to distribute clock and NOT clock. > > > - Do you have any spare LVDS input/outputs elsewhere > > on the chip ? ( handy for clock troubleshooting ) > > I have an unused bank with 2V5 IO actually so I could possibly get some > clocks in and out here. > I like to have some LVDS I/O available for these sorts of measurements; I've been thinking about plunking a vertical launch SATA connector down on my boards to provide an easy clock test I/O connector ( less space then 4 SMAs, easier to probe/drive than resistor pads ) Brian
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