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"Gerhard Hoffmann" <spamtrap@dk4xp.de> wrote in message news:1cfe63d3g6f3od2d4sbpb636e9c84f4peu@4ax.com... > > Using a different mix of caps will only produce different resonances. <snip> Absolutlely. But the anti-resonance peaks will be much lower. Done properly, the impedance peaks stay below the minimum design impedance. I look forward to checking out your data when I have a moment.Article: 120426
austin wrote: > sanju, > > Somebody is using asynchronous design? Yes, ( but not much in your FPGA world ) Take a look at : http://www.handshakesolutions.com/partners/Index.html > > Wow. I thought it died (yet again) awhile ago now. > > I think when the famous asynchronous ARM chip was built synchronously > and was better in every possible way (size: smaller, power: less, etc.), > that it effectively killed asynchronous design (again). > > I have yet to see a single case where asynchronous design has any > advantages. See above. > > In the small (phase detectors, D flip flop, clock switches, FIFO, and so > on), asynchronous design must be used (somewhere). But it is usually > done by one expert (and only that one expert is allowed to do any > asynchronous design). > > Much more popular is "Globally asynchronous, locally synchronous" or > GALS approach to design, where groups of synchronous logics communicate > with others using asynchronous handshake protocols. > > No need for any new tools. I'd agree that Async+FPGA is not a good combination (sic). That moves into areas where the FPGA vendors have not tested their tools, and it is hard enough to get the tools 'settled down' on areas the vendors supposedly DO test !! FPGAs already have large silicon resources cast for SYNC designs. Thus whilst you could, in theory, do some research projects on async, in FPGA, for final production in other ASIC flows, it would not be trivial. -jgArticle: 120427
For standalone applications the heap is initialized in sbrk.c which you can find in ppc405_0/libsrc/standalone*/src/sbrk.c You can see that heap_ptr is initialized on the first call to sbrk() and increases its value after that on every call. It maintains its value through a reset. To change the behavior you can copy sbrk.c into your own project and change it. Alternatively, there might also be a compiler option that allows you to initialize static values at run time instead of compile time. You might be able to static char *heap_ptr=0; in combination with the compiler option to get the desired behavior. - Peter sjulhes wrote: > Hi all, > > I have a SOC with a Power PC running on a Virtex II pro. > On FPGA configuration, the PPC firmware runs correctly, heap reservation on > firmware initialisation is correct. > When I reset the SOC with the reset controller, the PPC restarts correctly, > but when it tries to use the heap to initialize some dynamic variables, I > get a fail on the malloc. > > It seem that on the reset the power PC context is not reinitialized. > I guess we have to add something in the boot sequence of the PPC to reset > the heap pointer. > > I'm I right ? > It is something that must be standard in the power PC world, does someone > have an exemple how to do this ?? > > Thanks. > > Stéphane. > >Article: 120428
The problem is typically caused by reset or clocking, i.e. the processor is not in a state where it can answer to JTAG requests. For a start you can directly feed the clock into the processor (no DCM) and get rid of the reset connections to the PPC405. - Peter Pablo wrote: > Hi, I have the following problem: > > I want to configure my virtex II pro with powerpc but when I try to > download with JTAG the application doesn't run. So I have tried to use > XMD, but when I init this debug I find this message. I have asked to > Xilinx, and they have some solutions for this, but this doesn't work. > > Did anyone take this problem? > > > PD: I use ISE/EDK 8.1 > > Regards >Article: 120429
Avail ram is definitely wrong. Try to add mem=0x4000000 to the kernel boot command line and see if that gets you any further. - Peter gseegmiller@gmail.com wrote: > Anyone, > > When I try to boot linux on a Xlinx ML403 board I get the following > out put: > > loaded at: 00400000 004FA1A0 > board data at: 00000000 0000007C > relocated to: 0040405C 004040D8 > zimage at: 00404FE5 004F7A9B > avail ram: 004FB000 7C9E2378 > > Linux/PPC load: console=ttyS0,9600 ip=on root=/dev/xsysace2 rw > Uncompressing Linux...done. > Now booting the kernel > > Does the 'board data at' arguments look ok. Any help would be > appriated!!! >Article: 120430
Patrick Dubois wrote: > On 28 mai, 00:35, Ken Ryan <newsr...@leesburg-geeks.org> wrote: >> Thanks, you encouraged me to try that tack again. :-) >> >> I commented out the bogus sleep() definition, and I had to drop >> a "#define LWIP_TIMEVAL_PRIVATE 0" to keep lwip away from struct >> timeval. >> >> Next, to figure out why the Xilinx gdb quit giving me symbols... >> (yes I have -g -O0 in both the app and libraries...) >> >> ken > > Thank you guys for sharing your experiences. I had the same problem > and commented out this line in sleep.h. > //void sleep(unsigned int seconds); > Is it the line you were talking about? Yes, that's it. > > I'm not sure where to do the fix however... Doing any modification to > the EDK source tree is not portable accross computers. Doing the > modification in the ppc405_0 folder will be lost during the next > library rebuild. Is there a better way? Yes, that;s a problem. I haven't figured out a better way. As a stopgap I added that sleep.h to the list of include files for my application, as a reminder. Doesn't help for a command-line build though. I'm seeking out another solution for the whole mess anyway. Evidently the xilinx-provided libc is only thread-safe for some functions, and they don't seem to have a list of which ones. So it's either wrap all the standard C library functions in mutexes or do my own libc port. Xilinx should be ashamed of themselves, but after the xilnet disaster I doubt they are. > > Another question while I'm at it, did you fix the problem about debug > symbols? It indeed seems broken in EDK v9.1, even after 2 service > packs. Note sure I came across this one (or at least I don't recognize it)... kenArticle: 120431
antoine.vernay@gmail.com wrote: > Hi, > > I'd like to get some help from experienced people because I'm really > running low on ideas here.. I'm a beginner in FPGA/LwIP and I can't > seem to make it work using Xilinx EDK 8.2i. > > I've been creating a project using BSB including onewire, uart, emac > and the external memory and using PPC. > Once I am in the project manager, I did all of the required > modifications to boot up on the bram and execute the code from the > external memory, set up the -llwip4, checked the lwip 2.00a and set up > the MAC address. > Once i compile, it works fine, initializing a server code I took as an > example and printfs display everything is fine but it is impossible to > connect to the card or even ping it. > > Could someone give me a hint about what I m doing wrong? Just a few "silly" questions: Did you go through the section of lwip documentation talking about configuring xilkernel? Did you also include -lxilkernel? I assume you're appropriately setting IP address and mask? Did you try building the example design in the lwip page on the xilinx website (there are several, pick the one closest to your hardware)? Did you try turning on the verbose debugging switched in the lwip and xilkernel driver configs? I'm sure none of those are news, but sometimes I find I missed something basic... kenArticle: 120432
On Jun 6, 6:43 pm, Test01 <cpan...@yahoo.com> wrote: > It seems that bufio has the lowest clock skew in order to clock the oserdes. OSERDES in my configuration requires two clocks 1x clk and 2x clock. I would like to know how many OSERDES can I drive using one BUFIO. I would like to bring in limited number of clocks inside the part and avoid using bufg has it has 270 ps of clock skew as opposed to 50 ps of clock skew for bufio. > > Thanks. It depends on a few things (bonded or bonded I/Os, bottom or top of the device, etc). In general, For V4, each BUFIO can reach 3 clock regions and each clock region has 32 I/Os. For V5, each BUFIO can only reach 1 clock region each clock region has 40 I/Os. You can use ADEPT (http://home.comcast.net/~jimwu88/tools/adept/) to see dynamically how many I/Os a clock capable pin (CC) (which directly drives BUFIO) can reach. Cheers, JimArticle: 120433
On Jun 5, 4:02 pm, John Williams <jwilli...@itee.uq.edu.au> wrote: > Hi Shant, > > Shant wrote: > > My basic version of design has two interconnected microblaze, FSL has > > been used for interconnection. > > There is one application on each microblaze such that frist writes to > > second then the second microblaze sends some data back to the first > > one. > > Sounds reasonable. > > > My problem is that while performing Build all user application, it > > builds the application present in first microblaze but throws errror > > while building the application in second microblaze. > > Details of the error message would be helpful! > > John Hey John, Thanks for the reply... The problem has been figured out. It was because both the microblazes were using the same Uartlite for their printf function. After removing the printf from the second microblaze, the build process does not error out. Thanks again. ShantArticle: 120434
On Tue, 05 Jun 2007 21:25:46 -0700, Jonathan Bromley <jonathan.bromley@MYCOMPANY.com> wrote: >On Wed, 06 Jun 2007 04:07:14 -0000, >VIPS <thevipulsinha@gmail.com> wrote: >>We have been knowing the false path and its nature but i am confused >>as to how to identify a false path in a design having say 100 modules. >FishTail, an interesting new tool that uses formal techniques >to identify false and multi-cycle paths.... >http://www.fishtail-da.com/ I should also have mentioned Blue Pearl's products... http://www.bluepearlsoftware.com/ I talked with some of the Blue Pearl guys at DAC today and they assured me their tools can find false paths that cross design hierarchy boundaries in designs up to at least a million gates. I haven't yet had a chance to try out for myself this interesting application of formal technology. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 120435
Finally I configure dcm with a C_DFS_FREQUENCY_MODE to HIGH and Reset Polarity to High. Now it seems to work fine.Although I have though to get rid of the reset signals and to configure PowerPC with the clock directly. RegardsArticle: 120436
I have been trying to find the time to start a project with an FPGA for a while and I think I've finally found one. I've messed around with my Digilent FPGA development board but I have never created a full featured standalone application. I want to take a modern FDC I/O controller and connect it to my Altair with an 8080 processor. I understand the S-100 connections and the operation/connections of the FDC controller. The thing I need advice on is the FPGA in the middle. I have not completed my research, but I don't think the 8080 is fast enough to keep up with a 1.4MB disk. This is one reason I would need the FPGA, to buffer one sector of data and then handle transmission to the FDC IC. Another reason I will need an intermediate device (the FDC is 8 bit) is because I want the controller to be compatible with all MITS software. To do this I will need to emulate the simple MITS hard sector disk controller. Understanding the controller is not a problem for me. We have 77 tracks of 32 sectors of 136 bytes (or 138, can't remember off hand). I want to use the disk drive's 80x36x512 and just insert nulls to fill up the unused parts of the sectors. This way the disks can be read/written with a PC. I currently have the Altair booting CP/M off of a 3.5" disk connected to a vintage tarbell board, but its 70k formatted capacity isn't exactly standard (controller thinks its a SS SD 5.25"). ; ) I imagine the best way to handle this is to have an FPGA like the XC3S100E with some VHDL and a micro core??? I want the FPGA to be TQFP at the most for easy at home soldering. I imagine the micro core would handle initializing and error checking of floppy disk operations. The FPGA or possibly the FPGA and micro would emulate the "fake" disk I/O status bits. What would the suggested core be for a project like this? If I have a 100,000 gate FPGA running with a 50MHz oscillator, how fast should an average risc core run? I'm trying to figure out what kind of performance I could get out of an FPGA. After describing the project I'm wondering if it would be better to use a hardware micro and a CPLD??? Any tips or pointers to get me start would be appreciated. : ) Thanks, GrantArticle: 120437
"Gerhard Hoffmann" <spamtrap@dk4xp.de> wrote in message
news:1cfe63d3g6f3od2d4sbpb636e9c84f4peu@4ax.com...
> On Wed, 06 Jun 2007 07:35:13 -0700, austin <austin@xilinx.com> wrote:
>
>>The extra pins to ground isn't go to do anything for him (use of IOs as
>>ground), as he is already in an excellent package in V4, and we are
>>looking at his bypassing solution. He used all one value for Vcco
>>bypass, 0402 1.0uF, and I am working on showing him that there can be
>>anti-resonant peaks (right around 200 MHz), where the use of all one
>>value is a bad choice.
>
> Using a different mix of caps will only produce different resonances.
>
> I recently had some time to wait for while (1) { XST; translate; map;
> place & route }
> and used it to play with capacitors.
>
> 6.8 Mb pdf of capacitors on a stripline: pictures and impedance plots,
> still bound to grow.
>
>
> <http://www.hoffmann-hochfrequenz.de/downloads/experiments_with_decoupling_capacitors.pdf>
>
>
> (hi, Peter, see you at the Berlin XFest!)
>
> regards, Gerhard
>
Hi Gerhard,
Thanks for posting that. A very interesting series of experiments. They show
how both form factor and layout are important.
I wonder if you saw the thread back in March about X2Y caps? Subject,
"Bypass caps, X2Y and 'puddles'". You may like to check it out, there are
links to some similar experiments there also.
FWIW, I think all this different value caps thing is bunkum. Especially if
they're in the same sized package. Unless someone does a detailed 3-D
analysis _INCLUDING_ the bond wire, the BGA pacakge traces and the BGA
balls, I won't be convinced by 'resonance' bluster. OTOH, the X2Y stuff has
me convinced that I should think even harder about bypass networks in my
next design.
Thanks, Syms.
p.s. I guess it would be fairly straightforward for Mike (the OP) to change
some values in his bypass network and see how it affects jitter. That'd be
interesting.
Article: 120438"MikeJ" <mikej@fpgaarcade.nospam.com> wrote in message news:U4v9i.1466$ZA.983@newsb.telia.net... > There is a single VCCIO 2V5 bank on the device but it is totally unused. > My thoughts on the regulator were to isolate the VCCAUX from possible > noise elsewhere on the board. > (I remember linear regs were recommended on the SerDes 2v5 supplies on > Virtex2pro) > Yeah, I saw that too. I think a passive filter will perform better than the suggested circuit above a few hundred kHz. The linear regulator solution runs out of bandwidth. HTH, Syms.Article: 120439
On Thu, 7 Jun 2007 09:55:39 +0100, "Symon" <symon_brewer@hotmail.com> wrote: >I wonder if you saw the thread back in March about X2Y caps? Subject, >"Bypass caps, X2Y and 'puddles'". You may like to check it out, there are >links to some similar experiments there also. That file will grow, I'll test X2Y when I get my next board fabricated. On 1.5 mm epoxy they would probably be pearls before swine. GerhardArticle: 120440
"Gerhard Hoffmann" <spamtrap@dk4xp.de> wrote in message news:p6kf631domu4c150668pg2aggeutjdq58o@4ax.com... > On Thu, 7 Jun 2007 09:55:39 +0100, "Symon" <symon_brewer@hotmail.com> > wrote: > >>I wonder if you saw the thread back in March about X2Y caps? Subject, >>"Bypass caps, X2Y and 'puddles'". You may like to check it out, there are >>links to some similar experiments there also. > > That file will grow, I'll test X2Y when I get my next board fabricated. > On 1.5 mm epoxy they would probably be pearls before swine. > > Gerhard That should suit most of us on this newsgroup then... :-) I'm looking forward to seeing your results! Thanks, Syms.Article: 120441
what is the error in the following code. in it the main module is
"test". in that module's "always" block another module "counter" is
called. but it shows error. how can i solve the problem? how can i
call another module in always block?
module counter(clock, reset, count);
input clock, reset;
output [3:0] count;
reg [3:0] next_count,count;
always@*
begin
if(count<15)
next_count=count+4'd1;
else
next_count=count;
end
always@(posedge clock)
begin
if(reset)
count<=4'd0;
else
count<=next_count;
end
endmodule
module test(clock,reset,count);
input clock, reset;
output [3:0] count;
reg [3:0] count;
always @(clock)
counter(clock, reset, count);
endmodule
Article: 120442Hi, I have seen about configuring the JTAG as UART since I have not RS232 port in my board. I have found that Xilinx provides OPB_MDM as uart with C_USE_UART PARAMETER, but in my desing I use PowerPC. In powerPC the debug is done by jtag_cntlr and not by opb_mdm so console says that "opb_mdm_0 is not accessible from processor ppc405_0". Has anyone configured JTAG as UART in PowerPC? RegardsArticle: 120443
"ARH" <haghdoost@gmail.com> wrote in message news:1181149333.018129.33940@q69g2000hsb.googlegroups.com... > On Jun 6, 11:32 am, han...@ht-lab.com wrote: >> As I mentioned above, what is lacking is software support but >> converting the processor to Verilog or finishing off Antti's one would >> also be an interesting exercise. The other area which would be >> interesting is taking the processor and building a proper verification >> environment around it using SystemC, PSL and Mentor's AVM. But this >> requires expensive tools like Questa.... > > Hans, > > Thank you for contribution suggestions. > > I want to work on a project that have some thing new to develop and > document it in some internal or international conferences, when I see > CPU86 project an initiative idea take place in my mind to contribute > with you to develop various aspect of it specially in the system level > description. > > But when you say that x86 soft IP core have no main advantage versus > other useful CPU IP-core , I think that there are no thing new in this > work and after all no one interest it. Hi Arh, I should have been more precise, there is no commercial advantage. Anybody who needs an embedded soft processor is better off with one of the many fully supported commercial offerings. I played with the Nios-I core and was quite impressed that I could get a simple application (Faile chess engine) up and running with a minimum amount of hassle. This is important for commercial applications but less fun for a hobbyist :-) > > What is your idea about it? Are there any rooms in HT-Lab projects > that have a valuable academic tent? Instead of worrying about the academic novelty of your project I would simply select a project that you are most interested in, this will motivate you and hence increases your chance of getting a high mark. If you really want an academic subject than pick an area (imaging/processor/comms/dsp/space/embedded/formal/soc etc) and then google to see what research is going on. Then contact the university/company to see if you can contribute/collaborate. You seem to be interested in SoC development so why not pick a number of open/free cores and build yourself a full system. You will discover that putting all the blocks together is easily done but verification becomes a nightmare :-) Good luck with your project, Regards, Hans. > > Of course I am a novice student in hardware engineering and I can't > judge about the academic value of project. > > Best regards > --ARH > > >Article: 120444
Hans posted in news:Ybj9i.4930$sM1.2868@newsfe4-win.ntli.net :
"[..]
Using SystemC for your project is a great suggestion since [..]
you can really put your teeth into issue like [..]
concurrency [..]
[..]"
In news:1181080157.909291.81940@p47g2000hsd.googlegroups.com
timestamped Tue, 05 Jun 2007 14:49:17 -0700, ARH <haghdoost@gmail.com>
posted:
"Hans,
Thank you very much for your useful explanations.
I agree with you about systemC abilities [..]
[..]"
In news:1181134884.494511.240490@k79g2000hse.googlegroups.com
timestamped Wed, 06 Jun 2007 06:01:24 -0700, hans64@ht-lab.com posted:
"On Jun 6, 9:17 am, Colin Paul Gloster <Colin_Paul_Glos...@ACM.org>
wrote:
> Hans posted innews:Ybj9i.4930$sM1.2868@newsfe4-win.ntli.net:
..snip..
> Then perhaps you are in trouble because you have not noticed yet that
> the SystemC(R) standard is actually explicitly written in a way which
> does not use concurrency.
Why is he in trouble?
Are you hinting to the fact that thread synchronisation by events is
not ideal and can lead to deadlocks and race conditions if you are not
careful?"
No. Hans said something about the SystemC(R) library and concurrency;
after that, ARH agreed with Hans about SystemC(R) abilities; and after
that C.P.G. pointed out that concurrency is not part of the SystemC(R)
standard. It is very clearly written in Section 4.2.1 The scheduling
algorithm:
"[..]
4.2.1.2 Evaluation phase
[..]
Since process instances execute without interruption, only a single
process instance can be running at any
one time, and no other process instance can execute until the
currently executing process instance has
yielded control to the kernel. A process shall not pre-empt or
interrupt the execution of another process. This
is known as co-routine semantics or co-operative multitasking.
[..]"
In news:1181134884.494511.240490@k79g2000hse.googlegroups.com
timestamped Wed, 06 Jun 2007 06:01:24 -0700, hans64@ht-lab.com posted:
"[..] However, lets be realistic, a lot of big companies
like ARM and ST use SystemC for their models, do you think they would
spend all this effort on a language that is flawed in terms of
concurrency support?"
Yes. I could tell you about an unscalable slow SystemC(R) model none
of whose parts run concurrently for a major European Union research
project (whose name ironically enough is Scalable software Hardware
Architecture Platform for Embedded Systems) developed by one of the
two companies you explicitly mentioned. The time limit in the
nondisclosure agreement has not expired yet.
"I am no expert (not even a novice) so perhaps one of the Doulos guys
can shed some light on this?
[..]"
They tend to answer SystemC(R) questions very well on one of the
discussion forums on WWW.SystemC.org .
Article: 120445On 7 Jun, 11:14, "nasif4...@gmail.com" <nasif4...@gmail.com> wrote: > how can i > call another module in always block? You can't. Try: module test(clock,reset,count); input clock, reset; output [3:0] count; wire [3:0] count; counter counter_inst(clock, reset, count); endmoduleArticle: 120446
Check out Balsa HDL for async design http://intranet.cs.man.ac.uk/apt/ also Async FPGA, hardware is async http://vlsi.cornell.edu/fpga.php http://www.achronix.com/ Google "async digital circuits" find other Universities doing similar research http://www.async.elen.utah.edu/book/ Agree with the other previous post. Current FPGAs not suited for async, global clock trees already exist, might as well use them. You will utilize more logic elments to implement the async logic. If your goal is to save power you may save power (correct dynamic power should be lower) but it will be at the cost of more logic usage, issues verifying timing (depending what async architecture you use), PAR (tools may not understand it is async?). Paper on using current FPGA tool flow for async http://www.ics.forth.gr/carv/papers/PID255199.pdf If the goal is to learn async circuit design, you can implement async in standard Verilog or VHDL and/or try Balsa. Couple free books online on the subject as well. Good luck and lets us know how it goes.Article: 120447
On 7 jun, 12:45, Pablo <pbantu...@gmail.com> wrote: > Hi, I have seen about configuring the JTAG as UART since I have not > RS232 port in my board. I have found that Xilinx provides OPB_MDM as > uart with C_USE_UART PARAMETER, but in my desing I use PowerPC. In > powerPC the debug is done by jtag_cntlr and not by opb_mdm so console > says that "opb_mdm_0 is not accessible from processor ppc405_0". > > Has anyone configured JTAG as UART in PowerPC? > > Regards Solved.Article: 120448
On Jun 6, 10:08 pm, Ken Ryan <newsr...@leesburg-geeks.org> wrote: > Xilinx should be ashamed of themselves, but after the xilnet > disaster I doubt they are. The software side of EDK is really disappointing to say the least. I sold the idea around here to use the Avnet FX12 mini-module as a nice solution to ethernet connectivity. I thought that there would be lots of working examples for it (as ethernet seems to be its biggest selling point). Wrong. The Avnet ethernet examples all use lwIP in sockets mode and as we seem to discover, not everything is xilkernel friendly. Not only that, the ethernet examples using MPCM2 are not compatible with flash booting in EDK v9.1 (not an essential feature it seems?!). Gigabit reference design? It's using an expensive tcp/ip stack, so it's not very useful for most people. It's very hard for me to explain to my boss why such a simple application (SPI-ethernet bridge) is taking forever to complete. I thought that the mini-module would be a nice integrated solution (as far as ethernet is concerned) like the Rabbit microcontroller is. Boy was I wrong on this one. I'm starting to think that trying to make lwIP work in raw mode instead (despite the lack of driver support for the temac!) might be easier than dealing with all the xilkernel related issues. Or maybe I could go back to EDK v7.1 (!), Avnet has a reference design with lwIP v1.0 working in raw mode for that version... But what if I get a bug in the design, I'll probably be told by Xilinx to upgrade to v9.1. Virtex-4 was released what, 2 years ago now? Come on software folks at Xilinx, it's about time to get a working tcp/ip solution (free) to use the hard temac without having to bother with xilkernel!! Is that too much to ask? PatrickArticle: 120449
On Jun 7, 8:10 am, Pablo <pbantu...@gmail.com> wrote: > On 7 jun, 12:45, Pablo <pbantu...@gmail.com> wrote: > > > Hi, I have seen about configuring the JTAG as UART since I have not > > RS232 port in my board. I have found that Xilinx provides OPB_MDM as > > uart with C_USE_UART PARAMETER, but in my desing I use PowerPC. In > > powerPC the debug is done by jtag_cntlr and not by opb_mdm so console > > says that "opb_mdm_0 is not accessible from processor ppc405_0". > > > Has anyone configured JTAG as UART in PowerPC? > > > Regards > > Solved. Would you mind sharing the solution? I'd like to know how to use JTAG as UART in my design as well.
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