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>On Jun 14, 11:17 am, "cutemonster" <ckh...@hotmail.com> wrote: > >> Yes, I tried synchronous and asynchronously to Unblank signal. There are >> two problems. The first one is the noise itself with the stroke signal >> and the second one is the stroke signal being drawn at the second time >> doesn't being drawn at the exact position. It's like one pixel toggling >> between frames. >> >> Do you know which kind of filter fit the best in this situation? >> >> thanks for you suggestion- Hide quoted text - >> >> - Show quoted text - > >Sounds like you capture it as live video or multiple frames. In such >case you would need to synchronize or lock the clock to a reference, >the unblank may be? Having no idea what the unblank looks like so I >can't tell how to do it, how often does the unblank recycling? > >Having a good synchronized clock with low jitter is, IMHO, much easier >than doing the filter to minimize the artifact of pixels toggling >positions between frames > >For the spatial noise, If I was you I would try a high order analog >filter infront of the A2D first, before doing any digital filtering > >Regards, > > > > thanks for the suggestion. For analog filtering, all I can do now is putting a circuit in breadboard. The problem is that it's a couple inches away from ADC. For digital filtering, are they all very similar? I mean, there are many type of digital filtering and I'm confused which one I should use. Are they specifically work for certain application? thanks,Article: 120726
Hi, For those who are familiar with Lattice/LatticeSC, what is LatticeSC implementation of Virtex-4 ISERDES and OSERDES (see Xilinx Application Note - xapp721) -youngArticle: 120727
rickman wrote: > Joerg wrote: > >>That can backfire, big time. Many vendors think that only large >>companies matter and fail to see that it's often the little guys like us >>consultant who really call the shots. Meaning their (big) client's >>engineers trust their decision and stick with it. I've had sales guys >>literally beg me to reconsider but in pretty much all cases it was too >>late. When the work is done a consultant cannot saddle a client with >>more NRE just because a vendor shows remorse about not having supported >>what they thought was "only a little guy". >> >>A lot of companies, including nearly all European semi mfgs, don't even >>know what they have missed out on so far. Never will. > > > And if they don't know what they have missed out on, why would you > expect them to take these missed opportunities into account??? They > can only work with the info they have. > They do not listen. I've tried numerous times, then went on to their competitors and never really looked back. Listening is an important skill but it seems that it is not taught in marketing school. Ok, ok, on the other hand I liked my first contact with marketing so much that we are still married ;-) > That is why it is important for you to explain to the vendors what the > potential of a given product is. I have been in this position > before. Not only did I get samples, when I had some issues I got very > good support (partly to cover some mistakes on the part of the vendor) > and I was given very good pricing all things considered. > > So communicate with your distis and reps. Don't treat them like the > enemy, treat them as what they are, a business partner. > I would like to do that. However, most of them are still encrusted in the regional thinking of yesteryear. That was ok 50 years ago but now an engineer will not even know where something will be produced. Heck, even my clients sometimes don't because that is subject to an international bidding process. Could be China, could be Malaysia, who knows? I certainly don't. So what should I respond to the first question the disti fires at me: How many will be used per year and where will it be produced? Out of principle I do not lie. So what happens then? They remain polite but promised answers to questions never materialize, etc. Then we just move on to companies that provide efficient and direct support. National, TI, AD, and so on. The design-in rate for the others is approaching zero. -- Regards, Joerg http://www.analogconsultants.comArticle: 120728
> Then we just move on to companies that > provide efficient and direct support. National, TI, AD, and so on. If half of the companies were half as good to deal with as those you listed are.... It is nice to dream sometimes :-). Dimiter On Jun 15, 3:25 am, Joerg <notthisjoerg...@removethispacbell.net> wrote: > rickman wrote: > > Joerg wrote: > > >>That can backfire, big time. Many vendors think that only large > >>companies matter and fail to see that it's often the little guys like us > >>consultant who really call the shots. Meaning their (big) client's > >>engineers trust their decision and stick with it. I've had sales guys > >>literally beg me to reconsider but in pretty much all cases it was too > >>late. When the work is done a consultant cannot saddle a client with > >>more NRE just because a vendor shows remorse about not having supported > >>what they thought was "only a little guy". > > >>A lot of companies, including nearly all European semi mfgs, don't even > >>know what they have missed out on so far. Never will. > > > And if they don't know what they have missed out on, why would you > > expect them to take these missed opportunities into account??? They > > can only work with the info they have. > > They do not listen. I've tried numerous times, then went on to their > competitors and never really looked back. Listening is an important > skill but it seems that it is not taught in marketing school. Ok, ok, on > the other hand I liked my first contact with marketing so much that we > are still married ;-) > > > That is why it is important for you to explain to the vendors what the > > potential of a given product is. I have been in this position > > before. Not only did I get samples, when I had some issues I got very > > good support (partly to cover some mistakes on the part of the vendor) > > and I was given very good pricing all things considered. > > > So communicate with your distis and reps. Don't treat them like the > > enemy, treat them as what they are, a business partner. > > I would like to do that. However, most of them are still encrusted in > the regional thinking of yesteryear. That was ok 50 years ago but now an > engineer will not even know where something will be produced. Heck, even > my clients sometimes don't because that is subject to an international > bidding process. Could be China, could be Malaysia, who knows? I > certainly don't. So what should I respond to the first question the > disti fires at me: How many will be used per year and where will it be > produced? Out of principle I do not lie. > > So what happens then? They remain polite but promised answers to > questions never materialize, etc. Then we just move on to companies that > provide efficient and direct support. National, TI, AD, and so on. The > design-in rate for the others is approaching zero. > > -- > Regards, Joerg > > http://www.analogconsultants.comArticle: 120729
cs_posting@hotmail.com wrote: > No meaning to personally target you here, but can I ask a general > question: what is up with the recent flood of people apparently having > no background embedded programming experience playing with soft core > FPGA processors? Because it's so cheap and easy? Phase 1. $600 for EDK + a decent Spartan3 board, plus free webpack tools Phase 2. ???? Phase 3. Profit!Article: 120730
On Jun 14, 8:37 pm, John Williams <jwilli...@itee.uq.edu.au> wrote: > cs_post...@hotmail.com wrote: > > No meaning to personally target you here, but can I ask a general > > question: what is up with the recent flood of people apparently having > > no background embedded programming experience playing with soft core > > FPGA processors? > > Because it's so cheap and easy? > > Phase 1. $600 for EDK + a decent Spartan3 board, plus free webpack tools > Phase 2. ???? > Phase 3. Profit! That ain't cheap. Cheap is doing it with the $100 s3kit, coding up a processor described in MIT open courseware web notes, simulating it in iverilog, hacking the gcc-cross target until it builds under cygwin *and* produces working code... rewriting an assembler...Article: 120731
Just curious, but was the error concerning the "outbyte" function for the 2nd processor? If this is the case, I have found a work-around. Just copy the / libsrc directory from the first processor's directory to the 2nd processors. Everything should work out OK.Article: 120732
Dear all, I am a graduate student at USF. I am working with XILINX XUPV2P board and i am using edk to interface memory and my RTL code (using import peripheral). the RTL code synthesizes at 70 Mhz and EDK ddr memory access works in 100 Mhz. However when i connect RTL to EDK using import peripheral, the design only passes implementation, place and route in 1 MHz, it fails to implement even in 25 Mhz. my application requires ddr memory access and data transfer from edk to rtl and so on. i really appreciate all ur suggestions. thanks for all ur help. sincerely, MahalingamArticle: 120733
I am trying to boot the PPC with a minimum of block ram, since I want to save that for my own hardware peripherals. My idea is to take the smallest amount of on chip memory (4K of isocm seems to be the minimum - why not 2K I wonder) and hold a small assembly language program that will copy my real program from external flash into DDR space, initialize the data sections and go. All the boot examples I have seen seem to use xil_kernel and take up an obscene amount of on chip memory. Does anyone know of a better way? I looked at the ultra-controller design that runs only from cache, but it seems the only way to load the cache is with XMD which is no good for stand-alone embedded booting. thanks, JeffArticle: 120734
I am trying to make a 4 Kbyte program to go in isocm at the top of PPC address space. It seems to build OK. But when I try to update the bitstream before downloading I get the somewhat cryptic error "ERROR:MDT - Memory overlap detected between various program headers for processor ppc405_0". This occurs when it is "Analyzing file bootloops/pc405_0.elf". Does anyone have a clue what I might be doing wrong, in particular how to make it stop trying to use the bootloops mechanism. thanks, JeffArticle: 120735
On 2007-06-15, Jeff Cunningham <jcc@sover.net> wrote:
> I am trying to boot the PPC with a minimum of block ram, ...
> will copy my real program from external flash into DDR space, initialize
> the data sections and go.
The ppc is going to start at 0xfffffffc. What you boot from depends
on what you place at that memory location. You should be able to boot
from flash, provided it's visible from your instruction PLB bus. All
you need to do it point the stack somewhere into DDR and then you can
write the rest in C, provided you avoid global data:
boot()
{
back:
/* assuming your DDR starts at 0, a small stack */
__asm ("li 1,1024");
yourfunc();
/* put this function at the end of your file and this will be the
* last instruction, which will go at 0xfffffffc and run first!
*/
goto back;
}
Just put that at the end of your file, compile it to a .o, then use
`objcopy -O binary boot.o boot'. Then pad the file `boot' so that you
can flash it at the end of your flash space. If you start getting
fancy you'll eventually need a custom link script and more magic to
relocate the code, but if you just zero some memory and copy some
stuff around before jumping into it, you'll be fine.
--
Ben Jackson AD7GD
<ben@ben.com>
http://www.ben.com/
Article: 120736Jeff Cunningham schrieb: > I am trying to make a 4 Kbyte program to go in isocm at the top of PPC > address space. It seems to build OK. But when I try to update the > bitstream before downloading I get the somewhat cryptic error "ERROR:MDT > - Memory overlap detected between various program headers for processor > ppc405_0". That means there are two binaries that should be loaded to the same address. If you have only one application the most common error is to not disable the default bootloop which seems to be the case here: > This occurs when it is "Analyzing file > bootloops/pc405_0.elf". Does anyone have a clue what I might be doing > wrong, in particular how to make it stop trying to use the bootloops > mechanism. Do you have disabled the "Mark to initialize BRAMs"-Option for the ppc405_bootloop? The icon next to ppc405_bootloop on the "Applications" tab should contain a small red x. You can adjust the setting by right clicking on the bootloop entry. AndreasArticle: 120737
> That ain't cheap. Cheap is doing it with the $100 s3kit, coding up a > processor described in MIT open courseware web notes, simulating it in > iverilog, hacking the gcc-cross target until it builds under cygwin > *and* produces working code... rewriting an assembler... That is exactly what i keep saying around the net! Cheap is writing down the MIT Beta (that's the one you refer to if i'm right), simulating it in iverilog (or GHDL since i use VHDL only) and working on the toolchain. Still we don't have an open-source implementation tool (or at least for the synthesis part). "Signs" is progressing but i don't think it supports any real architectures. Most soft cores out there are wildly unoptimized. This is where Xilinx did a good job with both MicroBlaze and Picoblaze. And of course i would prefer a soft core written in general VHDL (i.e. not for a specific vendor). I think the compromise would be rather small, given that internal RAM storage and multiplier(s) will be inferred from the general HDL code. Nikolaos KavvadiasArticle: 120738
Frank Buss <fb@frank-buss.de> wrote in news:1ki61sjualhfi.xxscjrzdk91a$.dlg@40tude.net: > While trying to minimize my microcode implementation to implement a > small 6502 CPU, eventually I designed a new Forth CPU: > > http://www.frank-buss.de/vhdl/forth-cpu2.html > > I would like to have a full Forth system for it, which could run at > about 4 MIPS with a 50 MHz clock on a FPGA with internal block RAM. > This could be at least doubled with some more thinking about the RAM > interface. With this system I can implement a 6502 CPU emulation :-) > > But first I would like to hear some comments. What do you think about > the instruction set architecture (ISA)? Any ideas how to modify the > VHDL code (see bottom of the page) or the ISA to use less LEs, but > without impact on the compactness of code for the CPU? > > At the bottom of the page you can find a full Quartus 7.1 project for > testing it. Looks like adjusting some settings can increase or decrase > the number of LEs by 20% and more. E.g. when changing "Auto RAM > replacement" to "On" in "More Settings" in "Analysis & Synthesis > Settings" increases the LE count from 590 to 697 LEs, which is > strange, because I would expect that replacing registers and logic > with RAM should save LEs, and if not, the compiler should not use it. > > When the design is finished, I want to implement an assembler for the > system in Forth. How could the mnemonics look like and are there any > good examples of assemblers in Forth, which could be used to implement > my ISA? For testing, an emulator would be nice, too, but this should > be easy to implement, because of the simple and orthogonal ISA. Simulate first. jrhArticle: 120739
On 14 jun, 23:25, "MM" <m...@yahoo.com> wrote: > > Respect to the project you send me, I cannot see the vhdl code related > > to the ddr control. Where do I look for?. > > When you design with EDK you don't normally need to go down to VHDL or > Verilog code unless you are designing your own cores. In the case of the > design I mentioned, all of the cores are from the Xilinx EDK library (the > PLB_DDR core is for sure from the EDK library), so there isn't really any > need to look for the code. To see how the cores are connected take a look at > the system.mhs file. > > /Mikhail What about the phase difference?. I suppose that there is a little skew resolve by the feedback, but it seems that internal feedback clock is the same of the proccesor?. Regards againArticle: 120740
Just had a look at some of the Xilinx development boards e.g. ML405 and they seem to have Vcco_0 connected to 3.3V but have the pullups on done, init_b connected to 2.5V. Is it possible to have them pulled up to 3.3V instead? The documentation seems a bit vague about what supply you need to use. JonArticle: 120741
Andreas Hofmann wrote: > Do you have disabled the "Mark to initialize BRAMs"-Option for the > ppc405_bootloop? The icon next to ppc405_bootloop on the "Applications" > tab should contain a small red x. You can adjust the setting by right > clicking on the bootloop entry. Thanks, Andreas - I didn't notice the bootloop "application" in the little window (not in bold type like the other apps). I disabled that, and now when I try to update the bitstream, the first time Data2mem runs, it crashes. If I run it again, it says nothing needs to be done. But when I then go to download the bitstream, it says the bitstream is empty. I guess I will need to open a webcase on this unless anyone has any better ideas. -JeffArticle: 120742
On Jun 15, 3:15 am, Uncle Noah <n...@skiathos.physics.auth.gr> wrote: > Cheap is writing down the MIT Beta (that's the one you refer to if i'm > right), simulating it in iverilog (or GHDL since i use VHDL only) and > working on the toolchain. Yes, that's it. > Most soft cores out there are wildly unoptimized. This is where Xilinx > did a good job with both MicroBlaze and Picoblaze. Yeah, Beta's 32x32bit register file ended up as lutram... not exactly efficient. The old two read ports and one write port problem... Also, the 32 bit instruction words are fairly wasteful of BRAM code space. And if you aren't going to pipeline, a RISC design isn't necessarily such a great idea. But still, it worked, and it ran in an XC3S200... There are some more FPGA-appropriate open architectures out there I think, even some open source microblaze workalikes.Article: 120743
Ben Jackson wrote: > On 2007-06-15, Jeff Cunningham <jcc@sover.net> wrote: >> I am trying to boot the PPC with a minimum of block ram, ... >> will copy my real program from external flash into DDR space, initialize >> the data sections and go. > > The ppc is going to start at 0xfffffffc. What you boot from depends > on what you place at that memory location. You should be able to boot > from flash, provided it's visible from your instruction PLB bus... Thanks for replying Ben. In my case I'm trying to save fabric by not having any PLB-OPB-flash path (I didn't see any direct PLB to flash IP, and I'm leery of making my own PLB slave). So the flash is not memory mapped. Instead, I made a DCR peripheral that can do simple programmed-register type access of the flash. So my tiny assembly language boot program would use this peripheral to read the flash and fill the ddr. I guess the choice is to either make a PLB slave that can access the flash, or sacrifice two brams. A nice thing about the DCR reading of the flash is that I can also do a CRC check of the data to make sure it is not corrupted before trying to run it. So I can have my normal application code, which can be updated by the user, plus a backup copy to fall back on if the primary application code gets corrupted during user updating, and have this all happen automatically during bootup. -JeffArticle: 120744
"Pablo" <pbantunez@gmail.com> wrote in message news:1181903383.310304.114860@q75g2000hsh.googlegroups.com... > > What about the phase difference?. I suppose that there is a little > skew resolve by the feedback, but it seems that internal feedback > clock is the same of the proccesor?. Exactly, the purpose of the feedback must be to compensate for the skew, however it is probably small enough on this particular board that it can be ignored. /MikhailArticle: 120745
Hi, I'm new to FPGA world and currently working on an emulation board with 2 Virtex-5. I think to forward clock from chip A to chip B. Is that possible to make these 2 clocks synchronous ? What kind of steps, components and constraints need to be done to ensure the synchronous between these 2 FPGAs. The clock frequency is about 50-100 MHz range. My current scheme is as following, but doesn't work properly. Any help is appreciated. On FPGA A, 1. A clock, APP_CLK (200 MHz), comes out of a DCM, which is used to mange the receiving clock from off-chip DDR2 DIMM. 2. APP_CLK drives another DCM for clock synthesis of 100 MHz and 50 MHz. The feedback of this DCM is from the output of DCM itself, which may be an issue. 3. Takes the 100 MHz clock to an ODDR primitive (Dedicated IOB double data rate output registers). This is suggested by Xilinx Vitex-5 User Guide. 4. forward this clock to FPGA B. on FPGA B, 1. use IBUG, DCM and BUFG to generate the synchronous clock. My concern is: 1. The 2 FPGAs don't have knowledge about each other. How does these two clock synchronize to each other ? 2. I put huge clock uncertainty (4 ns) with INPUT_JITTER. I hope this will compensate the latency on board. 3. What IO standard and PAD's constraints is suitable for this? One background that why I didn't choose board clock source to distribute 2 FPGAS is because we want the 100 MHz clocks of both FPGAs synchronized to APP_CLK. Appreciate any help in advance. Chris Kuo @ Austin, TexasArticle: 120746
Jeff Cunningham wrote: > Andreas Hofmann wrote: > >> Do you have disabled the "Mark to initialize BRAMs"-Option for the >> ppc405_bootloop? The icon next to ppc405_bootloop on the "Applications" >> tab should contain a small red x. You can adjust the setting by right >> clicking on the bootloop entry. > > Thanks, Andreas - I didn't notice the bootloop "application" in the > little window (not in bold type like the other apps). I disabled that, > and now when I try to update the bitstream, the first time Data2mem > runs, it crashes. If I run it again, it says nothing needs to be done. > But when I then go to download the bitstream, it says the bitstream is > empty. I guess I will need to open a webcase on this unless anyone has > any better ideas. By anychance, did you try to make a compressed or encrypted bitstream ? data2mem doesn't support those and it just crashes ... SylvainArticle: 120747
Hi, I'm new to FPGA world and currently working on an emulation board with 2 Virtex-5. I think to forward clock from chip A to chip B. Is that possible to make these 2 clocks synchronous ? What kind of steps, components and constraints need to be done to ensure the synchronous between these 2 FPGAs. The clock frequency is about 50-100 MHz range. My current scheme is as following, but doesn't work properly. Any help is appreciated. On FPGA A, 1. A clock, APP_CLK (200 MHz), comes out of a DCM, which is used to mange the receiving clock from off-chip DDR2 DIMM. 2. APP_CLK drives another DCM for clock synthesis of 100 MHz and 50 MHz. The feedback of this DCM is from the output of DCM itself, which may be an issue. 3. Takes the 100 MHz clock to an ODDR primitive (Dedicated IOB double data rate output registers). This is suggested by Xilinx Vitex-5 User Guide. 4. forward this clock to FPGA B. on FPGA B, 1. use IBUG, DCM and BUFG to generate the synchronous clock. My concern is: 1. The 2 FPGAs don't have knowledge about each other. How does these two clock synchronize to each other ? 2. I put huge clock uncertainty (4 ns) with INPUT_JITTER. I hope this will compensate the latency on board. 3. What IO standard and PAD's constraints is suitable for this? One background that why I didn't choose board clock source to distribute 2 FPGAS is because we want the 100 MHz clocks of both FPGAs synchronized to APP_CLK. Appreciate any help in advance. Chris Kuo @ Austin, TexasArticle: 120748
Hi, (Sorry that if I sent this more than once. Somehow, my email client just doesn't function well.) I'm new to FPGA world and currently working on an emulation board with 2 Virtex-5. I think to forward clock from chip A to chip B. Is that possible to make these 2 clocks synchronous ? What kind of steps, components and constraints need to be done to ensure the synchronous between these 2 FPGAs. The clock frequency is about 50-100 MHz range. My current scheme is as following, but doesn't work properly. Any help is appreciated. On FPGA A, 1. A clock, APP_CLK (200 MHz), comes out of a DCM, which is used to mange the receiving clock from off-chip DDR2 DIMM. 2. APP_CLK drives another DCM for clock synthesis of 100 MHz and 50 MHz. The feedback of this DCM is from the output of DCM itself, which may be an issue. 3. Takes the 100 MHz clock to an ODDR primitive (Dedicated IOB double data rate output registers). This is suggested by Xilinx Vitex-5 User Guide. 4. forward this clock to FPGA B. on FPGA B, 1. use IBUG, DCM and BUFG to generate the synchronous clock. My concern is: 1. The 2 FPGAs don't have knowledge about each other. How does these two clock synchronize to each other ? 2. I put huge clock uncertainty (4 ns) with INPUT_JITTER. I hope this will compensate the latency on board. 3. What IO standard and PAD's constraints is suitable for this? One background that why I didn't choose board clock source to distribute 2 FPGAS is because we want the 100 MHz clocks of both FPGAs synchronized to APP_CLK. Appreciate any help in advance. Chris Kuo @ Austin, TexasArticle: 120749
> I guess the choice is to either make a PLB slave that can access the > flash, or sacrifice two brams. There's one more option. You can implement a custom ISOCM slave to interface a tiny COREGEN ROM with your loader code. It should be do- able with <32 instructions (128 bytes of ROM). Regards, Marc
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