Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Marc Weber wrote: > Hello > > I'm new to FPGAs. > > I need some kind of 30-40 channel input extension beeing able to detect > 0.01mA currents. (The current should flow through your fingrs .. ;) > I already know that implementing some kind of multiplexer is no problem. > But can I use a FPGA as well to detect these low currents? > This could be done by a analog comparator or by amplifying using two > transistors. > > Of course this could be done using asics. But I don't know wether I need > that a high volume to pay off. You should give more info on what you are trying to do, and is this a Lab situation, or something you expect to have in volume production. If you want to sense 10uA to 1% precision, then no, Digital devices will not work for you. If you just want to sense if someone has touched a terminal, than you might be OK. Leakage currents are highly temperatute dependant. Rather than run 40 wires to the FPGA, you could use low cost logic devices like HC165, or HC597 to chain all your detect points into a serial data stream, or if you need lower voltage, use a CPLD like Atmel ATF1502BE/ATF1504BE - that specs 1uA MAX leakage, and has good schmitt buffers. You may not need a FPGA at all, if you just want to sense & act on a few lines - CPLDs can do that very easily. -jgArticle: 121151
On 2007-06-26, PFC <lists@peufeu.com> wrote: > Can you give more details about upcoming gear ? If it looks good I may > decide to wait. Just what every company loves to hear!! -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/Article: 121152
commone wrote: > Did you mean that if I assign the "PLL1_outp" to c1 it will function > as general I/O pin; otherwise,if I assign the PLL1_outp to c2 it will > function as PLL<#>_out? I do not know if there is an option available in > Quartus II to determine this pin to function as a general I/O pin or > PLL<#>_OUT. But does this problem influence the compensation for clock > skew? According to the Pin Information for the Cyclone II, the PLLn_OUTp/n pins can be used as general IO with PLLn_OUTp/n an optional functional. And yes, IIUC if you drive it with C0/C1 then it is in effect a general IO and you cannot use the compensation as you would for C2. > Another question: > IN "Pin Information for the Cyclone® II EP2C15A, EP2C20..." it is said > that "These pins can only use the differential I/O standard if it is being > fed by a PLL output" for PLL[1..4]_OUTP. (on page 19) > But in Cyclone II device handbook it is said that "One of these outputs > (C2) can also drive a dedicated PLL<#>_OUT pin (single ended or > differential)." (Table 2-4 on page 2-26) > So my question is if the PLL1_OUTP can be funtion as a single ended > external clock out fed by internal pll ouput C2 or it must be used along > with PLL1_OUTN to function as a differential clock output fed by c2. Not really sure what your confusion here is??? You can drive single or differential output with C2. What may be confusing you is the statement from the pin info on p19 - it means you can't use PLLn_OUTp/n as differential *general-purpose* IO - only a differential clock output driven by the PLL. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 121153
I am simulating a verilog design that uses Virtx4 ISERDES primitive. This design requires the "O" ouput pin of the Virtx4 ISERDES primitive. The "O" pin in the Virtx4 ISERDES primitive provides a copy of D input or delayed copy of D input. Now I am transitioning my design to Virtex5. Virtex5 ISERDES primitive does not seem to support the "O" output pin. This is a timing sensitive design and wanted to know clean way to do this in Virtex5. Why this pin was removed from Virtex5 ISERDES module? What was its original purpose in Virtex4? What is the best way to handle this? Is it as simple as using a buf to get the signal and use it? Thanks for your help. VimalArticle: 121154
Wow, I'm embarrassed. You were right, I forgot the part in the manual/readme which says I need to load the DE1_USB_API pof/sof file. It's working now! I bought my kit through digikey.com, and it came (flash) preloaded with the flashing-lights demo-application -- apparently not the same FPGA-bitstream as the Control-Panel applet. "RedskullDC" <red@oz.org> wrote in message news:wM6dnVKN-L0MO-LbnZ2dnUVZ_o6gnZ2d@giganews.com... > Hi, > > You are of course copying the default project back to the FPGA that comes > on the CD? > DE1_USB_API.pof/sof ? > (or whatever Altera call it on their CD, I bought mine direct from > TerASIC) > > The control panel will 'see" the USB port, but will only "talk" to the > default project > (or something that emulates it). > > Red > > "mitshek" <noal@ajkl.com> wrote in message > news:e3Afi.8490$c06.4187@newssvr22.news.prodigy.net... >> I'm using Altera's "Cyclone II Starter Kit", and while the board seems to >> work fine, I can't figure out one of the bundled utility programs. >> >> I installed the Cyclone II Starter Kit CD on my Windows/XP machine. I'm >> able to use Quartus II 7.1 (web) to compile and then download projects to >> the board -- That works fine. >> >> However, I cannot get the "Control Panel - Starter II Kit" application to >> work. I launch it, and the application window comes up. It appears to >> work fine -- I can 'open USB' connection to my board, then click on the >> various tabs (sram, sdram, led, etc.) and toggle the controls. However, >> when I click 'set' on anything, nothing happens. I see the blue-light on >> my Kit board flicker momentarily, so it's getting some kind of traffic >> from the PC. But otherwise, nothing happens. >> >> For example, I tried the 'SRAM' tab, and wrote several unique values >> (0x0123, 0x4567) to the SRAM at address 0x00 and 0x01. But, when I read >> them back, they always come back 0x0000. The Control Panel's built-in >> self-test also fails on the sdram, sram, and flash. >> >> What am I doing wrong? I tried toggling the RUN/PROG switch (SW12) back >> and forth, then cycling power to the board. With either position, Control >> Panel applet still doesn't work. >> >Article: 121155
VGA 1920x1080 and HDTV 1920x1080i aren't the same thing. The HDTV-signal is 60Hz interlaced, and runs at a pixel-clock of 74.25MHz (60Hz), or 74.178MHz (59.94Hz.) Are you just looking for a board with VGA-output? Or do you need a board with both VGA-in (ADC) and VGA-out? If it's just VGA-output and nothing else, then you have plenty of choices. Xilinx and Altera have demo/evaluation/kits with a bunch of random peripherals/RAM, and many of them have VGA RAMDACs capable of 1920x1080 output. Either a TI, Analog Devices, Chrontel, or other RAMDAC. (Nowadays, RAMDAC products have evolved into integrated DVI-D transmitters and VGA DAC functionality on one-chip.) Boards with full-path VGA in/out are more specialized and expensive. "vasile" <piclist9@gmail.com> wrote in message news:1182833447.150084.178110@w5g2000hsg.googlegroups.com... > Hi, > I need a VGA 1080x1920 chip supporting HDTV. Anyone here has used > before such IC ? > > thank you, > VasileArticle: 121156
Rotem, I am afraid that there is no such product..(at least in my knowledge). You may ask from technical support of Vivid engineering, if they intend to design any product meeting your requirement in near future. Try designing a custom board .............as a last option On Jun 27, 2:12 am, Rotem Gazit <rotem.ga...@gmail.com> wrote: > Hi All, > We are looking for a board (or adaptor) able to convert CameraLink > video to Hotlink-II. > > Thanks in advance, > RotemArticle: 121157
Be sure to place I/O markers at the input and outputs. Otherwise, you will get an error. Highlight the top level schematic in the source window. In the process window below expand 'User Constraints' and double click 'Assign package pins'. Answer 'Yes' to create constraint file. The program Xilinx Pace should start. In the 'Design Browser' window expand the 'I/O Pins' tree list. Drag each pin to the desired available I/O pin. Save and close. You can implement a design without assigning pins. It will automatically place the I/O pins at the most effecient place. This is useful when designing a new board, and you want optimun placement and performance. Ensure the top level schematic is still highlighted. In the process window double click 'Implement Design'. Review the log window below for any errors. I can email you a zipped AND gate project if you want! evansamuel@charter.netArticle: 121158
The device is v4fx60-ES. EDK and ISE versions are 9.1.02 and 9.1.03 seprately. The error message apears as follows: Phase 7.5 Phase 7.5 (Checksum:42c1d79) REAL time: 1 mins 10 secs Phase 8.8 .............. ........... DeleteInterpProc called with active evals This application has requested the Runtime to terminate it in an unusual way Please contact the application's support team for more information. ERROR:Xflow - Program par returned error code 3. Aborting flow execution... make: *** [implementation/plb_pci.bit] Error 1Article: 121159
"Jeremy" <jeremylees@hotmail.com> writes: > Greetings, > > Has anyone used Microsoft Visual Source Safe or any other software I wouldn't use Sourcesafe myself - I've lost data to it :-( > version control applications to manage ISE projects? More specifically > what files are required to be maintained to keep a project intact, and > which files can be regenerated through Synthesis and Place and Route? > I use Subversion here, although I don't use ISE project Navigator, just a build script. Subversion works very well, having commandline tools which mae automating releases very simple for me. And TortoiseSVN integrates well with Windows Explorer for everyday use. Tortoise isn't perfect, merging changes from multiple branches can be a bit of a pain, although you can add external tools to help with this. To regenerate, you should just need your HDL source, ISE project file and your UCF file. And if you use Coregen, I guess that'll have stuff that needs saving, but I try and avoid that! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 121160
Thank you MarkArticle: 121161
Thank you all for your replies.
Can you/ would you use an fpga to replace a microcontroller already
containing already USB support? (1000+ < $1,70).
> You should give more info on what you are trying to do,
I hope this is not to much off topic.
I want to design a new computer interface. A mouse keyboard hybrid.
Similar to the one described on www.combimouse.com (US patent only)
but the two moveable parts should be more like a mouse:
= = =.
x |_,_,_, ( x = optical sensor, , = keys, ~ = USB cable )
=============~~~~
Because they should be moveable I can't imagine using some
kind of fixed grid to reduce inputs.
I want to have have between 30 and 40 keys
The Fxx keys could be accessed using a special shift key.
I'd like to have two mouse pointers as well.
Some drivers already have been written for WinXP .. (cpnmouse on sf)
There are different ways to implement the keys:
a) standart keys you have on most keyboards:
- to big. Why do you need to press a key down anyway ? All you need is feedback.
b) using your finger as resistor. (This has caused the original question)
(-) ESD problems
30-40 channel
using multiplexers (approx 4EUR) :
(eg 5x8 channel : DG408DYZ ¿ INTERSIL ¿ IC, SM 8-KANAL ANALOG MUX)
quantitios: quantitiy 100+ 5*0,79 EUR (de.farnell))
+ one transistor + comparator
or two transistors two amplify current
I've tried this using a atmel avr microcontroller and it did work well
using IO extensions would mean overkill when adding 30 to 40 amplifiers ?
using FGPA:
nice: everything can be integrated wihtin a chip, even the
microcontroller ?
eg "The LatticeMico32" is a highly
configurable 32-bit Harvard
architecture "soft" microprocessor core for Lattice FPGA
devices" [1]
Don't know how much this component would cost?
Parhaps you can give me an estimate (FPGA/CPLD to just collect inputs,
FPGA conctaining the microcontroller as well?)
c) capacitive sensors
(-) you need two wires for each "key"
(-) I think they are more expensive compared to a conductor
(But I don't know exactly because I don't have much experience
in calculating final production costs (lacking experience)
I know about: (approx >= 4.05 EUR )
http://www.analog.com/en/prod/0,,760_1077_AD7142,00.html
(3x $1.35 quantity 1000+)
c) some kind of touch pad
- you don't feel wether you have hit the key or not because everything
is one plane.
e) tactile switches ? Do you think there are some beeing an option?
Mmmh I just don't know which is the best way to implement this yet.
And I don't know yet which controlling component to use.
Atmel AVR. I have a developement board (avr-gcc etc)
The chips used by avagotech's SDNK reference kits?
(Cypress / freescale)
If you are interested and want to join drop me a mail.
Marc Weber
links:
[1] http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/index.cfm
Article: 121162On Wed, 27 Jun 2007 00:21:22 -0700, Perry <lipeng.net@gmail.com> wrote: >The device is v4fx60-ES. EDK and ISE versions are 9.1.02 and 9.1.03 >seprately. >The error message apears as follows: ... >DeleteInterpProc called with active evals > >This application has requested the Runtime to terminate it in an >unusual way >Please contact the application's support team for more information. It's a new one on me. But often when PAR crashes for no good reason, re-running with a different cost table seed (-t 3 for example) gets past the problem. - BrianArticle: 121163
Hi all, I am facing a problem. I cannot find the opb AC97 Controler in BSB, EDK 8.2 to add to my project. I am new to EDK Please some one help me out.... Thanking You cheers Dinesh dineshvc@gmail.comArticle: 121164
On Tue, 26 Jun 2007 11:34:25 +0530, "Ravishankar S" <ravishankar.s@in.bosch.com> wrote: >Im in embedded software development, but interested in developing a device >which can caputure trace information from a Nexus class-3 compliant >processor. Possibly later changed to capture trace from any processor. The >trace has to be modfied to be used by data-acquisition application running >on a PC (interfaces: USB/Ethernet/Firewire) > >I figured out that using an FPGA would be ideal for such a application. But >which one ? Any recommendations ? Unless you expect to embed this functionality in large numbers of copies of your product, you should instead consider an off-the-shelf logic analyzer from the usual instrumentation suppliers. You will get all the functionality you describe, lots of built-in software and configurability, and a helpdesk to beat-up when things aren't going well. Many hobbyists make do-it-yourself logic analyzers based on some kind of FPGA+PC combination, but it's labour-intensive stuff. If you need this for your development lab(s), go buy or rent a ready-to-use box. They're not cheap, but it's well-established technology and they work brilliantly. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 121165
On Jun 27, 1:38 pm, dines...@gmail.com wrote: > Hi all, > > I am facing a problem. > > I cannot find the opb AC97 Controler in BSB, EDK 8.2 to add to my > project. > > I am new to EDK > > Please some one help me out.... > > Thanking You > > cheers > Dinesh > dines...@gmail.com its not included with EDK http://www.xilinx.com/univ/xupv2p_demo_ref_designs.html it is inthere, and possible in many other demos on xilinxweb, but you need to install the IP core manually before adding it. AnttiArticle: 121166
Hi Jonathan, But this is a processor with no external bus. (Also its for experimentation). So logic analyser as far as I know wont help here. The idea is to build an emulator which can caputure the Nexus public messages and also write into internal memories of the controller for calibration of variables. Kind Regards, Ravishankar "Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message news:gfj483d0ts5gtub42nnog89g5dtlsf05vo@4ax.com... > On Tue, 26 Jun 2007 11:34:25 +0530, "Ravishankar S" > <ravishankar.s@in.bosch.com> wrote: > > >Im in embedded software development, but interested in developing a device > >which can caputure trace information from a Nexus class-3 compliant > >processor. Possibly later changed to capture trace from any processor. The > >trace has to be modfied to be used by data-acquisition application running > >on a PC (interfaces: USB/Ethernet/Firewire) > > > >I figured out that using an FPGA would be ideal for such a application. But > >which one ? Any recommendations ? > > Unless you expect to embed this functionality in large numbers of > copies of your product, you should instead consider an off-the-shelf > logic analyzer from the usual instrumentation suppliers. You will get > all the functionality you describe, lots of built-in software and > configurability, and a helpdesk to beat-up when things aren't > going well. > > Many hobbyists make do-it-yourself logic analyzers based on > some kind of FPGA+PC combination, but it's labour-intensive stuff. > If you need this for your development lab(s), go buy or rent a > ready-to-use box. They're not cheap, but it's well-established > technology and they work brilliantly. > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.bromley@MYCOMPANY.com > http://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated.Article: 121167
Hi Antti, I must come back to you at a later as I dont understand many extentions and applications here. Why is it called a "player"..? and what are these file formats..? If i understand right, the on the device side DB-25 we have to connect a cable with the header to the debug port (BDM,JTAG etc). And programming the device through the Parallel Port reconfigures the device side DB-25.. Kind Regards, Ravishnkar "Antti" <Antti.Lukats@googlemail.com> wrote in message news:1182844103.044847.288430@q75g2000hsh.googlegroups.com... > On Jun 26, 8:35 am, "Ravishankar S" <ravishanka...@in.bosch.com> > wrote: > > Hello Amontec, Larry, > > > > Spefically for you, since I did not get any reposone from the Amontec site! > > > > Could you explain the features of the chameleon. How does it work ? Can it > > be configured to work with any debug connection. Specifically I want to > > debug a MPC8241 (COP connector) and possibly a TriCore controller. How will > > the chameleon help here.. > > > > It has DB-25 parallel ports on both sides (I - O ) , how is the debug-port > > (like COP) to be connected ? > > > > Kind Regards, > > Ravishankar > > Since you havent got a reply from Larry let me answer you: > > with chameleon you can either use existing configurations, or you can > create your own LPT-ADAPTER if you know the function-schematic. > > just create the project with ISE, as output generate XSVF with OLD > version of XSVF tool !! rename the file to .ASVF then you can use > amontec > tool to reconfire chameleon. > > or if you have modified XSVF player then you can use latest version of > XSVF also. > > have fun! > > Antti > > > > > > > > > > > >Article: 121168
On Wed, 27 Jun 2007 17:34:43 +0530, "Ravishankar S" <ravishankar.s@in.bosch.com> wrote: Ravishankar, >But this is a processor with no external bus. Ah. Bad assumption by me. I just (foolishly) assumed that Nexus was yet another regular CPU. Any links I can follow to take a look? > (Also its for experimentation). OK, fair enough. >So logic analyser as far as I know wont help here. The idea is to build an >emulator which can caputure the Nexus public messages and also write into >internal memories of the controller for calibration of variables. Logic analysers can be persuaded to decode all manner of protocol stuff, but I agree that this sounds a bit too specialised. Sorry to have misunderstood. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 121169
My client is an award winning leader in their global field, and looking to expand their broadcast engineering team. If you are an engineer with strong Verilog VHDL experience then we would like to hear from you. C++ and FPGA experience would be a nice to have. If you want to be part of an unrivalled technical broadcast engineering team then please call us. We have 15 Long Term Contract roles available. Please call Richard Prentice on 020 7213 9876 for full information.Article: 121170
Oftentimes you can get some degree of relative control by proper placement of LUTs/FFs (or appropriate term for your technology.) But this would only give you relative control, which would vary over temp/voltage/process. Generally, the best solution is to use the appropriate clock period, and put the critical items in FFs. Then control the location of the FFs to suppress routing variability. Typically (but not very often), I will use such a behavioral construct to force the simulation tool to reflect 'reality' where a signal is guaranteed to be delayed (some tiny bit) from another. Unless doing timing simulation, the value is just a token delay to prevent ambiguity with event order. In your particlar case, muxing the two signals prior to a FF is probably the ideal solution, since clock_rd is gated. There are additional issues to be concerned with, though: getting onto the clock tree. If there are just a few loads in a Xilinx part, and they are all arranged properly, you could get away with local clocking (no global buffer.) But you still may need to be concerned about interaction with other clock domains. JTW "EEngineer" <maricic@gmail.com> wrote in message news:1182807776.669252.200390@k79g2000hse.googlegroups.com... > On Jun 25, 5:12 pm, Mike Treseler <mike_trese...@comcast.net> wrote: >> EEngineer wrote: >> >>> I did not use the ucf constraints file for the delay. Here is the >> >>> actual line of code I am using: >> >>> clock_rd <= clock after 20ns WHEN frame_done = '0' ELSE >> >>> clock_dby8_logic; >> >>> This works fine for one part of my design but doesn't for the other. >> >> The "after 20ns" is ignored for synthesis. >> > Why is it ignored? >> >> Because synthesis can only delay >> in increments of one clock period >> using a counter or shifter process. >> >> > It seems that it works fine in the other design. >> >> It is working with an unconstrained delay, >> so that is just good luck. So far. >> >> -- Mike Treseler > > > > >> "after 20ns" is ignored for sinthesys > Now this explains why I had some designs work perfectly only in > simulations but not on chip. > I was just lucky that it worked in the other case. > I am adding some more code so I can use 4 times faster clock and split > it by 2 twice so I can get needed clock and 4 possible stages that > will be used instead of "after 10ns" and "after 20ns". > > Dan >Article: 121171
On Jun 26, 2:46 pm, "N.V. Chandramouli" <mouli1...@gmail.com> wrote: > Dear all, > I am working on Virtex-4 Fx12LC (ML 403 ) Fpga that has > powerpc hard core. > I would want to load Linux RTOS onto it and try and access the on chip > memory and Fpga logic from that. > May I know if any body has the preview kit for Linux for that version > of the VIrtex-4 FPGA. > It would be great if they can disclose the details as to where can I > find the same. > thanks and regards > vijay I'm working on a design for a V4FX60. We used to use the MontaVista Linux Pro but have recently switched to using the latest kernel with patches from Grant Likely (secretlab.ca) and the rest of the linux- embedded-ppc development list (https://ozlabs.org/mailman/listinfo/ linuxppc-embedded). IIRC, w/ the latest kernel and the git from secret lab, there is support for most of the ML403 dev board. There is also a git repository from MontaVista themselves and they had support for the ML403 board as well. -- MikeArticle: 121172
I am trying to add a custom IP to my EDK project. I am using the
Avnet Mini-Module (MM) and EDK 9.1i SP2. This is my first custom IP
and I am starting off small. The MM baseboard has three LEDs that I
am trying to turn on/off. From my working project I created a custom
IP template and then imported my template into my project. I then
made the following changes:
To system.ucf I added:
Net fpga_0_LED1_pin LOC =G5 | IOSTANDARD = LVCMOS33;
Net fpga_0_LED2_pin LOC =F5 | IOSTANDARD = LVCMOS33;
Net fpga_0_LED3_pin LOC =E5 | IOSTANDARD = LVCMOS33;
To system.mhs I added the following:
PORT fpga_0_LED1_pin = fpga_0_LED1, DIR=O
PORT fpga_0_LED2_pin = fpga_0_LED2, DIR=O
PORT fpga_0_LED3_pin = fpga_0_LED3, DIR=O
and my custom IP
BEGIN opb_test
PARAMETER INSTANCE = opb_test_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x73c00000
PARAMETER C_HIGHADDR = 0x73c0ffff
BUS_INTERFACE SOPB = opb
PORT LED1 = fpga_0_LED1
PORT LED2 = fpga_0_LED2
PORT LED3 = fpga_0_LED3
END
And finally the opb_test.vhd file:
In the entity under user ports I added:
LED1 : out std_logic;
LED2 : out std_logic;
LED3 : out std_logic;
In the architecture I added the following internal signals:
signal iLED1 : std_logic := '1';
signal iLED2 : std_logic := '0';
signal iLED3 : std_logic := '0';
An also in the architecture under begin I added:
LED1 <= iLED1;
LED2 <= iLED2;
LED3 <= iLED3;
No matter what I default the internal signals to the LEDs do not
change state. Does anybody see what I am doing wrong or do you need
more information?
Thanks,
Glenn
Article: 121173Petter Gustad wrote: > I once implemented a microcode assembler generator in Common Lisp. The > specification for the mnemonics and arguments were written in Verilog > (as `define statements). The program would read this specification and > generate an assembler on the fly and then assemble the > microprogram. This sounds like a good idea for more complex designs, but I've simplified my design again, now the whole VHDL CPU core is 173 line, including comments, for which a generator would be overkill: http://www.frank-buss.de/forth/cpu1/ While developing the CPU, I implemented it in VHDL, first. Then I ported the VHDL source to an emulator, and I tested it with an assembler, both written in Forth. With the emulator it was easy to find some bugs, which changed the VHDL source, too. Now it is a nice little CPU core, not very fast (it needs 4-6 clock cycles per instruction), but small (423 LEs with an Altera Cyclone I device, about 7% device utilisation). The next step is a Forth cross-compiler. This should be easy, because basicly a colon definition needs only to define a constant with the highest bit set to 1 for the address (because then this will be interpreted as a call in other words by the CPU) and the content will be simply storing the value of constants to memory. A bit more tricky will be loops and if/then. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 121174
I need to extend a memory-mapped bus into another enclosure and thought that a bidirectional LVDS implementation with serial/ deserializer pairs at each end might work. Does anyone have any experience or guidance on such a setup?
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z