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Hi all, for my PhD thesis I am looking for a citeable publication describing the FPGA technology advances during the recent years (say 10 years - or even from the very beginning), especially what advantages were achieved regarding available logic resources and maximum clock frequencies. Does someone know about anything like this, e.g. some FPGA "timeline" ? Regards, S. HeitheckerArticle: 124351
Sorry for the wrong email address. It must be "sven.heithecker@web.de". Regards, S. HeitheckerArticle: 124352
On Sep 18, 9:01 am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > vasile wrote: > > On Sep 17, 10:39 am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > >> vasile wrote: > >>> Hi to everybody, > >>> I'ts not very clear from the Virtex 5 User guide, Clock resources > >>> chapter if it's possible to route (on different GCLK inputs) single > >>> ended and differential CLKs. Then at configuration time use either the > >>> single ended clock (routed at the P side of the differential input > >>> pair) or differential clock (say LVDS clock). > >>> User manual say: "The 20 global clock pins on Virtex-5 devices can be > >>> connected to 20 differential or 20 singleended board clocks" > >>> page20-21 and "Each clock input can be either single-ended or > >>> differential" page 20. That means only either single ended either > >>> differential clock is allowed? > >>> The second question is about differential clocks routed to XY GTP > >>> transcievers. Can those be used safely as GCLK or RCLK for the GTP > >>> opposite banks (banks far away from the GTPs) or an outer clock must > >>> be routed on PCB? > >> You are misinterpreting the documentation. A clock circuit is made > >> up of multiple resources including an package input pin (IBUF or IBUFDS), > >> an optional DCM or PLL and a global clock tree (BUFG). > > >> The paragraph that you quoted was discussing that the package input pin > >> could be either single ended (LVCMOS, SSTL, HSTL, etc) or differential > >> (LVDS). These package pins would be connected to a physical on board > >> clock device that outputs a specific signaling standard. A > > >> The MGTREFCLK input pins are intended only for use with the RocketIO > >> transceivers. These can be driven into the array, but it must be done > >> through an instantiated RocketIO and the only allowed connection from > >> here is to a BUFG. It is not recommended to use these pins for anything > >> other than RocketIO based designs. In particular you would not want to > >> use these pins for system synchronous designs as the timing is not the > >> same as defined clock input pins. > > > OK, thank you, this is answering just to a part of my question. > > Can I route both differential and single ended clocks to the same GCLK > > dedicated bank (like bank3 in LX330T ) and use both of them (one is > > LVDS as you say and the other is single ended 2.5V clock) ? > > Where can I found this info in the datasheet please, so I will not > > misinterpreting anymore ? > > The clock input pins are independently configurable just like the other IOs, > so yes you can have both single ended and differential inputs in bank 3. The > limitations on what IO standards can be used at the same time in this bank > is the same as for all other banks. > > Ed McGettigan > -- > Xilinx Inc.- Hide quoted text - Thank you, Ed. VasileArticle: 124353
You could ask that question in de.sci.electronics too. > or even from the very beginning Xilinx called them Programmable Gate Array or User Programmable ... or Logic Cell Array ( for that they had a trademark ) not FPGAs in 1984/86. But for better or worse they defined complexity in "number of gates" like gate arrays. Their part was "1k gates" and PLDs they defined as "100 gates". Earliest "field programmable" parts were probably bipolar PROMs. PLDs like John Birkners PALs ( MMI 1975 ) and later GALs ( Lattice 1986 ) were cheaper, less complex, commercially successfull ( not all PLDs could/can claim that ). There were before 1984 complex PLDs around ( Signetics FPLAs ; TI ). Usually based on bipolar PROMs like PALs but often limited to certain applications like state-machines. Expensive and not widely used. MfG JRDArticle: 124354
On 18 Sep., 22:25, acd <acd4use...@lycos.de> wrote: > Sorry, I thought the term "population count" was clear. > I mean counting the number of ones in a given input vector. > In this case, I want a pipelined circuit which can process a new input > vector every clock cycle, giving the result a fixed number of cycles > later at the output. > As mentioned, a tree of adders with increasing width would do it. > But I think using only a full adder at the last stage may be faster/ > cheaper. A tree aproach has the disadvantage of irregular routing which really hurts performance. If you want maximum speed and do not care about cost you could have a triangular setup. The vector is input at the top and in each clock cycle it is sent one DFF down and one to the left. On the left there is a column of carry save incrementers that add the bit coming from the right to the value from the top. At the bottom you add a log(N) stages to finalize the carry save result. This is a very expensive solution that probably can run at speeds a lot higher than the 550MHz the Virtex-5 is officially designed for. There was a correlator design published that used a similar approach to achieve 250MHz in a XC3195A. The BRAM result probably is more realistic and gets you 550 MHz. Kolja SulimmaArticle: 124355
On Wed, 19 Sep 2007 01:35:11 +1000, Allan Herriman <allanherriman@hotmail.com> wrote: >Hi, > >Since the initial rash of AES / Rijndael cores a few years ago, I >haven't seen much research at the high speed end. > >Does anyone know how low the latency is for a recent high-end core in >a current FPGA family? >A quick web search reveals plenty of heavily pipelined implementations >with poor latency, but none that are really quick in terms of latency. I did some tests today... I unrolled our (conventional) 14 round implementation into one big mess of combinatorial logic with FFs at either end and ran it through the tools: V5, using 8.2 software: Par spat the dummy after six hours, claiming it was too hard. I added a bunch of area constraints. It's still running. StratixII gave sixty-something ns (=14MHz clock) in the slowest speed grade, but that was without timing constraints. A version with a 30ns clock constraint is still running. 14MHz results in feedback modes giving about 1.8Gb/s encryption throughput. I guess that's enough for GbEthernet, but we already know GbE can be done with a conventional pipelined AES implementation. I'll post tomorrow on the results. Regards, AllanArticle: 124356
There is an excellent article about the use of fast 4k-bit SRAMs as reconfigurable logic devices. I believe the article was published by fairchild around 1978 an was called "When a memory is not a memory" or similar. Sorry, that I have no better pointer. The article describes how to build multipliers, state machines, etc. from those RAMs. Also, IBM used a technique in the 60ies where instead of using logic gates directly they used small boards with multiplexers on them. They could be configured using jumpers to implement various logic functions. Nearest neighbour connections where iconfigured by jumpers whereas the remaining interconnect used wire-wrap. The structure looked very similar to mux-based FPGAs (and likely invalidates many FPGA-related patents of the 80ies) Unfortunately I have no pointer to that either. Kolja Sulimma On 19 Sep., 11:52, Sven Heithecker <sven.heithec...@epost.de> wrote: > Hi all, > > for my PhD thesis I am looking for a citeable publication describing the > FPGA technology advances during the recent years (say 10 years - or even > from the very beginning), especially what advantages were achieved > regarding available logic resources and maximum clock frequencies. > > Does someone know about anything like this, e.g. some FPGA "timeline" ? > > Regards, > S. HeitheckerArticle: 124357
>> IF OP = "Weng Tianxiang" AND group = comp_arch_fpga THEN >> be_prepared_for_a_long_thread; >> ORIF crossposted = to_comp_lang_vhdl THEN >> this_could_go_on_all_week; >> ANDIF both_the_above THEN >> make_that_a_month; >> BUTIF plonk! THEN >> blessed_relief; >> ELSIF experiences < imagination THEN >> OP_question <= not(sense); >> ELSE >> possibly_on_topic; >> END IF; ... > > What's this ANDIF, BUTIF ?!?! > And I was hoping for an ORELSE :)Article: 124358
Hi KS, jg, I answer your questions directly and clearly here: 1. The number of state machines should be much greater than 100k. 2. "Many state machines have no reset signal. " I have answered your question: "A synchronous or an asynchronous reset signal is vital, either with clear routing or a hidden procedure within other initial procedures." 3. "a single FF_CE can be considered a state machine" No, a single FF_CE is not included in the count. Otherwise my post for a guessing doesn't make sense. 4. Shifting registers can and should be counted as a state machine with only one bit set (or only one bit reset) among all its bits. Please don't delete group names: comp.lang.verilog, comp.lang.vhdl Because answering this quiz needs knowledge beyond scopes of FPGA and VHDL. A quiz beyond FPGA and VHDL may have been the first time since both groups were set up 10-20 years ago. I have been wondering why there nobody is asking such a question: Why is this quiz beyond scope of VHDL? Any more questions? WengArticle: 124359
Hi!, I have a big problem: I use Libero to Proasic Plus Family of Actel. My FPGA has got 4 global pin (4 GL macro), I need put a clock in a global buffer but I can=B4t because I have others signals with highest fanout. what can I do? thanks chArticle: 124360
> ... >> >> What's this ANDIF, BUTIF ?!?! >> > > And I was hoping for an ORELSE :) I'm for BUTOUT.Article: 124361
I gave my guess. Why haven't you responded? You told me you would tell me the answer after I guessed. Now tell me. ShannonArticle: 124362
Weng Tianxiang wrote: > No, a single FF_CE is not included in the count. Otherwise my post for > a guessing doesn't make sense. Weng, it still doesn't make sense! But I hope you continue to post. You are very entertaining! -JeffArticle: 124363
On Sep 18, 6:31 am, Gabor <ga...@alacron.com> wrote: > 3) Don't assert LVAL while FVAL is deasserted. > You can violate any of these rules as necessary, but > realize that for each one you violate your list > of compatible framegrabbers gets shorter. To use National Instruments framegrabbers with their IMAQ software, you have to follow specific rules, one of which requires the camera to toggle LVAL four times before the start of each frame. What's amazing is that this really important piece of information is buried in the help file for their Camera File Generator program and their wonderful front-line tech support people don't know about it. Apparently this toggling clears the FIFO in the framegrabber's FPGA, or something. If you don't do it, then images aren't displayed properly. -aArticle: 124364
Sven Heithecker <sven.heithecker@epost.de> wrote: > Hi all, > for my PhD thesis I am looking for a citeable publication describing the > FPGA technology advances during the recent years (say 10 years - or even > from the very beginning), especially what advantages were achieved > regarding available logic resources and maximum clock frequencies. > Does someone know about anything like this, e.g. some FPGA "timeline" ? There was recently a link to PDFs of old XCELL magazines in this group. Starting from issue 17, second quarter 1995. A nice read, giving perhaps some points for your timeline. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 124365
>"A synchronous or an asynchronous reset signal is vital, either with >clear routing or a hidden procedure within other initial procedures." Nonsense. Consider self synchronizing scramblers. They are just a batch of XOR gates and FFs. From any unspecified state, they will put out garbage for N clock ticks. After that, the output is determined by the input. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 124366
> There were before 1984 complex PLDs around ( Signetics FPLAs ; >TI ). Usually based on bipolar PROMs like PALs but often limited to >certain applications like state-machines. Expensive and not widely >used. Not FPGAs, but history... Back in the 70s, it was common to built microcoded systems with the instructions stored in ROMs. The instruction format typically included a next-instruction field with branching done by ORing (or MUXing) a few bottom bits. Those bits often took longer to setup and were the limiting factor on the cycle time. ROMs were typically implemented as a wide word followed by a mux to select the right chunk out of that word. Sometimes the manufacturers would give you better setup times on the address bits that fed the MUX. Guess which ones were used for branching? Somebody made a neat part that included the ROM and some programmable branch logic (and registers and whatever). It was UV erasable. I forget who made it, but I think I can find a board and scrape off an old label if anybody is really curious. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 124367
comp.arch.fpga wrote: (snip) > But you do not react if someone answers your question. > Can you beat the 10k+ state machines of a > smith-waterman DNA matcher? If this is the one I remember, then it is wrong: Smith-Waterman does local alignment which requires finding the maximum score anywhere in the array. Global alignment only needs the score at the end. It is interesting, but most DNA research needs the local alignment. Paracel and Time Logic make (or made) commercial DNA matching machines that should qualify as large number of state machines. -- glenArticle: 124368
On Sep 19, 3:53 pm, hal-use...@ip-64-139-1-69.sjc.megapath.net (Hal Murray) wrote: > >"A synchronous or an asynchronous reset signal is vital, either with > >clear routing or a hidden procedure within other initial procedures." > > Nonsense. Consider self synchronizing scramblers. They are > just a batch of XOR gates and FFs. From any unspecified state, > they will put out garbage for N clock ticks. After that, > the output is determined by the input. > > -- > These are my opinions, not necessarily my employer's. I hate spam. Hi Hal, Can you please put more information on scramblers and their state machines? I don't know scramblers. WengArticle: 124369
On Sep 19, 9:59 pm, Allan Herriman <allanherri...@hotmail.com> wrote: > On Wed, 19 Sep 2007 01:35:11 +1000, Allan Herriman > > <allanherri...@hotmail.com> wrote: > >Hi, > > >Since the initial rash of AES / Rijndael cores a few years ago, I > >haven't seen much research at the high speed end. > > >Does anyone know how low the latency is for a recent high-end core in > >a current FPGA family? > >A quick web search reveals plenty of heavily pipelined implementations > >with poor latency, but none that are really quick in terms of latency. > > I did some tests today... > > I unrolled our (conventional) 14 round implementation into one big > mess of combinatorial logic with FFs at either end and ran it through > the tools: > > V5, using 8.2 software: Par spat the dummy after six hours, claiming > it was too hard. > I added a bunch of area constraints. It's still running. > > StratixII gave sixty-something ns (=14MHz clock) in the slowest speed > grade, but that was without timing constraints. A version with a 30ns > clock constraint is still running. > > 14MHz results in feedback modes giving about 1.8Gb/s encryption > throughput. I guess that's enough for GbEthernet, but we already know > GbE can be done with a conventional pipelined AES implementation. > > I'll post tomorrow on the results. > > Regards, > Allan Allan, you want to encrypt the data from the GbEthernet interface? Whether the GbEthernet interface is in the same the FPGA board? If not, even you find the maximum frequency for the AES algorithm, you should consider the delay of the OS.Article: 124370
>Can you please put more information on scramblers and their state >machines? >I don't know scramblers. The idea is to generate a random bit stream that you can XOR with a data stream for a serial link to make sure there are no long strings of 0s or 1s. It's a pile of FFs and XORs. The same logic as CRCs. LFSR, Linear Feedback Shift Register is another buzzword. The "self synchronizing" part means that the output doesn't need to be reset. It will get to a known state after N cycles. A single bit error on the link will produce a multi-bit error after the descrambler. That pattern of bits is the polynomial used by the scrambler. The wiki article is pretty good. http://en.wikipedia.org/wiki/Scrambler_(randomizer) A digital communications text might be better. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 124371
On Sep 19, 5:58 pm, hal-use...@ip-64-139-1-69.sjc.megapath.net (Hal Murray) wrote: > >Can you please put more information on scramblers and their state > >machines? > >I don't know scramblers. > > The idea is to generate a random bit stream that you can XOR > with a data stream for a serial link to make sure there are > no long strings of 0s or 1s. > > It's a pile of FFs and XORs. The same logic as CRCs. > LFSR, Linear Feedback Shift Register is another buzzword. > > The "self synchronizing" part means that the output > doesn't need to be reset. It will get to a known state > after N cycles. A single bit error on the link > will produce a multi-bit error after the descrambler. > That pattern of bits is the polynomial used by the scrambler. > > The wiki article is pretty good. > http://en.wikipedia.org/wiki/Scrambler_(randomizer) > A digital communications text might be better. > > -- > These are my opinions, not necessarily my employer's. I hate spam. Hi Hal, Thank you very much for your information. WengArticle: 124372
Hi Hal, 8b/10b is perfect for scrambling function. PCI-e uses 8b/10b technology. Scramble technology still uses randomized serial and XOR now? After 8b/ 10b technology, I think other randomized XOR scramble technology is dying out, is it right? IBM got one patent for 8b/10b technology in 1981, Xilinx filed for 23 patents on 8b/10b implementation in FPGA on one day in 2004. I think that IBM is really a technology leader in almost all respects in computer industry. Xilinx is the leader of FPGA. WengArticle: 124373
Far too restrictive. In a TDMA architecture I implemented, one RAM contains
512 locations of N bits each: 512 individual state machines. Each 'virtual
process' was identical, but had different inputs. For this particular
design, a lower bound on the number of states would be 4*512 = 2048, since I
had four instances of that particular module. Probably double that, due to
similar logic structures downstream. If it were appropriate for the
application, scale it up appropriately.
Depending on required processing speed, state machine complexity, target
device capabilities, etc., an internal (or external) RAM could contain
thousands -- or millions -- of individal state machines.
For my particular case, the next states were defined by equations, the last
states were the outputs of the RAMs, and the particular state machine was
selected by the RAMs address. (I instantiated the RAMs, but they could have
been generated by a process. However, the tools aren't always that good at
properly inferring dual-port RAMs, so if you need a particular
structure... )
So, what are the limiting factors? Available logic, available storage
(registers and memory), creativity, and objectives.
What is the value of the answer?
JTW
"Weng Tianxiang" <wtxwtx@gmail.com> wrote in message
news:1190052227.791942.311570@w3g2000hsg.googlegroups.com...
> Hi,
> OK, a state machine is defined by standard one process or two
> processes in VHDL.
>
> There is no short cut.
>
> It can be implemented in anywhere in a design and where the state
> machine is located is decided by compilers and beyond the interest of
> this topics.
>
> I have to expand the guess to include Verilog group people, because
> VHDL people may have no chance to do the designs.
>
> I may know the answer. The final result may surprise everyone who
> gives a guess.
>
> Thank you.
>
> Weng
>
From dont@email.me Wed Sep 19 19:52:14 2007
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From: Berk Birand <dont@email.me>
Subject: Gated Clock Problems
Date: Wed, 19 Sep 2007 22:52:14 -0400
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Hi everyone,
I am running into a really peculiar problem for a research project that I
am working on. The circuit is fairly simple one, which needs to measure
which one of two signals reaches a flip-flop first. Two impulses are sent
through two different paths, and they are both fed to a D flip-flop. The
circuit uses a nifty trick for outputting which signal got there first.
One of the signals (signal A) is connected to the D input, and the other
one (signal B) to the Clock input. Both signals get a 0-to-1 transition.
If signal A arrives first, D is '1' when there is a transition on Clk,
so output of flip-flop is 1:
|-------------
A (D) |
____|
|-------------
B (Clk) |
__________|
If signal B gets there first, then when Clock occurs, D is still '0', so
output is '0'
|-------------
D |
_________|
|-------------
Clk |
____|
(I hope my feeble attempts were sufficient to demonstrate the situation)
It was pretty easy to code this using VHDL; I just needed to connect the
signals correctly.
The problem is that during the Place & Route phase, I receive a warning
telling me that I have a clock signal coming from a combinatorial, gated
circuit. As I have pointed out, this is actually what I want. The peculiar
problem manifests itself as follows:
When I synthesize it, the Device Summary correctly finds 64 slices that
are being used. Yet when I run PAR, that number suddenly becomes 8 slices!
I think the reduction in the slice count is due to the given warning,
since the rest of the circuit behaves as expected.
Can anybody tell me how I should deal with this situation? I have tried
using a CLOCK_SIGNAL attribute, but I doubt that's what I want.
I would appreciate any help,
Thanks,
Berk Birand
--
Posted via a free Usenet account from http://www.teranews.com
Article: 124374>I am running into a really peculiar problem for a research project that I >am working on. The circuit is fairly simple one, which needs to measure >which one of two signals reaches a flip-flop first. Do you understand metastability? The problem you are describing is its first cousin called the arbiter problem. It used to be more common before designers generally switched to synchronous systems. The basic rule is that you don't know how long an arbiter will take to generate the answer. http://en.wikipedia.org/wiki/Arbiter_%28electronics%29 If you are working with traditional synchronous logic, it's probably simplest to send both external signals through the standard pair of FFs and then make the decision with normal logic. You can keep an extra bit of state and alternate the answer if both arrive during the same cycle. -- These are my opinions, not necessarily my employer's. I hate spam.
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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z