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Peter Alfke wrote: <paste> > I do not see how metastability could ever be a "useful" feature. I can think of a couple of useful tasks : One would be as a seed scheme, for simple random number generation systems. Another would be for comparing very low jitter systems. A metastable capture, means the edges were within a _very_ narrow time slot, so it can give information. <snip> > On a related subject: It amazes me that there is so much talk and fear > about metastability, but nobody gets his fingers dirty and performs > real measurements. > I published "my" original circuit 18 years ago (!), and to my > knowledge no university has picked this up as a simple challenge. Any > competent student can grasp the concept in less than a week, and > anybody with the skill to configure FPGAs or CPLDs can duplicate these > experiments in a short time with simple equipment, ( an eval board, a > variable clock source, and a stop watch), and every experiment usually > runs for less than an hour. Why does nobody try to PROVE me (and > Xilinx) right or wrong? > I have publicly (in this newsgroup) offered my assistance, but nobody > responded. I can see areas where the work can be extended :) The measurements themselves I doubt anyone has issues with. Suppose we extend this to consider peak rates (as opposed to averages, which assumes non-correlated frequencies) First, let's move into the time domain, (as this is really a time- domain problem) and look at phase velocities : For simplicity of a first pass, (and nice round numbers) let's also assume a 0.1fs metastable window. and a 100fs jitter - so jitter is 1000x larger than the window. Also treat the jitter as a rectangular probability Now consider a 1.00MHz data rate, and two possible clocks, both chosen to give the same phase velocity of 0.1fs/cycle Using CCalc, we have > (1/(1e6+.1e-3))-(1e-6) ans = -99.99999999000000000100000e-18 (we'll call that 100 atto seonds, 0.1fs ) So, that's 0.1mHz above (or below) 1MHz Now, do the same with a 100MHz clock - note that only one clock in every 100 can sample the data, so the phase velocity is 100as in 100 cycles ((1/(100E6+10e-3))-(10e-9))*100 ans = -99.99999999000000000100000e-18 so 10mHz above (or below) 100MHz [or look at is as 0.1ppb] These two clocks have identical peak error rates, and sweep the 0.1ps jitter window, in 1000 consecutive data times. - This 1ms time is the expected 'hot zone'. Outside this, we would not expect to see any events. The 1MHz clock repeats this zone every 10^4 seconds, or appx once a day. The 100MHz clock only has to go to the next cycle, so repeats the zone every 100 seconds - so the average event rate is 100x higher at 100MHz, even tho the phase-velocities and peak rates are the same. The data-referred sample window size, should be identical in both cases, as it depends on the FF, not the clock speed. A good test system for these clocks would add the ability to capture consecutive events which are possible at the data rate (not the clock rate) , as well as log the time-stamp for each, which would then allow a 'sampling scope' style density plot to be built up over time. This would enable post-test verify of the phase velocity, (and actual frequency correlations) and allow a profile of the equivalent jitter.window combination. Assuming frequencies are un-correlated, and taking an average probability seems to be a common engineering approach, but as time progresses, and frequency sources get better and better, and PLL are more widespread, and things like GPS spread a 'global standard', it may be better to also consider peaks as well. Of course, as someone has mentioned, you could PLL this to deliberately sit in the 'hot zone' as much as possible - and this may even give a means to 'quality test' a given PLL, if you have the means to seek the hot zone. 'slow PLLs' may be able to do this The holy grail of a Metastable-seeking-PLL, would be one event every data-sample :) -jgArticle: 128076
>Ask a question that someone can answer as opposed to simply a question >that you can ask and you may get better help. Thanks for bouncing this poor question. If badly-posed and off-topic questions were more often rejected, those who would post them might stop first to think about how to ask, to think where to ask it and to let us know their own thoughts so far. When the last is omitted, I wonder if they've given it any thought at all (those whose first reaction to any problem is to throw up their hands and cry "Help!"). MikeArticle: 128077
Search under "systolic array". Marco ________________________ Marc Reinig UCO/Lick Observatory Laboratory for Adaptive Optics "lm317t" <lm317t@gmail.com> wrote in message news:3f2454fc-77ca-44e0-b156-4990866ca71d@s19g2000prg.googlegroups.com... >I have heard that FPGA's can have a much larger throughput, dollar per > dollar, than a special purpose DSP chip because of their parallelism. > Anyone here have any experience or pointers on this topic?Article: 128078
A relatively simple method is to do individual synthesis & ngdbuild/map for your block(s) of interest. Be sure to prevent deletion of unused logic, and you probably won't want IO instances. You can also use this method to get a reasonable estimate of achievable performance for the block by running through par. JTW <paragon.john@gmail.com> wrote in message news:27f58b4c-e4d6-436e-bccf-92954f83bec0@k2g2000hse.googlegroups.com... > Hello, > > I am interested in looking at the resource utilization of a design I > am working on broken down based on the RTL hierarchy of the design. I > am using a Virtex-II Pro part. I have seen in the past where you can > do this using Floorplanner, however when I attempt to use Floorplanner > on my design I get the following error.... > > "The design contains macros with RPM grid coordinates which are not > supported by Floorplanner" > > After digging a little in Xilinx's Answer Database, I don't believe > that there is a way around this based on this answer.... > > http://www.xilinx.com/support/answers/19355.htm > > Specifically, this line.... > NOTE: These solutions will not work if any of the cores have hardware > multipliers because the RPM_GRID system must be used with multipliers. > > I use hardware multipliers in my design. > > Does anybody have any ideas as to how I could get my design in > floorplanner, or another option for viewing the broken down resource > utilization? > > Thanks for all the help. > > Regards, > John >Article: 128079
Well, perhaps you can find somebody or some institution to dive into this. I am far too pragmatic. I think 99% of all metastability problems (real and imaginary) deal with uncorrelated clock frequencies. That's why I wanted (and did) establish numerical results, so that everybody knows what to be (or not to be) afraid of. Since that goal is met, I rather spend my part-time effort on convincing our circuit designers to improve the gain x bandwidth product, in order to reduce the metastable capture eye even more. Good luck with your sophisticated plans. I hope somebody else will translate them into practicality and reality. Action counts more than words! Peter AlfkeArticle: 128080
"FPGA" <FPGA.unknown@gmail.com> wrote in message
news:45f5408b-5139-4031-9793-d00d49bed668@f47g2000hsd.googlegroups.com...
On Jan 14, 3:34 pm, KJ <kkjenni...@sbcglobal.net> wrote:
> On Jan 14, 3:04 pm, Ann <thakkar.an...@gmail.com> wrote:
>
> > I am trying to write a sunction for complex multiplication of 2
> > complex numbers
>
> > function complex_multiply(a : signed; b: signed; c : signed; d:
> > signed) return signed;
> > (a + bi)(c + di) = [ac - bd] + [ad + bc]i.
>
> > I am not sure on how I would return the real and imaginary part of the
> > result. As per my understanding functions can return only one value.
> > How do i represent the inputs and outputs? I want to write code in
> > VHDL to be implemented on an FPGA.
>
> Define a new complex record type...
> type t_My_Complex_Type is record
> Real: signed;
> Imag: signed;
> end record;
>
> Now your function would be defined as
>
> function complex_multiply(a, b : t_My_Complex_Type) return
> t_My_Complex_Type is
> variable RetVal: t_My_Complex_Type;
> begin
> RetVal.Real := a.real * b.real - a.imag * b.imag;
> RetVal.Imag := a.real * b.imag + b.real * a.imag;
> return(RetVal);
> function complex_multiply;
>
> If you're really feeling gutzy, you can instead call the function
> "*" (with the double quotes) and you'll be defining an override for
> the multiply operator so you could use your function like this...
>
> C <= A * B;
>
> instead of
>
> C <= complex_multiply(A,B);
>
> But I would suggest getting it working with the new type and seeing
> how that all works first. Record types are synthesizable.
>
> Kevin Jennings
> It gave me errors. The result would be twice as long as the lengths of
> a or b. So RetVal cannot be of type t_My_Complex_Type. I did the
> following and it is compiling fine.
Well it depends on just how much precision you think you need in the
calculation. I'm guessing that 32 bits would've been enough. The range for
each of the elements of the complex type should be made to be large enough
to handle whatever range of complex numbers that you plan to be able to use.
That being the case, all that is needed then is to strip off the lower bits
of the result as shown below
RetVal.Real := (a.real * b.real - a.imag * b.imag)(a'range);
RetVal.Imag := (a.real * b.imag + b.real * a.imag)(a'range);
<snip>
> How do i simulate this? What should be the type of a and b in the
> simulation file. Should they be 64 bit vectors each ?
a and b need to be whatever width you need them to be to give you whatever
precision you need for your calculations. Whether that's 5 bits, 8 bits, 32
bits or something else I can't say since I don't know what precision you
need for your application.
Kevin Jennings
Article: 128081I'm trying to get the DCR interrupt controller working in EDK 9.1 with xil_kernel on a V4FX12. Hardware builds fine, but I'm not sure how to configure the software platform settings and so forth. In the PDF datasheet for dcr_intc, they make the following statement: "to use this core with EDK design tools, see solution record SR18804 for details". But I can't find any SR18804 on the xilinx web site. Does anybody know what this is? Has anyone had any experiences with using dcr_intc with xil_kernel and EDK? thanks, JeffArticle: 128082
On Jan 14, 8:51 pm, Jeff Cunningham <j...@sover.net> wrote: > I'm trying to get the DCR interrupt controller working in EDK 9.1 with > xil_kernel on a V4FX12. Hardware builds fine, but I'm not sure how to > configure the software platform settings and so forth. In the PDF > datasheet for dcr_intc, they make the following statement: "to use this > core with EDK design tools, see solution record SR18804 for details". > But I can't find any SR18804 on the xilinx web site. Does anybody know > what this is? Has anyone had any experiences with using dcr_intc with > xil_kernel and EDK? http://www.xilinx.com/support/answers/18804.htm may be the record in question, but there isn't much there... (found by selecting a random answer record and changing the number in the url. xilinx search is getting better, but isn't there yet) alan nishiokaArticle: 128083
Jim, I am sorry if I sounded cold and aloof. I did not realize that "jg" is Jim Granville. If I had, I would have given the same answer, but in a much more personable and friendly tone. This newsgroup needs all the warmth it can get, and I was amiss. Sorry PeterArticle: 128084
I would suggest not using the propossed functions unless you are required to. Unless those functions have been donated by a synthesis company they are highley unlikely to be supported when you need to synthesize to gates. "FPGA" <FPGA.unknown@gmail.com> wrote in message news:113ff161-5e90-43f8-9c06-7da9ca92db65@s12g2000prg.googlegroups.com... > Hello all, > > I am trying to use some of the proposed functions by IEEE which are > still awaiting approval. > http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/float_pkg_c.vhdl > > I am getting the following errors > **Error: C:/Modeltech_pe_edu_6.3c/examples/util_top.vhd(58): Library > ieee_proposed not found. > ** Error: C:/Modeltech_pe_edu_6.3c/examples/util_top.vhd(59): > (vcom-1136) Unknown identifier "ieee_proposed". > ** Error: C:/Modeltech_pe_edu_6.3c/examples/util_top.vhd(60): > (vcom-1136) Unknown identifier "ieee_proposed". > ** Error: C:/Modeltech_pe_edu_6.3c/examples/util_top.vhd(67): VHDL > Compiler exiting > > I have copied the zip file vhdl-200x-pkgs_18 available at > http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/files.html. I now > have a folder vhdl-200x-pkgs_18 which is the unzipped version. How do > I include this as a library? I have renamed the folder to > ieee_proposed and it still gives me the same errors. > > I am using ModelsimPE Student Edition 6.3c > > ThanksArticle: 128085
Hello all, In my recent projects, I was using the V4 device (quite a huge one) and it required two 32MB Platform Flash to configure. To generate the corresponding MCS file, I pulled in two 32M in Impact GUI which as a result automatically generated the mcs and shared it in 2 labelled mcs0(100% used) and mcs1(33% used). Now when I wanted to program them on the board, during the boundary scan, it found the 2 PROMs on the board but however I was not sure in which order should i load the mcs (mcs0 to the left and mcs1 to the right one or the other way). Though I have the schematic, I could not figure out much except that that 2 PROMs are connected in daisy chain along with the FPGA. Ofcourse by trial and error I figured out (thanks to the working code), I was wondering if some of you could share your thoughts as well. Thanks in advance, Venkat.Article: 128086
Hi, Make sure that your test program both works in simulation and on target since you will need to go back and forth between them. Create small assembler programs that test one feature (instruction) each and make them self-checking. You could make your programs to light one of two led to show if that program succeeded or not. This way you can run them in simulation and on a board. Then it's just a large labour of writing all programs for all features that you want to test. Göran "pg4100" <pg4100@yahoo.co.uk> wrote in message news:fmfqhm$a86$1@aioe.org... > Hi > > I have implemented a RISC architecure and RTL simulation in Modelsim works > fine. So the next step would be to run this architecture on an > FPGA and see if it still outputs the correct results. So far my only idea > is go use Chipscope to connect to the core and then try to read out > the register contents as soon as the computation of the program has > finished. Until now I just used Chipscope to debug simple design where > I just had debugg one output value and not a set of registers. > > Are their maybe other approaches that I could use to see if the sythesized > core does the same as the simulated one? > > Would be thankful for other ideas > > Thanks!Article: 128087
"FPGA" <FPGA.unknown@gmail.com> wrote in message news:113ff161-5e90-43f8-9c06-7da9ca92db65@s12g2000prg.googlegroups.com... > Hello all, > > I am trying to use some of the proposed functions by IEEE which are > still awaiting approval. > http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/float_pkg_c.vhdl > .. > > I am using ModelsimPE Student Edition 6.3c I am not sure about the Student Edition but in the commercial PE version (I use 6.3d) these packages are already supplied as standard. Have a look in your <your_mti_installation_dir>\vhdl_src\floatfixlib\ directory. In my PE version they are compiled into floatfixlib: Library floatfixlib; use floatfixlib.float_pkg.all; signal A32,B32:float(8 downto -23); signal Y32 : float(8 downto -23); A32 <= "01000000110100000000000000000000" ; -- 6.5 B32 <= to_float(3.23, B32); -- size using B32 Y32 <= A32 + B32 ; These are great libraries and very easy to use. The only problem is that the waveform doesn't have an option to display them properly. Hans www.ht-lab.com > > ThanksArticle: 128088
On 14 Jan, 21:04, Ann <thakkar.an...@gmail.com> wrote: > I am trying to write a sunction for complex multiplication of 2 > complex numbers > > function complex_multiply(a : signed; b: signed; c : signed; d: > signed) return signed; > (a + bi)(c + di) = [ac - bd] + [ad + bc]i. > > I am not sure on how I would return the real and imaginary part of the > result. As per my understanding functions can return only one value. > How do i represent the inputs and outputs? I want to write code in > VHDL to be implemented on an FPGA. Note that you can save a multiplier: ac-bd = a(c-d) + d(a-b) ad+bc = b(c+d) + d(a-b) and if (c,d) is a constant, you can precompute (c-d) and (c+d). PontusArticle: 128089
Peter Alfke wrote: > Jim, I am sorry if I sounded cold and aloof. I did not realize that > "jg" is Jim Granville. > If I had, I would have given the same answer, but in a much more > personable and friendly tone. > This newsgroup needs all the warmth it can get, and I was amiss. > Sorry > Peter No problems, I am roaming (as you can probably guess) and so I am forced to use Google groups. A klunkier interface than what I am used to and it does obfuscate the poster ID more than my usual news reader. -jgArticle: 128090
On Jan 15, 4:19 am, MikeShepherd...@btinternet.com wrote: > >Ask a question that someone can answer as opposed to simply a question > >that you can ask and you may get better help. > > Thanks for bouncing this poor question. If badly-posed and off-topic > questions were more often rejected, those who would post them might > stop first to think about how to ask, to think where to ask it and to > let us know their own thoughts so far. When the last is omitted, I > wonder if they've given it any thought at all (those whose first > reaction to any problem is to throw up their hands and cry "Help!"). > > Mike You are right guys. I am sorry. I actual thought how to connect fpgas with different operating voltage. For example if one is 3 and other 1.5V but I read yesterday more about all, and I see that there is relay many things I have to consider. I see now how much this question was poor. I am sorry again.Article: 128091
"Zorjak" <Zorjak@gmail.com> wrote in message news:77e177dc-2c4b-48ee-a6d4-f26d6c308d77@21g2000hsj.googlegroups.com... > > You are right guys. I am sorry. I actual thought how to connect fpgas > with different operating voltage. For example if one is 3 and other > 1.5V but I read yesterday more about all, and I see that there is > relay many things I have to consider. I see now how much this question > was poor. I am sorry again. Hi Zorjak, Ah well, no harm done, at least you fixed your problem. Can I suggest you Google CB3T ? This family of voltage translation parts may be of interest to you. You also might like to have a look at this link. http://catb.org/~esr/faqs/smart-questions.html It might help keep the grumpy old farts on here, of which I proudly count myself a member, a little happier. But not much. Cheers, Syms.Article: 128092
May I ignore this warning? WARNING:Route:436 - The router has detected an unroutable situation for one or more connections. The router will finish the rest of the design and leave them as unrouted, The cause of this behavior is either an issue with the placement or unroutable placement constraints. To allow you to use FPGA editor to isolate the problems, the following is a list of (up to 10) such unroutable connections: Unroutable signal: GLOBAL_LOGIC0 pin: system_i/PCI_Bridge/PCI_Bridge/PCI_CORE_V5_generate.pci_core/ IDELAYCTRL_4.XPCI_IDC3_MapLib_replicate11/REFCLK Unroutable signal: GLOBAL_LOGIC0 pin: system_i/PCI_Bridge/PCI_Bridge/PCI_CORE_V5_generate.pci_core/ IDELAYCTRL_4.XPCI_IDC0/REFCLK Unroutable signal: GLOBAL_LOGIC0 pin: system_i/PCI_Bridge/PCI_Bridge/PCI_CORE_V5_generate.pci_core/ IDELAYCTRL_4.XPCI_IDC1/REFCLK Unroutable signal: GLOBAL_LOGIC0 pin: system_i/PCI_Bridge/PCI_Bridge/PCI_CORE_V5_generate.pci_core/ IDELAYCTRL_4.XPCI_IDC2/REFCLKArticle: 128093
On Jan 15, 1:21 pm, "Symon" <symon_bre...@hotmail.com> wrote: > "Zorjak" <Zor...@gmail.com> wrote in message > > news:77e177dc-2c4b-48ee-a6d4-f26d6c308d77@21g2000hsj.googlegroups.com... > > > > > You are right guys. I am sorry. I actual thought how to connect fpgas > > with different operating voltage. For example if one is 3 and other > > 1.5V but I read yesterday more about all, and I see that there is > > relay many things I have to consider. I see now how much this question > > was poor. I am sorry again. > > Hi Zorjak, > Ah well, no harm done, at least you fixed your problem. Can I suggest you > Google CB3T ? This family of voltage translation parts may be of interest to > you. > > You also might like to have a look at this link.http://catb.org/~esr/faqs/smart-questions.html > It might help keep the grumpy old farts on here, of which I proudly count > myself a member, a little happier. But not much. > > Cheers, Syms. Thank you very much, Syms Like I said every help used to me. I will surely see this things Thanks again ZoranArticle: 128094
Slight correction to previous post. Instead of
RetVal.Real := (a.real * b.real - a.imag * b.imag)(a'range);
RetVal.Imag := (a.real * b.imag + b.real * a.imag)(a'range);
It should be
RetVal.Real := (a.real * b.real - a.imag * b.imag)
(a.real'range);
RetVal.Imag := (a.real * b.imag + b.real * a.imag)
(a.imag'range);
KJ
Article: 128095
-jg wrote:
> ... I am forced to use Google groups. A klunkier interface
> than what I am used to and it does
> obfuscate the poster ID more than my usual news reader.
My favorite news service is
http://news.individual.net/
It works well at home or through firewalls.
It's 10 euro a *year*, and well worth it
for the trouble-free service from anywhere.
Thunderbird is has excellent support
for news accounts and it's free.
http://www.mozilla.com/thunderbird/
-- Mike Treseler
Article: 128096On Jan 15, 5:25 am, axalay <axa...@gmail.com> wrote: > May I ignore this warning? > > WARNING:Route:436 - The router has detected an unroutable situation > for one or more connections. The router will finish > the rest of the design and leave them as unrouted, The cause of > this behavior is either an issue with the placement > or unroutable placement constraints. To allow you to use FPGA > editor to isolate the problems, the following is a list > of (up to 10) such unroutable connections: > Unroutable signal: GLOBAL_LOGIC0 pin: > system_i/PCI_Bridge/PCI_Bridge/PCI_CORE_V5_generate.pci_core/ > IDELAYCTRL_4.XPCI_IDC3_MapLib_replicate11/REFCLK > Unroutable signal: GLOBAL_LOGIC0 pin: > system_i/PCI_Bridge/PCI_Bridge/PCI_CORE_V5_generate.pci_core/ > IDELAYCTRL_4.XPCI_IDC0/REFCLK > Unroutable signal: GLOBAL_LOGIC0 pin: > system_i/PCI_Bridge/PCI_Bridge/PCI_CORE_V5_generate.pci_core/ > IDELAYCTRL_4.XPCI_IDC1/REFCLK > Unroutable signal: GLOBAL_LOGIC0 pin: > system_i/PCI_Bridge/PCI_Bridge/PCI_CORE_V5_generate.pci_core/ > IDELAYCTRL_4.XPCI_IDC2/REFCLK No, not if you want to get a bitstream. You have a problem with how you are dealing with the IDELAYCTRL blocks. It has been a while since I dealt with the IDELAYCTRL blocks in our designs and this is from memory so the details may be a bit off. I am also using the V4s so it may be different for the V5. First go back and reread the IDELAY section of the V5 documentation. On the V4, there was two options on how we could deal with the IDELAY controllers. We could either instantiate all of them, or either one or none of them (I don't remember which) and let the tools deal with the rest. By all of them, I mean every one of them in the FPGA, not just every one that you are using. From your UCF, it looks like you are using four of the IDELAYCTRL blocks. My guess about the problem you are having is that you have instantiated and placed those four, and not done anything about the other IDELAYCTRL blocks in the FPGA and the tools are unhappy about that. If that is the case, instantiate all of the IDELAYCTRL blocks in the FPGA. But like I said, it has been a while since I had to deal with this so reread the IDELAY section of the V5 documentation with this suggestion in mind. Regards, John McCaskill www.FasterTechnology.comArticle: 128097
I am looking at the Xilinx Ahead tools. I was told that there will be a "light" version included in the next release of ISE. If you have used these tools with the more recent ISE, Synplify, or other, I would be very interested in reading what your experiences were/are. ThanksArticle: 128098
Thanks for your feedback Goeran, the simlation in the Modelsim works fine. I have a PCI card, so the LEDS approach sounds good but I have already written some kind of libraray with different applications and I wanna see if they also work on the FPGA and not only in the simulation. So I was thinking of having the program counter as my trigger, so when the end is reached then I wanna somehow read out the values of the register with Chipscope. Or each time the program counter changes I read out the values of the Registers to see if the results are as expected and could so also immediately identify the instructions that have caused problems. SO far i have just debugged a simple counter with the chipscope so I hope the approach with the RISC also works as I have just described. Göran Bilski wrote: > Hi, > > Make sure that your test program both works in simulation and on target > since you will need to go back and forth between them. > > Create small assembler programs that test one feature (instruction) each and > make them self-checking. > You could make your programs to light one of two led to show if that program > succeeded or not. > > This way you can run them in simulation and on a board. > > Then it's just a large labour of writing all programs for all features that > you want to test. > > Göran > > "pg4100" <pg4100@yahoo.co.uk> wrote in message news:fmfqhm$a86$1@aioe.org... >> Hi >> >> I have implemented a RISC architecure and RTL simulation in Modelsim works >> fine. So the next step would be to run this architecture on an >> FPGA and see if it still outputs the correct results. So far my only idea >> is go use Chipscope to connect to the core and then try to read out >> the register contents as soon as the computation of the program has >> finished. Until now I just used Chipscope to debug simple design where >> I just had debugg one output value and not a set of registers. >> >> Are their maybe other approaches that I could use to see if the sythesized >> core does the same as the simulated one? >> >> Would be thankful for other ideas >> >> Thanks! > >Article: 128099
Downloading Bitstream onto the target board ********************************************* impact -batch etc/download.cmd Linux ist SuSE 9.2 Starte impact ... Release 8.2.02i - iMPACT I.34 Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. // *** BATCH CMD : setMode -bs // *** BATCH CMD : setCable -port auto AutoDetecting cable. Please wait. Connecting to cable (Parallel Port - parport0). Connecting to cable (Parallel Port - parport1). Connecting to cable (Parallel Port - parport2). Connecting to cable (Parallel Port - parport3). Connecting to cable (Usb Port - USB21). Checking cable driver. Overriding Xilinx file <> with local file </usr/local/eda/xilinx/edk_82i/bin/lin/> Cable connection failed. Cable autodetection failed. Done! At Local date and time: Tue Jan 15 14:49:29 2008 make -f system.make bits started... make: Nothing to be done for `bits'. Done! At Local date and time: Tue Jan 15 14:49:35 2008 make -f system.make download started... ********************************************* Downloading Bitstream onto the target board ********************************************* impact -batch etc/download.cmd Linux ist SuSE 9.2 Starte impact ... Release 8.2.02i - iMPACT I.34 Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. // *** BATCH CMD : setMode -bs // *** BATCH CMD : setCable -port auto AutoDetecting cable. Please wait. Reusing 7806C421 key. Reusing FC06C421 key. Connecting to cable (Parallel Port - parport0). Reusing 7906C421 key. Reusing FD06C421 key. Connecting to cable (Parallel Port - parport1). Reusing 7A06C421 key. Reusing FE06C421 key. Connecting to cable (Parallel Port - parport2). Reusing 7B06C421 key. Reusing FF06C421 key. Connecting to cable (Parallel Port - parport3). Reusing A006C421 key. Reusing 2406C421 key. Connecting to cable (Usb Port - USB21). Checking cable driver. Overriding Xilinx file <> with local file </usr/local/eda/xilinx/edk_82i/bin/lin/> Cable connection failed. Reusing B406C421 key. Reusing 3806C421 key. Reusing B506C421 key. Reusing 3906C421 key. Reusing B606C421 key. Reusing 3A06C421 key. Reusing B706C421 key. Reusing 3B06C421 key. Cable autodetection failed. Done!
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