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On Jan 17, 1:39 pm, Philipp <Philip...@hotmail.com> wrote: > Hi > > I have an VHDL core that is sythesizeable with the following tools > > Synopsys Design Compiler > Cadence Encounter RTL Compiler > > Until now I was using XST for sythesis and it seems when I try to run > sythesis for the VHDL core with XST I get a bunch of errors. The > convenient thing with Xilinx was the Chipscope which allows the on-chip > debugging. So I wonder if the tools mentioned at the beginning also > support this kind of on-ship debugging? Or could I sythesise the design > with the ICON and ILA with the Synopsis or Cadence RTL compiler and then > use CHIPscope. Does anyone have tried that? > > Many thanks > Philipp There is nothing to synthesize for chipscope icon and ila cores. You instantiate them as black boxes and the netlists for the cores will get pulled in during ngdbuild. Cheers, Jim http://home.comcast.net/~jimwu88/toolsArticle: 128176
> There is nothing to synthesize for chipscope icon and ila cores. You > instantiate them as black boxes and the netlists for the cores will > get pulled in during ngdbuild. Makes sense, could give that a go! Hope it will work ;)Article: 128177
> Do you have Xilinx .libs for DC or RC? No, at the moment I am just using the Xilinx stuff. Depends from whom (Xilinx or DC/RC) I could get this libs? hope they are for free. For what exactly do I need them?Article: 128178
On Jan 16, 10:22 am, austin <aus...@xilinx.com> wrote: > G. > > How one starts the configuration process is a different problem that how > the device after configuration, starts up. > > The first problem is often caused by people "not trusting" the internal > Power On Reset circuits in the FPGA: bad. We spend an immense amount > of time making sure the POR circuits work under all sequences, and all > ramps from 2us to 50ms. Mess with this, and then you have to do all the > engineering for three power supplies to make it work at least as well as > we already did. Not a smart move. Why would anyone want to re-invent > this wheel? > > After the product has loaded the configuration, and has completed the > start-up sequence, then everything is in a known state, so a reset isn't > even required (it is implicit in the starting values you placed in the > registers in your VHDL or verilog code, and was part of the loaded > bitstream). > > If at some time later, you want to return to a 'known good state', which > we will call "reset" for no better reason than it describes the action > you want to take, then the applications note (or the old Tech X) details > all kinds of ways to do this, that work. > > Austin No offense, but after being burned by power-on reset(s) in chips more than a few times, it's very difficult for me to trust them. Some may call this superstition, others may call it experience. I prefer that the system come out of reset when *I* want, not when it thinks it's ready. $.02, G.Article: 128179
<ghelbig@lycos.com> wrote in message news:f58dbc55-6061-4f25-a999-61975f1fc570@v67g2000hse.googlegroups.com... > > No offense, but after being burned by power-on reset(s) in chips more > than a few times, it's very difficult for me to trust them. Some may > call this superstition, others may call it experience. > > I prefer that the system come out of reset when *I* want, not when it > thinks it's ready. > > $.02, > G. > Hi G., Do you have any specific details of reset problems for any of the number of designs you refer to where the problem was the FPGA's not loading reliably? I'm sure we'd all like to avoid that if possible, and could benefit from your experience. Thanks, Syms.Article: 128180
Philipp wrote: > Hi > > I have an VHDL core that is sythesizeable with the following tools > > Synopsys Design Compiler > Cadence Encounter RTL Compiler > > Until now I was using XST for sythesis and it seems when I try to run > sythesis for the VHDL core with XST I get a bunch of errors. The > convenient thing with Xilinx was the Chipscope which allows the on-chip > debugging. So I wonder if the tools mentioned at the beginning also > support this kind of on-ship debugging? Or could I sythesise the design > with the ICON and ILA with the Synopsis or Cadence RTL compiler and then > use CHIPscope. Does anyone have tried that? I'll admit that if you are doing debugging, then instantiating the cores in your HDL design seems to be the hard way (but maybe that is just me). Have you tried the core inserter instead? It inserts the ILA post synthesis, so it doesn't matter what synthesis tool you use. If you have tried the inserter, what is it that you prefer about instantiating into the HDL code. I find using the core inserter a quick and flexible process.Article: 128181
On Jan 17, 11:43 am, Uncle Noah <nk...@skiathos.physics.auth.gr> wrote: > On Jan 17, 5:59 am, Amal <akhailt...@gmail.com> wrote: > > > Does anyone have a copy of Forte Design (CynApps) opensource Cynlib? > > > I appreciate if you can send me a copy. > > -- Amal > > Hi > > i have this one: cynlib.1.2.1.source.tar.gz (3,876,003bytes) > > I'll check the licensing issues (if i can pass it to you or not). But, > first of all, is this version OK for you? > > And what about the company, it might be best if you asked them about > the legality of this. > > Kind regards > Nikolaos Kavvadias I searched the net. They released this and another tool to open source community a long time ago. There is no mention of this anywhere on their web site anymore. Whatever version is fine. Not looking for any specific version really. -- AmalArticle: 128182
G, I understand. I understand perfectly. I spent years designing telecom equipment, and for much of that time, I didn't trust anything, except my own power on reset solution. Along came a Dallas Semiconductor POR chip, and I used it everywhere. One place I never used it, was for the PROG pin of the FPGA: the FPGA (Xilinx, of course) was much better at "knowing" when it was OK to power on, and configure (or power down, and go stupid -- tristate all IO). I mention this, because when I would force the FPGA to do my bidding, the product then failed the power on tests that AT&T had specified. I passed when I let the FPGA do what it was designed to do. That is my experience, AustinArticle: 128183
> I'll admit that if you are doing debugging, then instantiating the cores > in your HDL design seems to be the hard way (but maybe that is just me). > Have you tried the core inserter instead? It inserts the ILA post > synthesis, so it doesn't matter what synthesis tool you use. > > If you have tried the inserter, what is it that you prefer about > instantiating into the HDL code. I find using the core inserter a quick > and flexible process. Yes I tried using it but it didnt work :D. With the core inserter I never got any data back from the device whereas with the direct instantiation in the code it was working. Rather strange...probably I should give it a go again, i think i have done something wrong with the clock connection!Article: 128184
> lwip is not an adequate replacement for xilnet in all cases. First, > lwip requires some form of OS kernel and timers, while xilnet can be > used in stand-alone applications. As a result, xilnet is more suitable > for smaller projects where code space is a constraint. However, > reading the license for the code, it appears that you can keep using > it even though it is deprecated, you will just need to turn it into a > user library. > > I'm working on several projects on ML boards where we simply don't > have enough code space left for lwip and xilkernel, so this is the > approach we are taking. Sure, that is a valid approach. However, you might also want to check the RAW mode of lwIP. It does not require a kernel, and it should be small. However you have to rewrite your app using the RAW API. The benefit is ofcourse that you get the improvements/bug fixes in lwIP. RAW mode is also significantly better performing (close to 100 Mbps TCP throughput w/ xps_ll_temac). /SivaArticle: 128185
On Jan 17, 1:43 pm, Amal <akhailt...@gmail.com> wrote: > On Jan 17, 11:43 am, Uncle Noah <nk...@skiathos.physics.auth.gr> > wrote: > > > > > On Jan 17, 5:59 am, Amal <akhailt...@gmail.com> wrote: > > > > Does anyone have a copy of Forte Design (CynApps) opensource Cynlib? > > > > I appreciate if you can send me a copy. > > > -- Amal > > > Hi > > > i have this one: cynlib.1.2.1.source.tar.gz (3,876,003bytes) > > > I'll check the licensing issues (if i can pass it to you or not). But, > > first of all, is this version OK for you? > > > And what about the company, it might be best if you asked them about > > the legality of this. > > > Kind regards > > Nikolaos Kavvadias > > I searched the net. They released this and another tool to open > source community a long time ago. There is no mention of this > anywhere on their web site anymore. > > Whatever version is fine. Not looking for any specific version > really. > > -- Amal The Wayback machine has the cynapps web site in the archives, but the couple of pages that I clicked on the download button brought up a registration form. You might take a deeper look at that site and see if you can find it in one of the archives: http://web.archive.org/web/*/http://www.cynapps.com You might also try asking on the geda mail list. A search turned up several people on one of those list discussing it that are still participating in the list. Maybe one of them has a copy of it. See : http://geda.seul.org/mailinglist/index.html and use the search function on cynlib. Good luck, John McCaskill www.FasterTechnology.comArticle: 128186
Allan Herriman wrote:
> ... Until then, I will use cheap, reliable, external
> reset generator devices.
Well said.
Industrial systems have to just work.
Reminds me of a certain fireworks controller.
Let's see, ah yes:
"It stopped, they rebooted it,"
"They rebooted it a second time." But it didn't restart."
http://blogs.king5.com/archives/2008/01/computer_glitch.html
-- Mike Treseler
Article: 128187On 2008-01-17, Philipp <Philipp_G@hotmail.com> wrote: > > Yes I tried using it but it didnt work :D. With the core inserter I > never got any data back from the device whereas with the direct > instantiation in the code it was working. When using the inserter you may need to set preserve or keep attributes on the signals you want to instrument. Otherwise the optimizations done by your tools may cause problems. The most obvious would be one that is optimized out of the design, but there are more subtle pitfalls. Also don't forget to set 'trigger same as data' or hook up a real trigger. The first time I set one up in EDK I didn't realize the checkbox for that was off-screen (reachable only with a scrollbar) and didn't understand why I could never trigger... -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/Article: 128188
The Xilinx .libs for DC or RC....is the list of lowlevel Xilinx gates.
When you synthesize you map the rtl to a set of "low" level gates specified
by a library. Say you had RTL code
wire [31:0] a,b,c;
assign {carry,c}=a+b;
If the library had a 32bit adder as a low level cell. It would map 1 cell.
If the library has 4bits adders as the primitive it maps 4 of those.
The xilinx library would tell the synthesizer which primitives to map to.
Xilinx would normally provide the library. The price is variable. some
companies will give it away to potential bulk chip buyers. But since Xilinx
has a synthesizer and contracts with Mentor, they are liekly to charge for
it.
"Philipp" <Philipp_G@hotmail.com> wrote in message
news:fmo878$fnl$2@aioe.org...
>> Do you have Xilinx .libs for DC or RC?
>
> No, at the moment I am just using the Xilinx stuff. Depends
> from whom (Xilinx or DC/RC) I could get this libs? hope they are for free.
> For what exactly do I need them?
Article: 128189Is there a complete manual for iMPACT ISE9.2 ? Can't find it. Brad Smallridge AiVisionArticle: 128190
Dwayne Dilbeck wrote: > > Xilinx would normally provide the library. The price is variable. some > companies will give it away to potential bulk chip buyers. But since Xilinx > has a synthesizer and contracts with Mentor, they are liekly to charge for > it. Xilinx has never charged for synthesis or simulation libraries. It's been a long time since I've seen any requests for Synopsys synthesis so I had to go check to see if we were still shipping these with each release. I can see that they are still in the 9.2i release tree under $XILINX/synopsys but the files might only be included with the Solaris and Linux installers. If you don't have them contact your FAE or the hotline and they should be able to get you a copy. BTW, I wouldn't expect to see these around much longer. There must not have been any demand to add Synopsys DC support for Virtex-5 so that is definitely missing. Ed McGettigan -- Xilinx Inc.Article: 128191
linnix wrote: > On Jan 17, 12:03 am, recoder <kurtulmeh...@gmail.com> wrote: >> Dear All, >> As an assignment I have to design a CCD Sensor based FPGA digital >> Camera. However, the Camera will be exposed to XRAY (It will be placed >> behind an Imaging Intensifier). Does anybody know how XRAY affects the >> electronic circuits (The CCD Sensor and the FPGA ). What type of noise >> should I expect and what should I do to prevent it. >> Thanks in advance > > Is it internal flash or external flash? If anything, flash would be > the weakest link. I would think an old fashioned tube camera with tube amplifiers would be the most radiation resistant.Article: 128192
That is good to hear. I tend to be pestimistic about getting things for free. When NuHorizons finally ships my Spartan 3e kit to me I will look for the files. I will see how well RC can handle the mapping. I will probably have to file some bugs with Cadence. "Ed McGettigan" <ed.mcgettigan@xilinx.com> wrote in message news:fmoksq$j0q1@cnn.xsj.xilinx.com... > Dwayne Dilbeck wrote: >> >> Xilinx would normally provide the library. The price is variable. some >> companies will give it away to potential bulk chip buyers. But since >> Xilinx has a synthesizer and contracts with Mentor, they are liekly to >> charge for it. > > Xilinx has never charged for synthesis or simulation libraries. > > It's been a long time since I've seen any requests for Synopsys synthesis > so I had to go check to see if we were still shipping these with each > release. I can see that they are still in the 9.2i release tree under > $XILINX/synopsys but the files might only be included with the Solaris > and Linux installers. > > If you don't have them contact your FAE or the hotline and they should > be able to get you a copy. BTW, I wouldn't expect to see these around much > longer. There must not have been any demand to add Synopsys DC support > for Virtex-5 so that is definitely missing. > > Ed McGettigan > -- > Xilinx Inc.Article: 128193
Philipp wrote: >> I'll admit that if you are doing debugging, then instantiating the >> cores in your HDL design seems to be the hard way (but maybe that >> is just me). Have you tried the core inserter instead? It inserts >> the ILA post synthesis, so it doesn't matter what synthesis tool >> you use. >> >> If you have tried the inserter, what is it that you prefer about >> instantiating into the HDL code. I find using the core inserter a >> quick and flexible process. > > Yes I tried using it but it didnt work :D. With the core inserter I > never got any data back from the device whereas with the direct > instantiation in the code it was working. Rather strange...probably I > should give it a go again, i think i have done something wrong with > the clock connection! Yep, something strange there. I've not ever had that problem. It has always worked fine. Ben Jackson wrote: > > When using the inserter you may need to set preserve or keep > attributes on the signals you want to instrument. Otherwise the > optimizations done by your tools may cause problems. The most > obvious would be one that is optimized out of the design, but there > are more subtle pitfalls. Yes, sometimes the exact signal I want to instrument is not there. And especially, if I stick for example a debug counter in the code that I want to instrument, I have to have it go somewhere or else it will get optimized out before I run the inserter.Article: 128194
I am driving 'jtagd' on a Linux box remotely from a PC to access a ByteBlasterII cable. The client and server PCs are both plenty fast (the server was my desktop until recently and did the programming directly). The JTAG programming over the network via the remote cable works, but it's muuuch slower than the local access. Passive slave programming (of an FPGA) seems reasonably fast. Active serial programming of a flash part is slow, though. The only network between them is a 100Mbps switch. I don't see a cable speed option anywhere. Is there anything I can do to speed this up? I'm going to look into running the programmer on the Linux side, but it would be nice to drive it all from Quartus on the PC. -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/Article: 128195
Dwayne Dilbeck wrote: > That is good to hear. I tend to be pestimistic about getting things for > free. When NuHorizons finally ships my Spartan 3e kit to me I will look for > the files. > > I will see how well RC can handle the mapping. I will probably have to > file some bugs with Cadence. > I think by RC you mean the Cadence Encounter RTL Compiler. If this is correct then I do not know of any libraries that were ever developed for this tool for FPGA synthesis. My previous comments were with respect to the Synopsys Design Compiler (DC) tool. I did check the Synopsys DC libraries and there is one for Spartan-3E, but there isn't anything for the newer Spartan-3A families. At one time (early 1990s) there was a very active set of Synopsys DC users and it had good FPGA support, but now the focus is on Synplicity Synplify, Mentor Precision RTL and vendor owned tools. Ed McGettigan -- Xilinx Inc.Article: 128196
Hi,
I'm a systems engineer and not the direct FPGA guy, but I'm fairly
involved in the implementation of my DSP algorithm on our Virtex-II
platform. Our current code uses the 2's complement block IP core. Today,
when I went searching on the Xilinx site to refresh my memory on how it
works (we did the initial coding 3+ years ago), I couldn't find it anywhere!
Did it get replaced by something else, or should I just use the numeric
package to convert to that format?
Thanks,
Marty
Article: 128197In article <209b3e90-d60e-42b5-84fa- 9e2ce075c10e@s8g2000prg.googlegroups.com>, sci.electronics.design, kurtulmehtap@gmail.com says... > Dear All, > As an assignment I have to design a CCD Sensor based FPGA digital > Camera. However, the Camera will be exposed to XRAY (It will be placed > behind an Imaging Intensifier). Does anybody know how XRAY affects the > electronic circuits (The CCD Sensor and the FPGA ). What type of noise > should I expect and what should I do to prevent it. > Thanks in advance CMOS doesn't like X-Rays much. There is a failure mechanism that tends to harden CMOS SRAM bits in one direction. I'm not sure how bad it gets though. -- KeithArticle: 128198
On 2008-01-18, Marty Ryba <martin.ryba.nospam@verizon.net> wrote: > I'm a systems engineer and not the direct FPGA guy, but I'm fairly > involved in the implementation of my DSP algorithm on our Virtex-II > platform. Our current code uses the 2's complement block IP core. Today, > when I went searching on the Xilinx site to refresh my memory on how it > works (we did the initial coding 3+ years ago), I couldn't find it anywhere! I've lost track of how many times I've searched for something on Xilinx's website that I *knew* was there without ever finding it. Most likely it still exists. It may not show up in the tool (by default) if it's deprecated. -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/Article: 128199
On Jan 17, 8:47 pm, Ben Jackson <b...@ben.com> wrote: > On 2008-01-18, Marty Ryba <martin.ryba.nos...@verizon.net> wrote: > > > I'm a systems engineer and not the direct FPGA guy, but I'm fairly > > involved in the implementation of my DSP algorithm on our Virtex-II > > platform. Our current code uses the 2's complement block IP core. Today, > > when I went searching on the Xilinx site to refresh my memory on how it > > works (we did the initial coding 3+ years ago), I couldn't find it anywhere! > > I've lost track of how many times I've searched for something on > Xilinx's website that I *knew* was there without ever finding it. > Most likely it still exists. It may not show up in the tool (by > default) if it's deprecated. > > -- > Ben Jackson AD7GD > <b...@ben.com>http://www.ben.com/ You hit the nail right on the head Ben, As of at least 9.1, the twos complementer is still in CORE Generator, but it has been deprecated for a while. To make it show up, select "All Versions incl. Obsolete" in the Show pull down menu in the tool bar at the top of the CORE Generator window. Regards, John McCaskill, www.FasterTechnology.com
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Compare FPGA features and resources
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