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Hello, I am trying to use the PECL inputs of a ProASIC Plus APA075 device, independently of the PLL blocks. The two PECL inputs (one on each side of this device) can be used independently of the PLL by assigning the GLPE or GLPEMIB macros, which use a global line each. But I'm also using both PLL blocks on the device, although I only require one output from each it seems that I have to assign a global resource to both of the PLL outputs. This is a problem since there are only 4 globals available, so the PLL's use them all and I don't have any spare for the PECL inputs. Can anyone advise whether it is possible to have both PLL's and both PECL inputs available at the same time? Mark LeshaArticle: 128201
I tried synthesizing a Systemverilog-RTL file in Quartus-II 7.2sp1.
The synthesis-engine doesn't seem to understand SVA (systemverilog
assertion)
syntax.
property prop_x;
@ ( posedge clk ) // disable iff (rstn)
(!$stable( comb_sm )) |-> ##1 (comb_sm !== BADSTATE);
endproperty : prop_x
ap_x: assert property( prop_x );
For now, I've simply put some `ifdef/`endif blocks around the SVA,
to conditionally remove it from Quartus-II compile.
Now, I assumed SVA was standardized along with the rest of Systemverilog,
and synthesis-tools are supposed to ignore the SVA-constructs -- i.e.
ugly `ifdef should not be needed.
Is this understanding correct?
For example, does Synopsys Design Compiler and Cadence RTL Compiler
require `ifdef blocks around SVA?
Article: 128202I'm pretty annoyed that the iMPACT program (download/program) is unusable under Vista/64. When will this be fixed? Also, Xilinx EDK 9.2 doesn't run under Vista (32 or 64-bit.) (The Cygwin component seems to be the culprit.)Article: 128203
As other people have pointed out, you can specify the initial-state of any flop, using a VHDL-attribute, or a Verilog 'initial' statement. Verilog-2001 version: wire my_one_shot_reset; // active-high reset (fires once at FPGA-config/powerup!) reg [15:0] my_one_shot_ctr = 0; always @ ( posedge clk ) begin : always_my_one_shot_ctr if ( my_one_shot_ctr < 10000 ) my_one_shot_ctr <= my_one_shot_ctr + 1; end // : always_my_one_shot_ctr assign my_one_shot_reset = (my_one_shot_ctr < 10000); "jey" <jey_1453@hotmail.com> wrote in message news:fml0qo$qnd$1@aioe.org... > Hi > > I have a very basic question. I have a design that has a clk and reset > input. I know that I have to connect the clk and the reset inputs to > the corresponding pins of the FPGA. But how can i now assert a reset > signal for 8ns to my design to initialise some values? I dont think that I > have a reset button ;). can I specify this maybe somehow in the UCF file? > > thanks for help! > JeyArticle: 128204
Hello, I have a design where I need a couple of 16-bit shift registers, two bits wide. According to the "Virtex-5 FPGA User Guide", it should be possible to implement one of these in just one LUT6 in a SLICEM (as long as one doesn't need the extra flip-flop in that slice). XST does recognise them as 16-bit shift registers, but always uses two LUTs for them, instantiating two SRLC32Es. Does anyone know how to create them in one slice? Thanks, winscattArticle: 128205
I am trying to generate a CPLD pad file using a dummy module and ucf. Translate process gives the following error: ERROR:NgdBuild:605 - logical root block 'test' with type 'test' is unexpanded. Symbol 'test' is not supported in target 'xbr'. Any idea what might be wrong??Article: 128206
>I mention this, because when I would force the FPGA to do my bidding, >the product then failed the power on tests that AT&T had specified. I >passed when I let the FPGA do what it was designed to do. What did the power look like for the case that failed? I'd expect an external power-watcher chip would get OR-ed in with the internal logic so you would have the best of both worlds. What went wrong? Actually, now that I look more carefully, things get complicated. Is figure 23 in the Spartan3 data sheet the whole picture? Are there restart paths not shown to handle power-not-good (as detected by internal logic) while configuring? What if PROG goes active during configuration? What happens if INIT goes low after configuration has started? It gets forced low by a bad CRC. It would be handy if that restarted the whole thing if you are configuring several devices on a chain. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 128207
On Jan 17, 8:04 pm, Siva Velusamy <siva.velus...@xilinx.com> wrote: > > lwip is not an adequate replacement for xilnet in all cases. First, > > lwip requires some form of OS kernel and timers, while xilnet can be > > used in stand-alone applications. As a result, xilnet is more suitable > > for smaller projects where code space is a constraint. However, > > reading the license for the code, it appears that you can keep using > > it even though it is deprecated, you will just need to turn it into a > > user library. > > > I'm working on several projects on ML boards where we simply don't > > have enough code space left for lwip and xilkernel, so this is the > > approach we are taking. > > Sure, that is a valid approach. However, you might also want to check > the RAW mode of lwIP. It does not require a kernel, and it should be > small. However you have to rewrite your app using the RAW API. > > The benefit is ofcourse that you get the improvements/bug fixes in lwIP. > RAW mode is also significantly better performing (close to 100 Mbps TCP > throughput w/ xps_ll_temac). > > /Siva Thanks every one ! I have a good view of both options now and have got go ahead from my PM to go the lwip way.Article: 128208
Hi, in the help file of Xpower it says that the standard report contains: A standard report contains: Power Summary Thermal Summary Decoupling Network Summary Footer BUT ... my report dosent display the Decoupling Network Summary but all others summarys ... is there something which needs to be activated before it prints the Decoupling Network Summary ?Article: 128209
Hi, Could anyone explain why FIFO is difficult to implement in FPGA and ASIC? and how is FIFO implemented in FPGA and ASIC. Thanks, WeiArticle: 128210
>Could anyone explain why FIFO is difficult to implement in FPGA and >ASIC? and how is FIFO implemented in FPGA and ASIC. Where did you read that a FIFO is difficult to implement?Article: 128211
On Jan 17, 3:07 pm, John McCaskill <jhmccask...@gmail.com> wrote: > On Jan 17, 1:43 pm, Amal <akhailt...@gmail.com> wrote: > > > > > On Jan 17, 11:43 am, Uncle Noah <nk...@skiathos.physics.auth.gr> > > wrote: > > > > On Jan 17, 5:59 am, Amal <akhailt...@gmail.com> wrote: > > > > > Does anyone have a copy of Forte Design (CynApps) opensource Cynlib? > > > > > I appreciate if you can send me a copy. > > > > -- Amal > > > > Hi > > > > i have this one: cynlib.1.2.1.source.tar.gz (3,876,003bytes) > > > > I'll check the licensing issues (if i can pass it to you or not). But, > > > first of all, is this version OK for you? > > > > And what about the company, it might be best if you asked them about > > > the legality of this. > > > > Kind regards > > > Nikolaos Kavvadias > > > I searched the net. They released this and another tool to open > > source community a long time ago. There is no mention of this > > anywhere on their web site anymore. > > > Whatever version is fine. Not looking for any specific version > > really. > > > -- Amal > > The Wayback machine has the cynapps web site in the archives, but the > couple of pages that I clicked on the download button brought up a > registration form. You might take a deeper look at that site and see > if you can find it in one of the archives: > > http://web.archive.org/web/*/http://www.cynapps.com > > You might also try asking on the geda mail list. A search turned up > several people on one of those list discussing it that are still > participating in the list. Maybe one of them has a copy of it. See : > > http://geda.seul.org/mailinglist/index.html > > and use the search function on cynlib. > > Good luck, > > John McCaskillwww.FasterTechnology.com Thanks John. I checked all that. And those messages are way too old. I had no success finding it yet. -- AmalArticle: 128212
"Wei Wang" <camwwang@gmail.com> wrote in message news:cba45c89-9489-47fb-a36c-e67dbc43ca05@e6g2000prf.googlegroups.com... > Hi, > > Could anyone explain why FIFO is difficult to implement in FPGA and > ASIC? and how is FIFO implemented in FPGA and ASIC. > > Thanks, > Wei Wei, According to WHOIS, you're posting from Advanced RISC Machines Ltd. I bet there are several people in your office who can answer that for you. Perhaps no one in the office will talk to you? Googling fifo+fpga returns 400k hits. Adding I'm+a+little+teapot to the search gets you down to 7. HTH., Syms. p.s. http://catb.org/~esr/faqs/smart-questions.html p.p.s. http://en.wikipedia.org/wiki/Eternal_SeptemberArticle: 128213
On Jan 18, 4:56 am, kislo <kisl...@student.sdu.dk> wrote: > Hi, in the help file of Xpower it says that the standard report > contains: > A standard report contains: > > Power Summary > > Thermal Summary > > Decoupling Network Summary > > Footer > > BUT ... my report dosent display the Decoupling Network Summary but > all others summarys ... is there something which needs to be activated > before it prints the Decoupling Network Summary ? What device are you targeting? I don't think the Decoupling network is supported on devices older than V4.Article: 128214
On Jan 17, 5:16 pm, "Brad Smallridge" <bradsmallri...@dslextreme.com> wrote: > Is there a complete manual for iMPACT > ISE9.2 ? Can't find it. > > Brad Smallridge > AiVision In the new software manuals (.pdf) I only see a link to iMPACT help, not a manual. It's online in some fancy Java format. http://toolbox.xilinx.com/docsan/xilinx92/help/iseguide/mergedProjects/plugin_imp/plugin_imp.htm Regards, GaborArticle: 128215
Hi, does anyone know if it is possible to create a Chipscope Analyzer Project including alle Trigger and Data Port names from a cdc-file? Greetz HelmutArticle: 128216
"Helmut" <helmut.leonhardt@gmail.com> wrote in message news:e101a493-71c7-4b44-8ade-51e82936bdc8@l32g2000hse.googlegroups.com... > Hi, > > does anyone know if it is possible to create a Chipscope Analyzer > Project including alle Trigger and Data Port names from a cdc-file? > > Greetz Helmut Hi Helmut, Start the analyser. Go File -> import blah blah blah.. HTH., Syms.Article: 128217
On Jan 18, 3:14 am, akshat <mailtoaks...@gmail.com> wrote:
> I am trying to generate a CPLD pad file using a dummy module and ucf.
>
> Translate process gives the following error:
>
> ERROR:NgdBuild:605 - logical root block 'test' with type 'test' is
> unexpanded.
> Symbol 'test' is not supported in target 'xbr'.
>
> Any idea what might be wrong??
Is your top level module written in Verilog? If this is the
case and all the module contains is the port list, i.e. no
"code", the tools assume that it is a black box and look for
an underlying .ngc or EDIF file. Usually to get through
ngdbuild ("translate") you need to have at least an assign
statement in the module.
Article: 128218On Thu, 17 Jan 2008 21:14:46 -0500, in sci.electronics.basics, krw <krw@att.bizzzzz> gurgled: >In article <209b3e90-d60e-42b5-84fa- >9e2ce075c10e@s8g2000prg.googlegroups.com>, sci.electronics.design, >kurtulmehtap@gmail.com says... >> Dear All, >> As an assignment I have to design a CCD Sensor based FPGA digital >> Camera. However, the Camera will be exposed to XRAY (It will be placed >> behind an Imaging Intensifier). Does anybody know how XRAY affects the >> electronic circuits (The CCD Sensor and the FPGA ). What type of noise >> should I expect and what should I do to prevent it. >> Thanks in advance > >CMOS doesn't like X-Rays much. There is a failure mechanism that >tends to harden CMOS SRAM bits in one direction. I'm not sure how >bad it gets though. THE HORRORS! Someone need to tell Agilent & Teradyne ASAP. Millions of boards a year are run through their x-ray fault detection systems. Digital boards quite often with memory.Article: 128219
I managed to use the "Import" button instead of open. It works now. Greetz HelmutArticle: 128220
Hi, I am looking for a paper that compare the achieved performance from implementing general a N taps FIR filter on CPU, GPU, FPGA and ASIC i googled not much in return thanksArticle: 128221
Wei Wang wrote: > Could anyone explain why FIFO is difficult to implement in FPGA and > ASIC? and how is FIFO implemented in FPGA and ASIC. With dual port memory, like many FPGAs and ASICs have it isn't difficult to implement. It isn't for beginners, but it isn't that hard, either. In FPGA they are implemented with dual port memory and two counters. Also, logic to compare the counters to generate the full and empty status lines. -- glenArticle: 128222
On Jan 18, 3:54 pm, MikeShepherd...@btinternet.com wrote: > >Could anyone explain why FIFO is difficult to implement in FPGA and > >ASIC? and how is FIFO implemented in FPGA and ASIC. > > Where did you read that a FIFO is difficult to implement? "FIFO" is a broad term and can be either simple or complicated. For starters, a synchronous (single clock), small FIFO should be easy to understand and implement. See, for example: http://www.asic-world.com/examples/vhdl/syn_fifo.html FIFOs get more complex than that. They can have different clocks for read and write, they can be large and require a dual port memory block, etc. Start with the simple, advance to the more sophisticated when you need. EliArticle: 128223
"glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message news:r9WdnaStJ_4cJw3anZ2dnUVZ_ozinZ2d@comcast.com... > Wei Wang wrote: > >> Could anyone explain why FIFO is difficult to implement in FPGA and >> ASIC? and how is FIFO implemented in FPGA and ASIC. > > With dual port memory, like many FPGAs and ASICs have > it isn't difficult to implement. It isn't for beginners, > but it isn't that hard, either. > > In FPGA they are implemented with dual port memory and > two counters. Also, logic to compare the counters to > generate the full and empty status lines. > > -- glen > Hi Glen, My favourite FPGA FIFO design is described in XAPP291. The counters' storage elements are part of the dual port RAM. "Their advantage is in using only one clock load." Cheers, Syms.Article: 128224
On Fri, 18 Jan 2008 07:09:47 -0800 (PST), Eli Bendersky <eliben@gmail.com> wrote: >On Jan 18, 3:54 pm, MikeShepherd...@btinternet.com wrote: >> >Could anyone explain why FIFO is difficult to implement in FPGA and >> >ASIC? and how is FIFO implemented in FPGA and ASIC. >> >> Where did you read that a FIFO is difficult to implement? > >"FIFO" is a broad term and can be either simple or complicated. For >starters, a synchronous (single clock), small FIFO should be easy to >understand and implement. See, for example: >http://www.asic-world.com/examples/vhdl/syn_fifo.html > >FIFOs get more complex than that. They can have different clocks for >read and write, they can be large and require a dual port memory >block, etc. > >Start with the simple, advance to the more sophisticated when you >need. > >Eli I'm not planning to start at all. I was asking a question of the original poster.
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