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On Tue, 25 Sep 2007 09:26:28 +0100, Martin Thompson <martin.j.thompson@trw.com> wrote: >icegray <icegray@gmail.com> writes: > >> Hi, >> I'm looking for a control unit (plc, control card, control module) for >> construction equipment (excavator). It should contain digital and >> analog inputs and digital outputs. Any body have experience or know >> brand (like as axiomatic) about this subject? > >If the rest of the group can excuse the advert, is this any use? > >http://www.conekt.net/docs/CAN-click1%20flexible%20ECU.pdf > >It's not FPGA based, so may be off-topic :-) Cool. I was trying to work out how to tell the OP that the FPGA part would be absolutely the least of his worries; anyone who goes into the automotive (or industrial, or medical) electronics business thinking that the logic is the hard part will be in for some very nasty surprises :-) Is there a comp.arch.automotive newsgroup where you can see posts like this? hi group, i trid to use conkt flexible ecu to mak activ suspensn control for my 2000HP monster truk project but am having not succes. pls help. first I conekted alternator to canbus but then smoak cam out of ecu so I discntcd it. then it work loose so I dril 1/2"hole thru ecu for fixing blot and now it is not working. pls explain how i cn implement kalman filter for suspensn opmization using this method. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 124501
Hi, There are various kinds of DRAM modules such as RIMM,SODIMM,UDIMM,MiniDIMM etc. How do they differ from each other. Can anybody through some light on this. Thanks in advance. Regards, SaiArticle: 124502
On Mon, 24 Sep 2007 13:08:37 -0700, icegray <icegray@gmail.com> wrote: >Hi, >I'm looking for a control unit (plc, control card, control module) for >construction equipment (excavator). It should contain digital and >analog inputs and digital outputs. Any body have experience or know >brand (like as axiomatic) about this subject? >Thanks all Looks like you're in the USA, but if you were in Western Europe then these folk might be able to help: http://www.zetacontrols.com/ (I'm not connected with them, but have been loosely associated with them in the distant past.) See also Martin Thompson's post. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 124503
Hello, i have a problem with my dcm modules. By changing of frequency the clock-out phase gets also changed. So I have found a xapp from xilinx which may help me (Active Phase Alignment xapp268). I have used this in my design, but i cant see some changes and shold be error free. Maybe somebody can see the mistake: ---------------------------------------------------------------------------= -------------------- clk_bufg : bufg port map(i =3D> clkdcm, o =3D> clk); clkx4_bufg : bufg port map(i =3D> clkx4dcm, o =3D> clkx4); clkx4not_bufg : bufg port map(i =3D> clkx4notdcm, o =3D> clkx4not); clk_ibufg : ibufgds_lvpecl_33 port map(i =3D> clkin_p, iB =3D> clkin_n, o =3D> clkint); attribute DFS_FREQUENCY_MODE of dcm_clk : label is "HIGH"; attribute CLKOUT_PHASE_SHIFT of dcm_clk : label is "VARIABLE"; attribute PHASE_SHIFT of dcm_clk : label is "-255"; attribute CLKFX_DIVIDE of dcm_clk : label is dcm_clk_d; attribute CLKFX_MULTIPLY of dcm_clk : label is dcm_clk_m; attribute DUTY_CYCLE_CORRECTION of dcm_clk : label is "TRUE" ; attribute CLKDV_DIVIDE of dcm_clk : label is "4" ; attribute DLL_FREQUENCY_MODE of dcm_clk : label is "HIGH"; dcm_clk : dcm --pragma translate_off generic map ( CLKFX_MULTIPLY =3D> dcm_clk_m_udsim, CLKFX_DIVIDE =3D> dcm_clk_d_udsim, CLKDV_DIVIDE =3D> 4.0, CLKOUT_PHASE_SHIFT =3D> "VARIABLE", PHASE_SHIFT =3D> 160) --pragma translate_on port map ( clkin =3D> clkint, CLKFB =3D> clkx4, DSSEN =3D> low, PSINCDEC =3D> psincdec_tx, PSEN =3D> psen_tx, PSCLK =3D> psclk_tx, RST =3D> rx_dcm_lock_loss, CLK0 =3D> clkx4dcm, CLK90 =3D> open, clk180 =3D> clkx4notdcm, CLK270 =3D> open, CLK2X =3D> open, CLK2X180 =3D> open, CLKDV =3D> clkdcm, CLKFX =3D> open, CLKFX180 =3D> open, LOCKED =3D> clk_locked, PSDONE =3D> psdone_tx, STATUS =3D> open); .=2E.. .=2E.. ph_shift_tx : phase_control_full_range port map( enable =3D> high, monclkin =3D> clkint, rxclkin =3D> clk, -- clk ctlclk =3D> clkdcm, lockedin =3D> clk_locked, rst =3D> tx_dcm_lock_loss, psdone =3D> psdone_tx, forceup =3D> low, forcedown =3D> low, dcm_div_2_used =3D> dcm_div_2_used, -- nope k =3D> const_offset, -- the same as for rx side lockedout =3D> dpclocked_tx, psincdec =3D> psincdec_tx, psen =3D> psen_tx, psclk =3D> psclk_tx, binout =3D> binout_tx); -------------------------------------- The Design runs in DDR Mode, by changing of frequency from 300 MHz to 370 Mhz the phase jups ut to 180=B0.Article: 124504
Jonathan Bromley <jonathan.bromley@MYCOMPANY.com> writes: > Is there a comp.arch.automotive newsgroup > where you can see posts like this? > > hi group, > i trid to use conkt flexible ecu to mak activ suspensn control > for my 2000HP monster truk project but am having not succes. > pls help. first I conekted alternator to canbus but then > smoak cam out of ecu so I discntcd it. then it work loose > so I dril 1/2"hole thru ecu for fixing blot and now it is > not working. pls explain how i cn implement kalman filter > for suspensn opmization using this method. Stop it - now I have tea on my keyboard :-) Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 124505
"Symon" <symon_brewer@hotmail.com> wrote in message news:fd9hdo$s11$1@aioe.org... > "Jon Elson" <elson@wustl.edu> wrote in message > news:46F7FE10.90107@wustl.edu... >> >> If you try to do this with an FPGA FF, you will spend all day with >> exotic lab gear trying to get one event. >> >> Jon >> > Hi Jon, > Thanks for your post, but sorry, but that last statement is bollocks. It's > easy to get metastable events in an FPGA. X, A, L or otherwise. Email > Xilinx and ask about Virtex 4 fifos. Or search through this newsgroup's > archive. Or do the maths. > HTH., Syms. > Hi Jon, Sorry about that reply, re-reading it, I sound a little aggressive, dunno what came over me. Anyway, have a quick shufty at this. http://www.xilinx.com/bvdocs/appnotes/xapp094.pdf It's Peter from Xilinx's metastability experiments. Perhaps it will change your mind? Best regards, Syms.Article: 124506
Ordered a license for Quartus a month ago. Order is processed, rep says she needs NIC ID and host ID from PC, we explain that a new PC is on order and we will need to license software to old machine now, then move it. She says we have to wait. Okay, not good as a project is already behind schedule, but can live with that. New computer comes in. Get rep to clarify that host ID means volume serial number. Provide it. No response. Wait four days and ask what happened - told that LICENSE CANNOT BE ISSUED FOR AT LEAST ANOTHER FOUR DAYS. What the ???? I have work to do here, and you guys can't email me a tiny text file ? Going back to Xilinx... project is already halfway working on their eval board, which has a chip supported by their web version.Article: 124507
cs_posting@hotmail.com wrote:
> Ordered a license for Quartus a month ago. Order is processed, rep
> says she needs NIC ID and host ID from PC, we explain that a new PC is
> on order and we will need to license software to old machine now, then
> move it. She says we have to wait.
Give them the existing NIC and change it later.
Or maybe start with the web version.
That doesn't need a license.
-- Mike Treseler
Article: 124508On Sep 25, 10:11 am, Mike Treseler <mike_trese...@comcast.net> wrote: > cs_post...@hotmail.com wrote: > > Ordered a license for Quartus a month ago. Order is processed, rep > > says she needs NIC ID and host ID from PC, we explain that a new PC is > > on order and we will need to license software to old machine now, then > > move it. She says we have to wait. > > Give them the existing NIC and change it later. > Or maybe start with the web version. > That doesn't need a license. > > -- Mike Treseler Web version can't compile for an EP2S60Article: 124509
Volume IDs and MACs can be changed on most computers. Volume IDs do not need to be unique. I had some fun with an Avnet representive when we tried to register 12 licenses to the same volume ID. They refused to do it so we registered only one license. Kolja Sulimma On 25 Sep., 15:51, cs_post...@hotmail.com wrote: > Ordered a license for Quartus a month ago. Order is processed, rep > says she needs NIC ID and host ID from PC, we explain that a new PC is > on order and we will need to license software to old machine now, then > move it. She says we have to wait. > > Okay, not good as a project is already behind schedule, but can live > with that. > > New computer comes in. Get rep to clarify that host ID means volume > serial number. Provide it. No response. Wait four days and ask what > happened - told that LICENSE CANNOT BE ISSUED FOR AT LEAST ANOTHER > FOUR DAYS. > > What the ???? > > I have work to do here, and you guys can't email me a tiny text file ? > > Going back to Xilinx... project is already halfway working on their > eval board, which has a chip supported by their web version.Article: 124510
Ever heard of a USB Ethernet Adapter ? They also have NIC ID's and are around =80 10.- in my local store. That's 10 minutes of engineering time. Karl.Article: 124511
On 24 Sep, 22:32, Kevin Neilson <kevin_neil...@removethiscomcast.net> wrote: > davew wrote: > > Has anyone got any example Verilog code for this? I'm currently using > > Quartus wizard generated code and wrapping it up in a Verilog module > > so I can use my own parameters instead of running the wizard each time > > I need a new variation (which is a complete pain). I thought that > > perhaps inferring the memory might yield better and more efficient > > results. > > > Ta. > > I have such a piece of code but it only works for Xilinx parts. (Which > you should use.) Most likely the synthesizer will not infer RAMs of > different port widths from a behavioral description. My code takes > Verilog parameters that are passed in and then uses 'generates' to > instantiate an array of the correct blockRAM primitives with the > primitive parameters set for asymmetric port widths if necessary. > You'll probably need to do something similar if you want an HDL > solution. I'm not sure why the tools don't support this yet. A > behavioral description of an asymmetric RAM is slightly awkward, but > definitely doable. > -Kevin Thanks, I haven't tried to infer because I wasn't sure how to tackle the Verilog for differing port widths. It can be done easily with the wizard, but this is cumbersome when it comes to writing a neat re-usable unit. Dave.Article: 124512
All I can find is a one-page specification of "Kingston KVR100X64C2/128", but I do not know about the input and output interface of this SDRAM, e.g., what are the input and output signals, and how the input and output signals are wired into each Synchronous DRAM (Infineon HYB39S128800CT-8) module. Many thanks, -WeiArticle: 124513
On Sep 25, 6:51 am, cs_post...@hotmail.com wrote: > Ordered a license for Quartus a month ago. Order is processed, rep > says she needs NIC ID and host ID from PC, we explain that a new PC is > on order and we will need to license software to old machine now, then > move it. She says we have to wait. > > Okay, not good as a project is already behind schedule, but can live > with that. > > New computer comes in. Get rep to clarify that host ID means volume > serial number. Provide it. No response. Wait four days and ask what > happened - told that LICENSE CANNOT BE ISSUED FOR AT LEAST ANOTHER > FOUR DAYS. > > What the ???? > > I have work to do here, and you guys can't email me a tiny text file ? > > Going back to Xilinx... project is already halfway working on their > eval board, which has a chip supported by their web version. Mike, Sorry to hear you had a bad experience. I would like to help now if I can. First, Quartus II Subscription Edition includes a free 30-day trial (no license needed - just download and install). This should get you up an running with compiling a 2S60. Second, our sales team should be able to cut you an additional 60-day evaluation license. I'm happy to do so now - just email me your NIC ID. I can also help you with license you purchased. Happy to get you up and runnning today. Jordon Inkeles Altera Software Marketing jinkeles@altera-nospam-.com <remove the -nospam->Article: 124514
On Mon, 24 Sep 2007 13:12:32 -0500, Jon Elson <elson@wustl.edu> wrote: >> >> So far I've only seen talk of violated setup times in relation with the >> metastability problem. No problems with hold times? >> >> I've done a resonable amount of logic designs (TTL/CPLD/FPGA), but never >> have run into this problem. Maybe because most of my designs run fairly >> slow and I always like to clock everithing through dff's anyway. :-) >> > >If you want to actually see metastability, it is bets to start with a >slow technology, like the 74HC74. You could try a *really* slow technology like latching relays. Metastability resolution times are long, as long as... well, I had one once that didn't recover at all, with its outputs (contacts) stuck in an intermediate state. I assume this was due to friction. Regards, AllanArticle: 124515
Just interesting, how often some company is able to develope their own RISC soft-core processor for their needs, without any need to publish that fact or reveal any details?Article: 124516
sai wrote: > Hi, > > There are various kinds of DRAM modules such as > RIMM,SODIMM,UDIMM,MiniDIMM etc. How do they differ from each other. > Can anybody throw some light on this. http://www.micron.com --- Joe Samson Pixel VelocityArticle: 124517
On Sep 25, 7:51 pm, drop...@gmail.com wrote: > Just interesting, how often some company is able to develope their own > RISC soft-core processor for their needs, without any need to publish > that fact or reveal any details? I believe this is reasonable when the soft-core is not supposed to be marketed independently of a larger product (which is its context of use). It is also reasonable to worry since it your design effort :) You can safely publish, anytime you wish, following patents filed (of course) and the product being pushed in the market. Then, it is reasonable to publish stuff from the internals in order to increase momentum among the users of the product. This is from my own working experience, even though i'm mostly on my own here (in pswrokwstaina Greece). Regards Nikolaos KavvadiasArticle: 124518
On Sep 25, 8:51 am, Wei Wang <camww...@gmail.com> wrote: > All I can find is a one-page specification of "Kingston > KVR100X64C2/128", but I do not know about the input and output > interface of this SDRAM, e.g., what are the input and output signals, > and how the input and output signals are wired into each Synchronous > DRAM (Infineon HYB39S128800CT-8) module. Many thanks, -Wei Hi, Go to Infineon or Micron, or Samsung to search for similar SDRAM chips. Kingston is not a chip manufacture, but a DIMM manufacture. All SDRAM chips are almost same with Micron having the tighest requirements. You may print Micron 128800CT-8 SDRAM to see if there is a document over there. Maybe they are all out of date. WengArticle: 124519
On 25 Sep, 17:51, drop...@gmail.com wrote: > Just interesting, how often some company is able to develope their own > RISC soft-core processor for their needs, without any need to publish > that fact or reveal any details? I know there are quite a few companies that have done this. JonArticle: 124520
jinkeles@hotmail.com wrote:
> Mike,
> Sorry to hear you had a bad experience.
No, was "cs_posting" not me.
My quartus licenses work fine.
-- Mike Treseler
Article: 124521On Sep 25, 2:12 pm, Weng Tianxiang <wtx...@gmail.com> wrote: > On Sep 25, 8:51 am, Wei Wang <camww...@gmail.com> wrote: > > > All I can find is a one-page specification of "Kingston > > KVR100X64C2/128", but I do not know about the input and output > > interface of this SDRAM, e.g., what are the input and output signals, > > and how the input and output signals are wired into each Synchronous > > DRAM (Infineon HYB39S128800CT-8) module. Many thanks, -Wei > > Hi, > Go to Infineon or Micron, or Samsung to search for similar SDRAM > chips. > > Kingston is not a chip manufacture, but a DIMM manufacture. > > All SDRAM chips are almost same with Micron having the tighest > requirements. > > You may print Micron 128800CT-8 SDRAM to see if there is a document > over there. Maybe they are all out of date. > > Weng A good source for DIMM data is JEDEC. On their website, jedec.org, you can find standard connections for all standard DIMM types. If you know the type of chip and number of chips on your module you can generally narrow down the choices to one JEDEC standard. Their website is a little hard to navigate, but the search feature generally gets you to the information you need, and all of the standards include reference schematics so you can see the chip connections. HTH, GaborArticle: 124522
>Just interesting, how often some company is able to develope their own >RISC soft-core processor for their needs, without any need to publish >that fact or reveal any details? What do you mean by "RISC soft-core processor"? It's fairly easy to make an ALU unit. It's also fairly easy to make a simple CPU if you use wide instructions to simplify decoding. If your code is small enough to fit in local ROMs, then you don't need anything fancy like caches. You may not even need a memory interface. We used to call that sort of stuff microcode. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 124523
I am looking for open source software for logic minimization (a la espresso) targeted to a lookup table based architecture that can take advantage of six inputs LUTs (as you can imagine I have in mind a LUT6/Virtex 5 implementation). Is there such a beast? thanks much -ArrigoArticle: 124524
jinkeles@hotmail.com wrote: >On Sep 25, 6:51 am, cs_post...@hotmail.com wrote: >> Ordered a license for Quartus a month ago. Order is processed, rep >> says she needs NIC ID and host ID from PC, we explain that a new PC is >> on order and we will need to license software to old machine now, then >> move it. She says we have to wait. >> >> Okay, not good as a project is already behind schedule, but can live >> with that. >> >> New computer comes in. Get rep to clarify that host ID means volume >> serial number. Provide it. No response. Wait four days and ask what >> happened - told that LICENSE CANNOT BE ISSUED FOR AT LEAST ANOTHER >> FOUR DAYS. >> >> What the ???? >> >> I have work to do here, and you guys can't email me a tiny text file ? >> >> Going back to Xilinx... project is already halfway working on their >> eval board, which has a chip supported by their web version. > >Mike, > >Sorry to hear you had a bad experience. I would like to help now if I >can. First, Quartus II Subscription Edition includes a free 30-day >trial (no license needed - just download and install). This should get >you up an running with compiling a 2S60. Second, our sales team should >be able to cut you an additional 60-day evaluation license. I'm happy >to do so now - just email me your NIC ID. I can also help you with >license you purchased. Lesson learned today: Stupid licensing schemes cost customers. When I buy software I leave it in the shrink wrap if it has a dongle or lmserver and download the cracked version from internet and use that instead. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nl
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