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OK, the questions apply primarily to FPGA synthesis (Altera Quartus fitter for StratixII and HardCopyII), but I'm interested in feedback regarding all EDA tools in general. Context: I'm suffering some long Quartus runtimes on their biggest StratixII and second-biggest HardCopyII device. Boss has given me permission to order a new desktop/workstation/server. Immediate goal is to speed up Quartus, but other long-term value considerations will be taken into account. True or false? -------------------- Logic synthesis (analyze/elaborate/map) is mostly integer operations? Place and Route (quartus_map) is mostly double-precision floating- point? Static Timing Analysis (TimeQuest) is mostly double-precision floating- point? RTL simulation is mostly integer operations? SDF / gate-level simulation is mostly double-precision floating-point? AMD or Intel? ------------------- Between AMD & Intel's latest multicore CPUs, - Which offers the best integer performance? - Which offers the best floating-point performance? Specific models within the AMD/Intel family? Assume cost is no object, and each uses its highest-performing memory interface, but disk access is (necessary evil) over a networked drive. (Small % of total runtime anyway.) Multi-core, multi-processor, or both? 32-bit or 64-bit? Linux vs. Windows? >2GB of RAM? --------------------------------------------------------------------------------------------------------------------------------- Is Quartus (and the others) more efficient in any one particular environment? I prefer Linux, but the OS is now secondary to pure runtime performance (unless it is a major contributor). Can any of them make use of more than 2GB or RAM? More than 4GB? Useful limit on the number of processors/cores? Any specific box recommendations? Thanks a gig, jjArticle: 122401
On Jun 7, 9:47 pm, motty <mottobla...@yahoo.com> wrote: > I have upgraded to EDK 9.1 and am trying togeneratethe HDLsimulationfiles. I have successfully compiled both the ISE libraries > and the EDK libraries. They live in C:\xilinx_sim_libs and C: > \xilinx_sim_libs\EDK respectively. I have set the EDK to point to > both those paths. Whenver I click 'Simulation->GenerateSimulation > HDL Files' I get the following pop up error: > > "ISE Sim Library:XPScan not get library information from the path <C: > \xilinx_sim_libs>. Please make sure it contains the libraries > compiled with the same simulator and HDL as you set in the GUI, and > with current EDK/ISE version." > > If I click OK, it takes me to the 'Edit->Preferences' screen. The > paths are set up correctly. I fiddled around with those paths > (switched '/' to '\') and I got the same error but for both the ISE > libraries and the EDK libraries. I recompiled the ISE libs making > sure that the correct simulator path was chosen. I did this in GUI b/ > c it won't work directly from the EDK. Anyways, everything seems in > order. This worked for EDK 8.2. I think I got the same error, but > the software continued generating the sim files correctly. > > Any advice? We just had the same problem with the EDK 9.1 GUI. To get around this, we ran simgen from the command line with all the options found in _xps/simgen.opt and added our system.mhs at the end, as well as a - log option. Good luck! Dani.Article: 122402
On Jul 26, 6:19 pm, jjohn...@cs.ucf.edu wrote: > > True or false? > -------------------- > Logic synthesis (analyze/elaborate/map) is mostly integer operations? Yes. > Place and Route (quartus_map) is mostly double-precision floating- > point? I don't know why they would use floating point if they don't have to. > Static Timing Analysis (TimeQuest) is mostly double-precision floating- > point? I seriously doubt it. I don't see a need for floating point there when delays can use scaled integers. > RTL simulation is mostly integer operations? Yes. > SDF / gate-level simulation is mostly double-precision floating-point? No, or at least not in any implementation I am familiar with. All the delays are scaled up so that integers can be used for them. In simulation (assuming something with state-of-the art performance), the CPU operations themselves are not very important anyway. It is not compute-bound, it is memory-access-bound. What you need is big caches and fast access to memory for when the cache isn't big enough. > Is Quartus (and the others) more efficient in any one particular > environment? I prefer Linux, but the OS is now secondary to pure > runtime performance (unless it is a major contributor). Can any of > them make use of more than 2GB or RAM? More than 4GB? 64-bit Linux can make use of more than 4GB of RAM. But don't use 64- bit executables unless your design is too big for 32-bit tools, because they will run slower on the same machine. > Useful limit on > the number of processors/cores? Most of these tools are not multi-threaded, so the only way you will get a speedup is if you have multiple jobs at the same time. Event- driven simulation in particular is not amenable to multi-threading, despite much wishful thinking for the last few decades.Article: 122403
On 26 Jul, 15:37, Chris Carlen <crcarleRemoveT...@BOGUSsandia.gov> wrote: > mk wrote: > > On Tue, 24 Jul 2007 13:25:33 -0700, Chris Carlen > > <crcarleRemoveT...@BOGUSsandia.gov> wrote: > > >>Petter Gustad wrote: > >>>Chris Carlen <crcarleRemoveT...@BOGUSsandia.gov> writes: > > >>>>Is there something wrong with my .vcd file, or Gtkwave? > >>Thanks for the reply. > > >>>Did you try to: > > >>>click on the + in the SST window > >>What is the SST window? Do you mean the zoom-in? > > > Let's get some layout decided. At the top left there is a window which > > says "VCD loaded succesfully[12] facilities..." right? You're also > > seeing a window which has a title "Signals" and the content "Time" at > > this point from what you're describing. Now below "VCD loaded ..." > > window and to the left of "Signals" window, you should see a window > > which has SST in its title with a '+' to the left of SST string. If > > you see this click on the '+' and you should see your hierarchy. If > > you don't see the SST window, it's possible that your GTK+ setup is > > broken and you don't the right GTK+ installed. > > Hi, and thanks for the reply! > > 1. I have the '"VCD loaded succesfully[12] facilities..."' > 2. I have the '"Signals" and the content "Time"' > > But, > > >you should see a window > >which has SST in its title with a '+' to the left of SST string. > > I don't see this! > > I think the conclusion is that my GTK+ might be screwed. This Suse > Linux has been known to have a shoddy GNOME installation at times. So > perhaps the libs are just old, or Suse tinkered with them and broke it. > > Thanks for the help. > > It isn't worth any more time at this point. I may try Windows, or may > just live with the text output from the Icarus simulator (which is usable). > > I'll try GtkWave again once I have a chance to update Linux. > > -- > Good day! > > ________________________________________ > Christopher R. Carlen > Principal Laser&Electronics Technologist > Sandia National Laboratories CA USA > crcarleRemoveT...@BOGUSsandia.gov > NOTE, delete texts: "RemoveThis" and > "BOGUS" from email address to reply. My version of GtkWave (3.81) doesn't show the Signal Search Tree (SST) window by default either. You can bring it up by selecting Signal Search Tree from the Search menu. Or you can use the shortcut Shift- Alt-T. When using GtkWave, I can't show up vhdl signals created from enumerated types such as state vectors. I'm think older versions of GtkWave did show enumerated types, but I'm not sure. Anyone else had this problem?Article: 122404
Eddie, What Mike is saying to you is that if your design is synchronous performing timing simulation on it is a waste of your time. /MikhailArticle: 122405
Hello Mike,
No. The reset wasn't the problem.
Here is the code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity message is
port(
clk : in std_logic;
row : in std_logic_vector(4 downto 0);
col : in std_logic_vector(5 downto 0);
char : out std_logic_vector(6 downto 0) );
end message;
architecture beh of message is
type message_type is array( 0 to 31 , 0 to 63) of character;
constant message : message_type :=(
" 0 ABCDEFGHIJKLMNOPQRSTUVWXYZ -------------------------------- 0",
" 1 ABCDEFGHIJKLMNOPQRSTUVWXYZ 0123456789 ----------------- 1",
" 2 2",
" 3 VERSION ai\ntsc\n60 ____________ ----- 3",
" 4 4",
" 5 abcdefghijklmnopqrstuvwxyz 5",
" 6 !@#$%^&*()_+{}:<>?~ AND HOW DO I DO DOUBLE QUOTE? 6",
" 7 -=;',./` 7",
" 8 8",
" 9 BRAD SMALLRIDGE 9",
"10 (c)2007 AiVision 10",
"11 11",
"12 12",
"13 13",
"14 14",
"15 3456789012345678901234567890123456789012345678901234567890 15",
"16 16",
"17 17",
"18 18",
"19 19",
"20 20",
"21 21",
"22 22",
"23 3456789012345678901234567890123456789012345678901234567890 23",
"24 24",
"25 25",
"26 26",
"27 27",
"28 28",
"29 29",
"30 30",
"31 3456789012345678901234567890123456789012345678901234567890 31" );
begin
msg_proc: process(clk)
variable pointer : natural;
variable char_val : character;
variable char_pos : natural;
variable m : integer;
variable n : integer;
begin
if(clk'event and clk='1') then
-- 2D array simulated OK but the synthesizer does not BRAM it
m := to_integer(unsigned(row));
n := to_integer(unsigned(col));
char_val := message(m,n);
-- Flattened -- in constant message, change the ending commas to ampersands
-- pointer := to_integer(unsigned(row))*64 + to_integer(unsigned(col));
-- char_val := message( pointer );
char_pos := character'pos(char_val);
char <= std_logic_vector(to_unsigned(char_pos, char'length));
end if;
end process;
end beh;
There is also some issue concerning multidimensional arrays with
this format (m,n) and this format (m)(n) that is a great mystery
to me.
Brad Smallridge
AiVision
Article: 122406hi, all: i install ise9.1 in my gentoo linux. i connect usb cable and run the impact. it displayer the error information : Connecting to cable (Usb Port - USB21). Checking cable driver. File version of /usr/local/xilinx/Xilinx91i/bin/lin/xusbdfwu.hex = 1027(dec), 0403. File version of /usr/share/xusbdfwu.hex = 1030(dec), 0406. WinDriver v9.01 Jungo (c) 1997 - 2007 Build Date: Jun 14 2007 X86 32bit 20:55:18. Cable PID = 0008. Max current requested during enumeration is 150 mA. Cable Type = 3, Revision = 0. write cmdbuffer failed 2000001B. Setting cable speed to 6 MHz. write cmdbuffer failed 2000001B. Cable connection established. Firmware version = 1030. CPLD file version = 0012h. CPLD version = 0012h. PROGRESS_END - End Operation. Elapsed time = 4 sec. Attempting to identify devices in the boundary-scan chain configuration...// *** BATCH CMD : Identify write cmdbuffer failed 2000001B. // *** BATCH CMD : identifyMPM write cmdbuffer failed 2000001B. why it was connect but cant write cmdbuffer?? anyone ideas?Article: 122407
Hi, I just overheard about a kind of standard lib component F/F, which are used to "smash" X-values at the module level boundary. This components are said to have a quality of either pushing "0" or "1" at the outputs instead of "x" or "X". I would like to request you all, to throw some light on this. As I searched in Google it did not result in any kind of convincing information. Please reply. AkhileshArticle: 122408
Hi,
I am facing a strenge problem in using Model Sim 6.2 code coverage
report generation CLI.
e.g.
I have a modular design, as shown:
device
|
|_ top
|
|_ H1
|
|_ H2.1
|_ H2.2
|
|_ H3.1
|_ H3.2
|_ H3.3
H1, H2.1/2, H3.1/2/3 are module instanciations.
I am interested in knowing the module level code coverage i.e. for
instances H2.1/2, which I expect to be consolidation of the code
coverage of the module instances with in H2.1 and H2.2 respectively.
However, MS 6.2 "vcover report" CLI gives is Design Unit (DU) level
code coverage i.e. code coverage on the ".v" file used for the module
and not for module instance.
The report of interest in visible in Workspace and is clearly
indicated in the workspace against each instance.
My point of interest is the code coverage which I can obtain from
workspace and not from DU.
I am not sure about any other version of MS.
Please help in this regard.
Akhil
Article: 122409On 2007-07-18, Jon Elson <elson@pico-systems.com> wrote: > Hmm, maybe I believed Xilinx's own material, which I think in > ise 5.2 or whatever said it would be the last release to support > the 5 V chips. Very interesting to hear that 7.1 handles them > also. What about 5 V Spartan? I do more of that then 9500 parts. ISE 9.1 also supports the XC9500-series. But the later ISE-versions seem to have some problems in regards to these CPLDs. I've bumped into a problem where the FSM extraction acted up for example: http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/bdf705bececca67/c354755faddc41f3?lnk=st&q=ehliar+xc9536&rnum=1#c354755faddc41f3 /AndreasArticle: 122410
> I've already talked to an Altera FAE and he seemded OK. The real test > is ofcourse supporting real design problems/questions. > > -- > Stef (remove caps, dashes and .invalid from e-mail address to reply by mail) Well he is waiting for you to really start designing ;-) Karl. PS: I do not drive an AlfaArticle: 122411
On Jul 27, 5:37 am, Subroto Datta <sda...@altera.com> wrote: > Hi X.Y, > > The Incremental Compilation flow currently does not allow the > imported .qxp to be "stamped" onto different instances. This is > coming. One workaround is to have a different HDL file and name for > each instance. Admittedly, this is not ideal but in many cases is an > easy solution. (If you're making changes on the top-level file, it's > painful to repeat in multiple files. But if the changes are in the > HDL files beneath that entity, then it all works smoothly after the > initial set-up.) > > One flow Iused often, mainly because it works and is easy, is the > pseudo-bottom up flow. This basically involves putting partitions on > the hierarchies that are in the same level as the one/s you are > interested in and set them to Empty(so they have no logic, but nothing > gets removed). I then work on the partitions I want with quick > compiles. Then, when I get what I want, I set that partition to post- > fit and either set the other partitions to Source or delete them > altogether(making everything else one big partition). It's quick and > easy without creating sub-projects, making sure their layout fits into > the top-level, etc. Also, in Q7.1 you can export a .qxp from sub > partitions, so you can always save off your results. This works with > multiple instances of the same thing, since they now have different > instances(and locations). > > What end goal are you using Incremental Compilation flow for? Are you > trying to reduce compile times, are you trying to preserve > performance, or something else? > > - Subroto Datta > Altera Corp. Thanks for your reply! My end goal is trying to preserve performance. In our project, I use one Cyclone II FPGA to process four groups of image signal which comes from four cameras. The processing algorithms of the four groups of image signal are all the same. As a result, I plan to build a subproject implementing the processing of one of the four signals and export it as a partition. Then, I build a top level project and import it four times. Certainly, I will do four different pin assignments for the four partitions. It appears that LogicLock can do it also, am I right?Article: 122412
Please bear in mind that this is only an 8-bit ripple-carry adder, and the tools are still quite crude, but I believe we now have the first-ever instance of a design being taken through a 100% open-source flow, all the way from verilog to blinking lights on a programmed device. Details are here: http://research.cs.berkeley.edu/project/slipway/ Again, it's nowhere close to production-ready, but there are already a lot of doors opening up: programmatic access to the inner PAR loop (ie incremental runs) plus partial reconfiguration is a very powerful combination. More to come. - a -- PGP/GPG: 5C9F F366 C9CF 2145 E770 B1B8 EFB1 462D A146 C380Article: 122413
On 2007-07-25, John Oyler <john.m.oyler@gmail.com> wrote: > I don't know that my fpga is capable (spartan 3e 100k), but I thought > I might like to try to do ethernet first. I remember finding a > tutorial weeks ago but forgot to bookmark it, where the instructions > had you hook up two io pins directly to an ethernet cable, and you > could hardcode an IP address into the chip and ping it. Does anyone > know of any like this, or even of the one I speak? (Might even have > been verilog, I forget). In addition, I've found the following lab material very helpful when I wrote some VHDL code to interact with a Ethernet PHY: http://www.sm.luth.se/~maglun/lab33/lab33.pdf /AndreasArticle: 122414
hi all, i have done the post place and route timing simulation for my design. i am getting the following warnings . there is a setup time voilation but can any one explain what this statment means Time: 4785 ps Iteration: 2 Instance: /sts3c_top_tb/dut/ deframer_inst_fifo_inst_bu236 # ** Warning: /X_SFF SETUP High VIOLATION ON SRST WITH RESPECT TO CLK; # Expected := 0.748 ns; Observed := 0.653 ns; At : 4.785 ns is that my data is arriving early than the expected ... can any one explain me what that warnings means and how can i make sure in my design to avoide this kind of warning .. that does this kind of warning do matter when i am loading my design into silicon. as my design is not working on the actual silicon. thanks .... regards kilArticle: 122415
Sylvain Munaut wrote: > Kevin Neilson wrote: >> Sylvain Munaut wrote: >>> Hello everyone, >>> >>> >>> I have a placed and routed .ncd file and I'd like to be able to >>> convert it back to a simple netlist. >>> It doesn't contain any "secured" core, so I can freely use all the >>> xilinx tools suite on it. But there is no "ncd2edif" ... >>> >>> I convert it to XDL then somehow parse it ... but in the xdl I have >>> the slice configuration, which means I would have to convert it to a >>> basic element (LUT/MUXF5/...) + interconnections first ... That's >>> gonna be quite painful to do. >>> >>> Does someone has a better idea/tool to do the job ? >>> >>> >>> Thanks, >>> >>> Sylvain >> Presumably you have the NGD which you used to create the NCD. Then you >> can use NDG2EDIF. > > No I don't ;) > > All I have recovered is the .ncd, the .bit, and all the .ngc except one ... > I'm hoping to be able to reconstruct my missing ngc by "isolating" it from > the rest in the ngc. > > > I tried netgen, that gives me a vhdl (or verilog file), but parsing it > is gonna be painful as well ;) > > > Sylvain If you use netgen with an .ncd netlist, you can only retrieve a post-mapped netlist, which is not synthesizable and usually does not contain any hierarchy any more. Also, it contains additional symbols for buffers and routing path delay. If you discover a method to translate the .xdl primitives (slices, iobs) back into an .edf let us know! -MarkusArticle: 122416
Hello Sean, thank You for Your help. Unfortunately, including the UNISIM source did not cure the problem. I tried the verilog and the VHDL version. Finally, I upgraded to the latest version of Precision (2006a3.24), which now knows the DCM_SP. I can compile the design normally, without any changes now. Best Regards, Markus Fras Sean Durkin schrieb: > Markus Fras wrote: >> It seems to me that Precision does not recognize Xilinx' DCM for Spartan >> devices. >> >> Do You have any ideas? > I haven't worked with Spartan devices, and I don't use Verilog, but I've > had problems with instantiating Xilinx primitives in VHDL without > declaring them first, i.e. I get the same error message as you do when I > just instantiate e.g. a BUFG out of the work library, without declaring > it first. > > The same applies in designs where I use the PicoBlaze... in the HDL for > the PicoBlaze, there are flipflops, shift registers and such > instantiated without being declared first, and I could never get that > synthesized with Precision at first. > > What I then did was add the source code for the UNISIM-library to my > synthesis project (in $XILINX/vhdl/src/unisims/unisim_VCOMP.vhd). Inside > this file are declarations for all Xilinx primitives, including the > DSP_SP. Just including this in the synthesis fixed it for me. > > HTH, > Sean >Article: 122417
"Brad Smallridge" <bradsmallridge@dslextreme.com> writes:
> Hello Mike,
> No. The reset wasn't the problem.
> Here is the code:
>
Can't help with the BRAM, but if you still need a double quote, you
need to double the double quote:
" 6 !@#$%^&*()_+{}:<>?~ "" <-------------DOUBLE QUOTE 6",
which makes the line look a bit weird by being one char longer than
the others!
Cheers,
Martin
--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html
Article: 122418michel.talon@gmail.com wrote: > Hi alls, > > I've a amazing problem in my virtex XC2V1000 design. > > I've verilog code which normaly should generate a D flipFlop with > preload ( and it did in functional simulation): > input [7:0] reset; > input [7:0] n_set; > input [7:0] d; > input clockIn; > output [7:0] out; > > reg [7:0] out_reg; > wire [7:0] out = out_reg; > wire trigSig = |(reset | ~(n_set)); > always@(posedge clockIn or posedge trigSig) > begin > if(trigSig) > out_reg = ~reset; > else > out_reg = d; > end I don't know the Virtex 2, but how on a virtex 4 I don't see how to implement that ... (unless reset is constant). But I may be missing something ... SylvainArticle: 122419
Hi, First, thanks a lot, you was right.. In fact, i don't use scope for the moment, I simulate only post translate simulation model. But what you said was verified, I've looked about my clock generation, and it comes from combinatorial logical block. So I decided to reclock my clock with a faster clock ( fast clock = 50MHz , my clock = 2 MHz ) to it prevent from glitchs. And it works fine ! Problems disappeared.. But, there is something I don't understand, why can I not seen the glitchs on the clock on my waveform viewer ? I simulate with a time unit of 100ps, and the clock seems to be clean.. Is it due to a simulator option ? thanks On 26 juil, 19:50, Peter Alfke <pe...@xilinx.com> wrote: > I suppose you have reflections on your clock input. Your scope may not > be fast enough to see these reflections of perhaps 1 to 3 ns duration. > There are several ways to solve this, depending on the internal clock > distribution, depending on your willingness to change the pc-board, > whether this is a one-off or a production design, etc. > But when you see a single toggle flip-flop misbehaving, you know that > you have to do something. > Peter Alfke, Xilinx ApplicationsArticle: 122420
In comp.arch.fpga, Karl <jack6910@gmail.com> wrote: >> I've already talked to an Altera FAE and he seemded OK. The real test >> is ofcourse supporting real design problems/questions. > > Well he is waiting for you to really start designing ;-) > > Karl. > > PS: I do not drive an Alfa Yes, I know he is. 8-) What do you drive? -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail)Article: 122421
Hi,
SRST signal changes its value to close in time to the active edge of clock
CLK.
It should be changed at least 0.748 ns before the active edge. But the
change appears
0.653 ns before the active edge. The violation is detected at 4.785 ns
simulation time
(It is probably beginning of the simulation).
You are probably applying reset in the testbench at the same time when an
active clock edge appears.
The reset should be applied some time after an active clock edge. This is
the most frequent reason
of that. There are also many other possible reasons:
- you are clocking the design with too high frequency.
- the clock is significantly delayed in you design (big clock skew)
- the reset signal is crossing different clock domains..etc.
Best Regards,
Steve
www.pulselogic.com.pl
"kil" <j..@gmail.com> wrote in message
news:1185527160.897610.279660@i38g2000prf.googlegroups.com...
> hi all,
>
> i have done the post place and route timing simulation for my design.
> i am getting the following warnings . there is a setup time voilation
> but can any one explain what this statment means
>
> Time: 4785 ps Iteration: 2 Instance: /sts3c_top_tb/dut/
> deframer_inst_fifo_inst_bu236
> # ** Warning: /X_SFF SETUP High VIOLATION ON SRST WITH RESPECT TO CLK;
> # Expected := 0.748 ns; Observed := 0.653 ns; At : 4.785 ns
>
>
> is that my data is arriving early than the expected ... can any one
> explain me what that warnings means and how can i make sure in my
> design to avoide this kind of warning .. that does this kind of
> warning do matter when i am loading my design into silicon. as my
> design is not working on the actual silicon.
>
> thanks ....
>
> regards
> kil
>
Article: 122422Adam Megacz schrieb: > Please bear in mind that this is only an 8-bit ripple-carry adder, and > the tools are still quite crude, but I believe we now have the > first-ever instance of a design being taken through a 100% open-source > flow, all the way from verilog to blinking lights on a programmed device. > > Details are here: > > http://research.cs.berkeley.edu/project/slipway/ > > Again, it's nowhere close to production-ready, but there are already a > lot of doors opening up: programmatic access to the inner PAR loop (ie > incremental runs) plus partial reconfiguration is a very powerful > combination. They used Icarus Verilog for synthesis. Synthesis capability has been removed from icarus Verilog (though the author hopes to reintegrate it one day) since it was very broken and buggy. PhilippArticle: 122423
Hai all, I am having the following questions in SDIO : Which register will decide the mode as DMA or Normal mode? Wat does command with response with no data mean?wat does it do?can u give some example? wat is the function of command/data register ?wen it is used? thanks in advance regards, fazArticle: 122424
On Jul 27, 3:35 pm, "Slawek" <n...@pulselogic.com.pl> wrote:
> Hi,
> SRST signal changes its value to close in time to the active edge of clock
> CLK.
> It should be changed at least 0.748 ns before the active edge. But the
> change appears
> 0.653 ns before the active edge. The violation is detected at 4.785 ns
> simulation time
> (It is probably beginning of the simulation).
>
> You are probably applying reset in the testbench at the same time when an
> active clock edge appears.
> The reset should be applied some time after an active clock edge. This is
> the most frequent reason
> of that. There are also many other possible reasons:
> - you are clocking the design with too high frequency.
> - the clock is significantly delayed in you design (big clock skew)
> - the reset signal is crossing different clock domains..etc.
>
> Best Regards,
> Stevewww.pulselogic.com.pl
>
> "kil" <j...@gmail.com> wrote in message
>
> news:1185527160.897610.279660@i38g2000prf.googlegroups.com...
>
>
>
> > hi all,
>
> > i have done the post place and route timing simulation for my design.
> > i am getting the following warnings . there is a setup time voilation
> > but can any one explain what this statment means
>
> > Time: 4785 ps Iteration: 2 Instance: /sts3c_top_tb/dut/
> > deframer_inst_fifo_inst_bu236
> > # ** Warning: /X_SFF SETUP High VIOLATION ON SRST WITH RESPECT TO CLK;
> > # Expected := 0.748 ns; Observed := 0.653 ns; At : 4.785 ns
>
> > is that my data is arriving early than the expected ... can any one
> > explain me what that warnings means and how can i make sure in my
> > design to avoide this kind of warning .. that does this kind of
> > warning do matter when i am loading my design into silicon. as my
> > design is not working on the actual silicon.
>
> > thanks ....
>
> > regards
> > kil- Hide quoted text -
>
> - Show quoted text -
thanks mr steve..
i am usign clokc of 155Mhz(6.43 ns) and in my testbench i am doing
reset after 100 ns (intially it is '0' then it is '1' after 100 ns
delay) is this the reason for my warnings. but this is in testbench
and actual design should not be get effected by this right and it may
not effect in the actual silicon....
Clock Report:
**************************
Generating Clock Report
**************************
+-------------------------+----------+------+------+------------
+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max
Delay(ns)|
+-------------------------+----------+------+------+------------
+-------------+
| clk155p52 | Local | | 100 | 1.054 |
4.249 |
+-------------------------+----------+------+------+------------
+-------------+
The Delay Summary Report
The SCORE FOR THIS DESIGN is: 164
The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0
The AVERAGE CONNECTION DELAY for this design is: 1.053
The MAXIMUM PIN DELAY IS: 4.590
The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 2.960
Listing Pin Delays by value: (nsec)
d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 5.00 d >=
5.00
--------- --------- --------- --------- ---------
---------
899 217 82 116 34
0
Timing Score: 0
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
--------------------------------------------------------------------------------
Constraint | Requested | Actual
| Logic
| |
| Levels
--------------------------------------------------------------------------------
TS_clk155p52_p = PERIOD TIMEGRP "clk155p5 | N/A | N/A
| N/A
2_p" 6.430 nS HIGH 50.000000 % | |
|
--------------------------------------------------------------------------------
TS_clk155p52_n = PERIOD TIMEGRP "clk155p5 | 6.430ns | 6.091ns
| 6
2_n" 6.430 nS HIGH 50.000000 % | |
|
--------------------------------------------------------------------------------
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate
that the
constraint does not cover any paths or that it has no requested
value.
Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 6 mins 16 secs
Total CPU time to PAR completion: 2 mins 44 secs
Peak Memory Usage: 322 MB
Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
this what the timing report after place and route.......
regards
kil
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