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http://direct.xilinx.com/bvdocs/userguides/ug332.pdf Page 234. GSR sets all DFF's or latches CLB's to a specified initial condition (either 0, or 1). The initial state comes from the RTL code (verilog or VHDL) attributes. If not specified, the device has all flops and latches in the 0 state upon startup. Ignoring timing issues, this is useful to restart (reset) state machines in a known initial state. If GSR is asserted while the device is running, it is best if clock enables are used to disable the clocks in order to ensure that the GSR state is properly loaded in all flops and latches, and then the enables my be enabled. AustinArticle: 122451
On Fri, 27 Jul 2007 10:28:40 -0700, Peter Alfke <peter@xilinx.com> wrote: >When you say "or1200", do you mean the OR function of 1200 parallel >inputs? >The most obvious implementation uses 300 + 75 + 19 + 5 + 1 = exactly >400 LUTs. >I do not understand your problem. >Peter Alfke >============ >On Jul 6, 10:37 am, e2po...@yahoo.com wrote: >> i've synthesized or1200 and it consumed 3920 slices and 7258 LUT's >> which are beyond what is available with my xilinx device with 400K >> gates. (I followed instructions ghiven in "openrisc-HW-tutorial- >> Xilinx.pdf".) Why does this take this much of resources? is it >> possible to reduce this to an acceptable level? (by removing some >> stuff). > I believe or1200 is an open source processor.Article: 122452
Markus wrote: > Sylvain Munaut wrote: >> Kevin Neilson wrote: >>> Sylvain Munaut wrote: >>>> Hello everyone, >>>> >>>> >>>> I have a placed and routed .ncd file and I'd like to be able to >>>> convert it back to a simple netlist. >>>> It doesn't contain any "secured" core, so I can freely use all the >>>> xilinx tools suite on it. But there is no "ncd2edif" ... >>>> >>>> I convert it to XDL then somehow parse it ... but in the xdl I have >>>> the slice configuration, which means I would have to convert it to a >>>> basic element (LUT/MUXF5/...) + interconnections first ... That's >>>> gonna be quite painful to do. >>>> >>>> Does someone has a better idea/tool to do the job ? >>>> >>>> >>>> Thanks, >>>> >>>> Sylvain >>> Presumably you have the NGD which you used to create the NCD. Then you >>> can use NDG2EDIF. >> No I don't ;) >> >> All I have recovered is the .ncd, the .bit, and all the .ngc except one ... >> I'm hoping to be able to reconstruct my missing ngc by "isolating" it from >> the rest in the ngc. >> >> >> I tried netgen, that gives me a vhdl (or verilog file), but parsing it >> is gonna be painful as well ;) >> >> >> Sylvain > > If you use netgen with an .ncd netlist, you can only retrieve a post-mapped > netlist, which is not synthesizable and usually does not contain any > hierarchy any more. Also, it contains additional symbols for buffers and > routing path delay. > > If you discover a method to translate the .xdl primitives (slices, iobs) > back into an .edf let us know! > > -Markus > It's not entirely true that netgen HDL can't be resynthesized. I've done that often in order to use Synplify's schematic viewer to view an NGC created by XST. Well, I guess I've run netgen postsynthesis, which is a bit different than running it post-PAR, because the former uses UNISIMs and the latter SIMPRIMs, and maybe the SIMPRIMs aren't as synthesizable. Of course it would be possible to make your own synthesizable SIMPRIM library, but that's a ton of work, and anyway, by the time you get a new netlist from the ncd your names are going to be so munged it won't make much sense. -KevinArticle: 122453
"austin" <austin@xilinx.com> wrote in message news:f8dad7$mvu1@cnn.xilinx.com... > http://direct.xilinx.com/bvdocs/userguides/ug332.pdf > > Page 234. > > GSR sets all DFF's or latches CLB's to a specified initial condition > (either 0, or 1). The initial state comes from the RTL code (verilog or > VHDL) attributes. > > If not specified, the device has all flops and latches in the 0 state > upon startup. Austin, Flops and latches are initialized to zeros only if they don't have a set pin without a reset. No controls initialize to a zero. Set only control initializes to a one. Reset control (with or without set) initializes to zero. Are things different now? Look at the FDS primitive, for instance. - John_H > Ignoring timing issues, this is useful to restart (reset) state machines > in a known initial state. > > If GSR is asserted while the device is running, it is best if clock > enables are used to disable the clocks in order to ensure that the GSR > state is properly loaded in all flops and latches, and then the enables > my be enabled. > > AustinArticle: 122454
I've got a situation. My software is saying that my two Altera Stratix II FPGAs are successfully programmed, but they don't appear to be. I think something may be erasing them as soon as they're done being configured. I'm programming them in a JTAG chain. I have the done signals of three FPGAs tied together. Two are the Stratix II and one Xilinx Virtex 4. They're open drain, so they shoulldn't light the Done LED until all three of them are done. Does anyone see a problem with tying these together?Article: 122455
> Are you using flying leads with a breadboard? PC layoud with solid ground > planes? Even though you may be using a 5V device with a 5V oscillator, you > may be getting severe overshoot and undershoot on the clock. If you have a I didn't say I have a 5V oscillator, I have i 48mhz oscillator, I assume it is suitable as it is working. The oscillator is 68x7208 48.0mhz 8931 ndk japan. > long, flying lead, consider substituting a twisted pair with the clock and > ground on the two wires from the oscillator to the CPLD's clock input. > Adding a series resistor at the oscillator output around 100 ohms may make > the destination clock look even prettier. > > You only have the one clock destination, correct? > > Please verify that you have some bulk capacitance (10uF or larger) somewhere > on this side of the USB "power supply" entry to your circuit. Good, I added this, and will shortly try again, maybe it will solve the problem. Added 10uF electrolitic + 4.7uF tantalum. > >Article: 122456
John, Basically, since the entire configuration is set to zeroes, the set, or reset values that are loaded by GSR are set to 0 for resetting (default). Basically, on startup, GSR, GHIGH, GTS, and DONE (however you decide to program the startup, as the sequence itself is programmable -- see the configuration user's guide for details). When the device starts up, everything is a zero: flops, latches, LUTRAM, SRL16, BRAM... As far as a clean and maintainable design goes, you should not count on this, but rather specify everything, as hardware may change. I am an IC designer, so I see the world with that perspective (as wraped as that is). Sometimes it is helpful, and in a case like this one, perhaps I have provided more information than is required. Your point of "don't assume" is proper from a systems engineering standpoint. AustinArticle: 122457
http://direct.xilinx.com/bvdocs/userguides/ug071.pdf Page 14. 'DONE' is itself a bidirectional, active or open drain pin. Thus, the chip is looking at itself (and others tied to DONE). I suspect that Altera does something similar (yet different) and you are now in a "can't get there from here" mode. Perhaps there are options in the bitgen software for both vendors that you require (I know we have some options that might help make it work). Presumably Altera will reply with where their documentation on the subject is located. AustinArticle: 122458
jjohnson@cs.ucf.edu writes: > Thanks everyone, this is real interesting, but please don't stop > posting if you have more insights to share! [snip] > In 32-bit Linux, can it run 4GB per process and as many simultaneous > processes of that size as the virtual memory will support? As I recall, 32-bit Linux has a limit around 3.0-3.5GB per process. On the 64-bit Linux , I have used 8+GB for a single process doing gatelevel simulations. Kai -- Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk>Article: 122459
Jon Beniston <jon@beniston.com> writes: > On 27 Jul, 17:17, Kai Harrekilde-Petersen <k...@harrekilde.dk> wrote: >> Jon Beniston <j...@beniston.com> writes: >> >> > Static Timing Analysis (TimeQuest) is mostly double-precision floating- >> >> > point? >> >> >> I seriously doubt it. I don't see a need for floating point there >> >> when delays can use scaled integers. >> >> > Dynamic range? >> >> Not a likely problem. Even a 32bit int would be big enough for holding >> up to a ridiculous 4.3 seconds, assuming 1psec resolution. > > I think you're a factor of 1000 out. Duh, brain fart indeed! > For an ASIC STA, gate delays must be specified at a much finer > resolution than 1ps. I don't recall seeing sub-psec resolution in the 130nm libraries I have seen, but that doesn't imply that it cannot be so. But I stand by my argument: the actual resolution should not matter much, as the total clock delays and cycle times should scale pretty much as the library resolution. Otherwise, there wouldn't be a point in choosing such a fast technology (who in their right mind would use a 45m process for implementing an 32kHz RTC, unless they had to?) Kai -- Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk> From puiterl@notaimvalley.nl Fri Jul 27 14:02:01 2007 Path: newsdbm05.news.prodigy.net!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!newshub.sdsu.edu!newsfeed.freenet.de!feeder.news-service.com!newsgate.cistron.nl!xs4all!transit3.news.xs4all.nl!post.news.xs4all.nl!not-for-mail Message-Id: <46aa5d98$0$235$e4fe514c@news.xs4all.nl> From: Paul Uiterlinden <puiterl@notaimvalley.nl> Subject: Re: Best CPU platform(s) for FPGA synthesis Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Date: Fri, 27 Jul 2007 23:02:01 +0200 References: <1185488344.560696.185070@19g2000hsx.googlegroups.com> <1185490882.415577.205710@b79g2000hse.googlegroups.com> <1185545886.815866.29500@o61g2000hsh.googlegroups.com> <uir85g6sp.fsf@harrekilde.dk> <1185556657.834884.140810@x35g2000prf.googlegroups.com> Organization: AimValley User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8Bit Lines: 39 NNTP-Posting-Host: 80.127.156.243 X-Trace: 1185570201 news.xs4all.nl 235 [::ffff:80.127.156.243]:57085 X-Complaints-To: abuse@xs4all.nl Xref: prodigy.net comp.arch.fpga:134344 comp.lang.vhdl:71136 comp.lang.verilog:36757 jjohnson@cs.ucf.edu wrote: > In 32-bit Linux, can it run 4GB per process and as many simultaneous > processes of that size as the virtual memory will support? Below is what I have read about it in "Self-Service Linux®" http://www.phptr.com/content/images/013147751X/downloads/013147751X_book.pdf I have no experience with it. <quote> 3.2.2.1.6 The Kernel Segment The only remaining segment in a process' address space to discuss is the kernel segment. The kernel segment starts at 0xc0000000 and is inaccessible by user processes. Every process contains this segment, which makes transferring data between the kernel and the process' virtual memory quick and easy. The details of this segment’s contents, however, are beyond the scope of this book. Note: You may have realized that this segment accounts for one quarter of the entire address space for a process. This is called 3/1 split address space. Losing 1GB out of 4GB isn't a big deal for the average user, but for high-end applications such as database managers or Web servers, this can become an issue. The real solution is to move to a 64-bit platform where the address space is not limited to 4GB, but due to the large amount of existing 32-bit x86 hardware, it is advantageous to address this issue. There is a patch known as the 4G/4G patch, which can be found at ftp.kernel.org/pub/linux/kernel/people/akpm/patches/ or http://people.redhat.com/mingo/4g-patches. This patch moves the 1GB kernel segment out of each process’ address space, thus providing the entire 4GB address space to applications. <end quote> -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not.Article: 122460
"austin" <austin@xilinx.com> wrote in message news:f8dkpf$muk3@cnn.xilinx.com... > John, > > Basically, since the entire configuration is set to zeroes, the set, or > reset values that are loaded by GSR are set to 0 for resetting > (default). Basically, on startup, GSR, GHIGH, GTS, and DONE (however > you decide to program the startup, as the sequence itself is > programmable -- see the configuration user's guide for details). > > When the device starts up, everything is a zero: flops, latches, LUTRAM, > SRL16, BRAM... > > As far as a clean and maintainable design goes, you should not count on > this, but rather specify everything, as hardware may change. > > I am an IC designer, so I see the world with that perspective (as wraped > as that is). Sometimes it is helpful, and in a case like this one, > perhaps I have provided more information than is required. > > Your point of "don't assume" is proper from a systems engineering > standpoint. > > Austin Austin - I'm not asking, I'm telling. In the Spartan-2, 2E, 3, and 3E designs that I did, ALL elements with set (but no reset) controls power up high. I implore you again - check out the FDR primitive. Not all flops power up zero, hence the occasional problems when compiling a design without explicit asynchronous resets or INIT attributes. I had to parse through EDIF files to find the set-on-power-up synchronous elements to get my simulation to match my hardware. Unless something is different in the Virtex family of devices (which I would not expect at this very low level) the behavior of the synchronous elements as defined empirically and through the primitive definitions themselves is different than "all zeros all the time on power up." Life would be *so* much easier if this was the case. - John_HArticle: 122461
Sorry, I should have googled... Peter ======== On Jul 27, 10:43 am, mk <kal*@dspia.*comdelete> wrote: > I believe or1200 is an open source processor.Article: 122462
I have used the MIG 1.72 tool to generate a memory interface for the DDR2 SODIMM on the Xilinx ML501 board. It works... sort of. I The SIM_ONLY parameter, which disables the 200us power-on delay for simulation has been causing me quite a bit of angst.Article: 122463
I have used the MIG 1.72 tool to generate a memory interface for the DDR2 SODIMM on the Xilinx ML501 board. It works... sort of. I am using the MIG synthesizable testbench as an indicator that the memory and controller are functioning correctly (which does some reads and writes to some addresses and makes sure they come back ok, otherwise asserts its 'error' output). The SIM_ONLY parameter, which disables the 200us power-on delay for simulation has been causing me quite a bit of angst. When I implemented the controller on the FPGA, phy_init_done is asserted and the testbench gives no errors... iff SIM_ONLY is set to 1 (disable 200us delay). When I set SIM_ONLY to 0 (i.e. the way it should be set for implementation) one of the following happens: 1) phy_init_done is never asserted (memory init fails completely) 2) phy_init_done is asserted, but the testbench gives an error signal 3) After manually (pushbutton) generating a whole bunch of resets, once in a while, it can be made to start up correctly Not seeing how a 200us delay should have this effect, I did some simulations and dug into the MIG code and discovered that setting the SIM_ONLY parameter to 1 also causes stage 1 of the read calibration routine to be skipped (would have been nice if it was documented better). So, I set the SIM_ONLY flag back to 0 at the top level, and then set it to 1 for the calibration module only. Now with the 200us delay enabled, but stage 1 of the calibration routine is still being skipped. With this arrangement, I see the right outputs (phy_init_done is asserted, and no error from the testbench). So I am left with a great many questions: 1) Why do things seem to work with stage 1 disabled? Is the default good enough? 2) Why does stage 1 not succeed? I suspect perhaps a reset problem, since resetting enough times will eventually land it in a functional state. 3) Why does the testbench usually fail if stage 1 succeeds, yet does not fail ever when stage 1 is skipped? 4) How can I better probe to see where things are going wrong? What might be good things to check? Thanks, BenArticle: 122464
"austin" <austin@xilinx.com> wrote in message news:f8dkpf$muk3@cnn.xilinx.com... > John, > > Basically, since the entire configuration is set to zeroes, the set, or > reset values that are loaded by GSR are set to 0 for resetting > (default). Basically, on startup, GSR, GHIGH, GTS, and DONE (however > you decide to program the startup, as the sequence itself is > programmable -- see the configuration user's guide for details). > > When the device starts up, everything is a zero: flops, latches, LUTRAM, > SRL16, BRAM... > > As far as a clean and maintainable design goes, you should not count on > this, but rather specify everything, as hardware may change. > > I am an IC designer, so I see the world with that perspective (as wraped > as that is). Sometimes it is helpful, and in a case like this one, > perhaps I have provided more information than is required. > > Your point of "don't assume" is proper from a systems engineering > standpoint. > > Austin Austin, It appears things are slightly different for the newest families which use a common FDRSE primitive. Heck, this may be a software-only thing. The Spartan-3E Libraries Guide for HDL Designs for (ISE 8.1i and 9.1i checked) *does* have the common FDRSE primitive but the Xilinx Libraries Guide for 8.1i (9.2i has bookmark problems) has a separate FDS primitive (and FDSE, FDP, FDPE, LDP, LDPE, and all _1 variants) which states: "For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the flip-flop is preset to active high when GSR is active." I would hope the Spartan-3 maintains the old variants but I'm not certain EDIFs I've generated from the 3rd party synthesis doesn't use FDS style primitives - I'll have to check. I would expect XST to only support the FDRSE primitive. - John_HArticle: 122465
John, OK. I will check. I can be, and have been wrong before. I am staring at someone else's schematics (of the CLB) and perhaps I am seeing a behavior that doesn't exist. Without a simulation, well, you know, my statement is not much more than second hand stories, retold. Just because I don't see the problem, doesn't mean anything, as I am not making designs for production (just characterizing and testing). As much as I am a proponent of always doing a simulation, I am not setting a good example here! AustinArticle: 122466
> Austin, > > It appears things are slightly different for the newest families which use > a common FDRSE primitive. Heck, this may be a software-only thing. The > Spartan-3E Libraries Guide for HDL Designs for (ISE 8.1i and 9.1i checked) > *does* have the common FDRSE primitive but the Xilinx Libraries Guide for > 8.1i (9.2i has bookmark problems) has a separate FDS primitive (and FDSE, > FDP, FDPE, LDP, LDPE, and all _1 variants) which states: > > "For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, > Virtex-II Pro, and Virtex-II Pro X, the flip-flop is preset to active high > when GSR is active." > > I would hope the Spartan-3 maintains the old variants but I'm not certain > EDIFs I've generated from the 3rd party synthesis doesn't use FDS style > primitives - I'll have to check. I would expect XST to only support the > FDRSE primitive. > > - John_H Going through my EDIF from a few months ago, my design is an xc3s1600E and - although the S3E Libraries Guide shows no FDS primitives - the 3rd party synthesizer does use FDS primitives. When I spelunk into FPGA Editor to find one instance of an FDS without an INIT property, the register is checked with SRHIGH and INIT1, carrying over the expected behavior appropriate for a pre-Spartan-3E FDS primitive. I look forward to seeing only FDRSE style primitives instead to help with async-reset-free designs with better known inits. Now do the most recent synthesis tool verions produce these library elements exclusively? I'll have to check the latest release and, perhaps, call the Vendor for a new customer enhancement request. I'm happy this nuance in the devices is figured out - at least in my mind - such that future designs have a chance of running smoother. - John_HArticle: 122467
John, OK. If this is a software thing, then I am out of my field. Obviously, the software can fiddle with the bits to create any behavior that is desired on start-up, and it isn't a hardware issue at all. If the customer is programming with verilog, or VHDL (which I assume they are) then what they instantiate will be what they get (as you so clearly point out). If they also want to set, or reset the flops or latches at sometime other than initial start-up, then they may use GSR to do that. AustinArticle: 122468
John, I learned something new: software is everywhere.... AustinArticle: 122469
"austin" <austin@xilinx.com> wrote in message news:f8dpff$mvv1@cnn.xilinx.com... > John, > > OK. If this is a software thing, then I am out of my field. > > Obviously, the software can fiddle with the bits to create any behavior > that is desired on start-up, and it isn't a hardware issue at all. > > If the customer is programming with verilog, or VHDL (which I assume > they are) then what they instantiate will be what they get (as you so > clearly point out). > > > If they also want to set, or reset the flops or latches at sometime > other than initial start-up, then they may use GSR to do that. > > Austin My problem wasn't with instantiating primitives. My problem is that the list of devices from the Xilinx Libraries Guide that support the FDS (and similar) primitives WILL power-up to a logic high when the SYNTHESIS decides to infer those inverted primitives. My Verilog went to EDIF even in my Spartan-3E without my intervention to produce FDS primitives in many, many places. - John_HArticle: 122470
On Jul 27, 1:25 am, "X.Y." <Xieyu1...@gmail.com> wrote: > On Jul 27, 5:37 am, Subroto Datta <sda...@altera.com> wrote: > > > > > > > Hi X.Y, > > > The Incremental Compilation flow currently does not allow the > > imported .qxp to be "stamped" onto different instances. This is > > coming. One workaround is to have a different HDL file and name for > > each instance. Admittedly, this is not ideal but in many cases is an > > easy solution. (If you're making changes on the top-level file, it's > > painful to repeat in multiple files. But if the changes are in the > > HDL files beneath that entity, then it all works smoothly after the > > initial set-up.) > > > One flow Iused often, mainly because it works and is easy, is the > > pseudo-bottom up flow. This basically involves putting partitions on > > the hierarchies that are in the same level as the one/s you are > > interested in and set them to Empty(so they have no logic, but nothing > > gets removed). I then work on the partitions I want with quick > > compiles. Then, when I get what I want, I set that partition to post- > > fit and either set the other partitions to Source or delete them > > altogether(making everything else one big partition). It's quick and > > easy without creating sub-projects, making sure their layout fits into > > the top-level, etc. Also, in Q7.1 you can export a .qxp from sub > > partitions, so you can always save off your results. This works with > > multiple instances of the same thing, since they now have different > > instances(and locations). > > > What end goal are you using Incremental Compilation flow for? Are you > > trying to reduce compile times, are you trying to preserve > > performance, or something else? > > > - Subroto Datta > > Altera Corp. > > Thanks for your reply! My end goal is trying to preserve performance. > In our project, I use one Cyclone II FPGA to process four groups of > image signal which comes from four cameras. The processing algorithms > of the four groups of image signal are all the same. As a result, I > plan to build a subproject implementing the processing of one of the > four signals and export it as a partition. Then, I build a top level > project and import it four times. Certainly, I will do four different > pin assignments for the four partitions. > It appears that LogicLock can do it also, am I right?- Hide quoted text - > > - Show quoted text - I would recommend against using LogicLock for preserving performance(which is done through back-annotation of location assignments). LogicLock is excellent for floorplanning, but can have issues with these back-annotated assignments. That portion of the LogicLock flow is really meant to be replaced by the Incremental Compilation flow. One thing I want to make sure of, does your design not meet timing when run flat? Also, is it large portions of your design or just a small sub-section that continually fails timing? I'm assuming it doesn't meet timing when put together, and it's not just a single block, as the strategy for these flows can be slightly different. Do your four equal blocks connect to each other? Is there some central, common logic? Do they connect to pins? The problem I've seen with what you're trying to do is a good placement of a single block isn't good everywhere. For example, let's say you put them into the four quadrants of the device. In the lower-level you optimize one for the top-left corner, so the connections it makes to pins are all placed along the top-and-left side, and the connections you make to internal logic are on the bottom and right sides. Now, if you try to keep that placement but move it to an instantiation on the bottom- right, your pin and logic connections are reversed, and if these paths are critical at all, they can fail timing. Just to go over the pseudo-bottom up flow again, take your top-level design and: 1) Put a partition on all four instances, and any thing else you want to put a partition on. 2) Floorplan the partitions(most likely into quadrants) (This is can be optional) 3) Set three of the four to empty and let the fitter work on the fourth one(say top-left region.) 4) Set the top-left region to Post-Fit and set a second partition to Source(or Post-Synthesis) and fit it 5) Repeat onto the third and fourth partition 6) If any of them still doesn't make timing, you can back and refit that one while leaving the rest post-fit. The nice thing about this flow is each region is aware of pin locations, as well as any logic that is not set to empty. So if there is some central block of logic, it can optimize placement to connect to that. If the pin assignments have a different layour for all four instances, the fitter can optimize for that. Hope this helps, Subroto Datta Altera Corp.Article: 122471
John, I get it: at the highest level, you didn't specifically request, nor expect, a particular 'behavior'. The synthesis tool reached into its libraries, pulled out an element, and said "this will work..."... In ASIC standard cell design, I have had to specifically declare some elements as "do not use" because of their (unwanted) behavior. Each standard cell library being somewhat unique for any given technology, this is a moving target. Then finally the synthesis gives me what I wanted, but only after a sometimes painful period of debugging. If the designer doesn't capture everything and write it down, and someone else has to pick up what they have done, it can be a real nightmare. AustinArticle: 122472
Hi,
I am having trouble configuring a xc3s250e from a st m25pe20 spi
flash rom. Originally init would not go low and the chip was
constantly looping through the config. I inserted a 256 0xFF's at the
beginning of the mcs file and now init goes low, but done does not go
high. Is there some number of 0's or 1's that need to be appended to
the image. I am using xilinx ise 9.1. I generated the mcs file using
impact and selected the generic SPI options. I have tried bit-swapping
the file. Init only goes low one way. The last line of my prom image
is:
:1094F00020000000200000002000000020000000EC
I have heard of a postamble that should be 0x7F, this file doesn't
have one though.
Thanks,
Jon Pry
Article: 122473Gee ... for all the responses, the issue with the traditionally long propagation delay of the GSR has not been mentioned. The GSR transition time thru the Spartan 2Es was speced at 30 ns +, with the resulting problem being that flip-flops throughout the design were not guarenteed to see the deassertion of reset on the same clock. The rule of thumb was to avoid relying on the GSR for your chip reset. Instantiate your own reset as part of your design. Regards, John Retta Owner and Designer Retta Technical Consulting Inc. Colorado based Xilinx consultant email : jretta@rtc-inc.com web : www.rtc-inc.com <tonico> wrote in message news:46aa1291$1_4@mk-nntp-2.news.uk.tiscali.com... > Hello, > What does GSR pin do, when should I use it? How do I use it? > Is it required in every design? > Thanks in advance for any response. > >Article: 122474
Dear All.
I want to see the signals in the EP2C12Q240C8 FPGA for my
design inside with several instances..It has EPCS4 configuration
device .I am using quartus7.1 s/w.I am using byte blaster II download
cable.I am using LVTTL standards for all I/O with VCCINT 1.8V VCCI/O
3.3V.Which logic analyser i have to use signaltap or signal probe.Is
it possible.I am unaware of the term JTAG .Please help me as i am in
stalemate postion.I want to debug the signals.
thanking you
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