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Hi, as I mentioned there are many of possible reasons. 1. Regarding the timing violation. You can check inputs of the /sts3c_top_tb/dut/deframer_inst_fifo_inst_bu236 flip-flop and track the change to find its source. However, such violation at the beginning of the reset may not be relevant. 2. I am guessing but if your design incorporates LVDS transmission module working on both clock edges (DDR) quality of the clock is essential, for instance jitter, duty cycle, phase shift (comparing to clock phase in external receivers and transmitters) etc. Such things are not modeled very well in simulation and you may be surprised why it is working in simulation but not in the real silicon. This is all what I can guess without knowing your design. Best Regards, Steve www.pulselogic.com.pl "kil" <j..@gmail.com> wrote in message news:1185535035.270800.178190@d30g2000prg.googlegroups.com... > On Jul 27, 3:35 pm, "Slawek" <n...@pulselogic.com.pl> wrote: >> Hi, >> SRST signal changes its value to close in time to the active edge of >> clock >> CLK. >> It should be changed at least 0.748 ns before the active edge. But the >> change appears >> 0.653 ns before the active edge. The violation is detected at 4.785 ns >> simulation time >> (It is probably beginning of the simulation). >> >> You are probably applying reset in the testbench at the same time when an >> active clock edge appears. >> The reset should be applied some time after an active clock edge. This is >> the most frequent reason >> of that. There are also many other possible reasons: >> - you are clocking the design with too high frequency. >> - the clock is significantly delayed in you design (big clock skew) >> - the reset signal is crossing different clock domains..etc. >> >> Best Regards, >> Stevewww.pulselogic.com.pl >> >> "kil" <j...@gmail.com> wrote in message >> >> news:1185527160.897610.279660@i38g2000prf.googlegroups.com... >> >> >> >> > hi all, >> >> > i have done the post place and route timing simulation for my design. >> > i am getting the following warnings . there is a setup time voilation >> > but can any one explain what this statment means >> >> > Time: 4785 ps Iteration: 2 Instance: /sts3c_top_tb/dut/ >> > deframer_inst_fifo_inst_bu236 >> > # ** Warning: /X_SFF SETUP High VIOLATION ON SRST WITH RESPECT TO CLK; >> > # Expected := 0.748 ns; Observed := 0.653 ns; At : 4.785 ns >> >> > is that my data is arriving early than the expected ... can any one >> > explain me what that warnings means and how can i make sure in my >> > design to avoide this kind of warning .. that does this kind of >> > warning do matter when i am loading my design into silicon. as my >> > design is not working on the actual silicon. >> >> > thanks .... >> >> > regards >> > kil- Hide quoted text - >> >> - Show quoted text - > > thanks mr steve.. > > i am usign clokc of 155Mhz(6.43 ns) and in my testbench i am doing > reset after 100 ns (intially it is '0' then it is '1' after 100 ns > delay) is this the reason for my warnings. but this is in testbench > and actual design should not be get effected by this right and it may > not effect in the actual silicon.... > > > Clock Report: > ************************** > Generating Clock Report > ************************** > > +-------------------------+----------+------+------+------------ > +-------------+ > | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max > Delay(ns)| > +-------------------------+----------+------+------+------------ > +-------------+ > | clk155p52 | Local | | 100 | 1.054 | > 4.249 | > +-------------------------+----------+------+------+------------ > +-------------+ > > > The Delay Summary Report > > The SCORE FOR THIS DESIGN is: 164 > > > The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0 > > The AVERAGE CONNECTION DELAY for this design is: 1.053 > The MAXIMUM PIN DELAY IS: 4.590 > The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 2.960 > > Listing Pin Delays by value: (nsec) > > d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 5.00 d >= > 5.00 > --------- --------- --------- --------- --------- > --------- > 899 217 82 116 34 > 0 > > Timing Score: 0 > > Asterisk (*) preceding a constraint indicates it was not met. > This may be due to a setup or hold violation. > > -------------------------------------------------------------------------------- > Constraint | Requested | Actual > | Logic > | | > | Levels > -------------------------------------------------------------------------------- > TS_clk155p52_p = PERIOD TIMEGRP "clk155p5 | N/A | N/A > | N/A > 2_p" 6.430 nS HIGH 50.000000 % | | > | > -------------------------------------------------------------------------------- > TS_clk155p52_n = PERIOD TIMEGRP "clk155p5 | 6.430ns | 6.091ns > | 6 > 2_n" 6.430 nS HIGH 50.000000 % | | > | > -------------------------------------------------------------------------------- > > > All constraints were met. > INFO:Timing:2761 - N/A entries in the Constraints list may indicate > that the > constraint does not cover any paths or that it has no requested > value. > Generating Pad Report. > > All signals are completely routed. > > Total REAL time to PAR completion: 6 mins 16 secs > Total CPU time to PAR completion: 2 mins 44 secs > > Peak Memory Usage: 322 MB > > Placement: Completed - No errors found. > Routing: Completed - No errors found. > Timing: Completed - No errors found. > this what the timing report after place and route....... > > > regards > kil >Article: 122426
If I put a Xilinx SysAce and two Altera Stratix II FPGAs on the same JTAG chain, will I be able to program the two Altera parts with Quartus and the SysAce with impact? If so, will it work as it ordinarily would or do I need to do something to put the other devices in bypass mode? Thanks, DaleArticle: 122427
Where on does one find those files with pin<->name files? Like this: 1 GND 2 IO_7 207 PROG_B 208 TDI etc.. I know this was brought up before, but finding the thread.. in the usenet haystack ;)Article: 122428
On 27 Jul., 14:24, Dale <dale.prat...@gmail.com> wrote: > If I put a Xilinx SysAce and two Altera Stratix II FPGAs on the same > JTAG chain, will I be able to program the two Altera parts with > Quartus and the SysAce with impact? If so, will it work as it > ordinarily would or do I need to do something to put the other devices > in bypass mode? > > Thanks, > Dale yes (and you need as always to put other devices to bypass of course)Article: 122429
Yes. I have done the functional simulation and that seems to work fine. So I was curious about the timing simulation. I will work on doing the static timing analysis and see what Fmax I get. I have multiple clock domains so I am hoping that it will provide multiple Fmax values. Thanks. Eddie Thanks. CPArticle: 122430
PFC <lists@peufeu.com> wrote:
>> Where on does one find those files with pin<->name files?
>http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=-18772&iLanguageID=1
>comes as excel file (search for "excel" in the page)
>If you are using Eagle, check the download page at cadsoft for reasy to
>use libraries.
Eagle didn't have any proper .lbr
But under: Spartan-3 Data Sheets
Spartan-3 ASCII Pinouts and Excel Footprints
s3_pin/tables> awk -F, '{print $1,$7,$8,$9}' pq208_table.csv | more
6 VCCO_7 VCCO 7
.
.
etc
Does the job.
Thanks!
Article: 122431> Where on does one find those files with pin<->name files? http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?sGlobalNavP= ick=3D&sSecondaryNavPick=3D&category=3D-18772&iLanguageID=3D1 comes as excel file (search for "excel" in the page) If you are using Eagle, check the download page at cadsoft for reasy to = = use libraries. > > Like this: > 1 GND > 2 IO_7 > 207 PROG_B > 208 TDI > > etc.. =Article: 122432
On Fri, 27 Jul 2007 15:02:46 +0200, <pbFJKD@ludd.invalid> wrote: > PFC <lists@peufeu.com> wrote: >>> Where on does one find those files with pin<->name files? > >> http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?sGlobalN= avPick=3D&sSecondaryNavPick=3D&category=3D-18772&iLanguageID=3D1 > >> comes as excel file (search for "excel" in the page) > >> If you are using Eagle, check the download page at cadsoft for reasy = to >> use libraries. > > Eagle didn't have any proper .lbr ftp://ftp.cadsoft.de/eagle/userfiles/libraries/xilinx_spartan3_virtex4_a= nd_5.lbr Packages, Symbols and Devices for Xilinx Spartan 3, Virtex 4 and Virtex = 5 = FPGAs. All of them. Automatically generated from Xilinx ASCII pinout = files. Packages according to Xilinx drawings and recommendations. Not = tested, no warranties whatsoever.Article: 122433
"Akhil" <akhileshpatil@gmail.com> wrote in message news:1185516060.325876.251820@i13g2000prf.googlegroups.com... > Hi, > I just overheard about a kind of standard lib component F/F, which are > used to "smash" X-values at the module level boundary. > This components are said to have a quality of either pushing "0" or > "1" at the outputs instead of "x" or "X". > I would like to request you all, to throw some light on this. As I > searched in Google it did not result in any kind of convincing > information. > > Please reply. > > Akhilesh > Well, in the real world there really isn't such a beast as "X". Everything is either a "1" or "0". Sometimes you may not know whether its a "1" or "0" .. in virtual land that is one of the things that "X" tells you. SInce there is no "X" in the real world where real library components are used, then I do not believe there is such a library cell that banishes this condition. You can always edit the models for the cell libraries such that they don't produce an "X" anymore. You can also edit the SDC files so that timing violations no longer occur as well (that is another cause of the wicked "X"). MikeArticle: 122434
Xilinx V5 supports Differential select I/O data rate upto 1250 Mbps. It supports HT_25, LVDS_25 and may other electrical standards. What electrical standard should be used to support the maximum specified data rate of 1250 Mbps? My preference will be HT_25 as it is easy to meet the common mode voltage specification but I am not sure if I can achieve the highest supported data rate with the HT_25 electrical standard. The LVDS_25 has typical input common mode voltage of 1.2V while the HT_25 has typical input common mode voltage of 600mV. I understand that LVDS_25 has very wide common mode voltage range. But do I get the highest specified data rate if I do not follow they typical voltage specification? LVDS_25 I think is the most popular standard. Do I have to use 1.2V input common mode voltage for 1.25 Gbps operation? or Can I still get 1.25 Gbps with HT_25 at 600mV input common mode voltage? Thanks AaronArticle: 122435
> > Static Timing Analysis (TimeQuest) is mostly double-precision floating- > > point? > > I seriously doubt it. I don't see a need for floating point there > when delays can use scaled integers. Dynamic range? Cheers, JonArticle: 122436
I think that memory performance is the limiting factor for FPGA synthesis and P&R. This machine had a single core AMD 64 processor which I recently replaced with a slightly faster dual core processor. I ran a fairly quick FPGA build through Quartus to get a time for a before and after comparison before I did the swap. The before and after times were exactly the same :-( I think the amount and speed of memory is crucial, it's probably worth paying as much attention to that as to the processor. Nial.Article: 122437
Nial Stewart wrote: > I ran a fairly quick FPGA build through Quartus to get a time for a > before and after comparison before I did the swap. Did you changed the setting "use up to x number of CPUs" (don't remember the exact name) somewhere in the project settings? -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 122438
On Jul 26, 2:17 am, Richard Klingler <m...@aol.com> wrote: > Stef wrote: > > In comp.arch.fpga, > > Jim Granville <no.s...@designtools.maps.co.nz> wrote: > >> Stef wrote: > >>> Thank you all for your input. To sum it up: > > >>> Altera and Xilinx are indeed the major brands to look at. Lattice has > >>> some nice stuff, but is smaller and does not support VHDL (at least > >>> not in the low-end tools). > >> Are you sure ? > > >> The web page states this : > >> [Supported HDL languages include; VHDL, Verilog 1995, Verilog 2001.] > > >> and they release the Mico8/Mico32 in both Verilog and VHDL. > > > You are right the ispLever tools do include VHDL. > > I somehow missed that, sorry for the mis-information there. > > Heard that with ispLever 7.0 they now also support mixed > VHDL/Verilog design which Altera is doing it for years now (o; > > Can someone confirm on this? > > cheers > rick- Hide quoted text - > > - Show quoted text - Yes, Lattice ispLEVER 7.0 does support mixed VHDL / Verilog synthesis native to the ispLEVER Project Navigator GUI. Actually, the ispLEVER has supported a mixed language support for some time. In the past, Precsion (included with the ispLEVER) could be used as the synthesis vendor of choice to create an EDIF file from a mixed design. Then the EDIF file could be brought into the ispLEVER Project Navigator. The advantage of ispLEVER 7.0 is that now a "single-step" flow can be supported and customers can use Synplify as a synthesis tool if so desired. John Dimtsios LatticeArticle: 122439
Aaron, That is why people use signal integrity simulation tools: without running a simulation for your pcb traces, and your driving/driven device(s), your question can not be answered. The 1.25 Gbs also presumes double data rate (DDR). A quick "what if" using Hyperlynx SI tool, shows both standards are capable of the speed (ie they switch fast enough, 'eye' is open), but a full simulation for your situation would be required to have confidence that it would work at this speed. AustinArticle: 122440
Akhil <akhileshpatil@gmail.com> writes: > I just overheard about a kind of standard lib component F/F, which > are used to "smash" X-values at the module level boundary. X's are your friend. Filter them away and you filter away your bugs. The place where you want to filter aways X's is when crossing clock domains. Here you would like to propagate 0 or 1 to mimic metastability flops. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 122441
On Jul 26, 6:19 pm, jjohn...@cs.ucf.edu wrote: > AMD or Intel? > ------------------- > Between AMD & Intel's latest multicore CPUs, > - Which offers the best integer performance? > - Which offers the best floating-point performance? > Specific models within the AMD/Intel family? > > Assume cost is no object, and each uses its highest-performing memory > interface, but disk access is (necessary evil) over a networked drive. > (Small % of total runtime anyway.) > > Multi-core, multi-processor, or both? 32-bit or 64-bit? Linux vs. > Windows? >2GB of RAM? If cost is no object, then go with the Intel quad-core running at 3 GHz : QX6850. Each core has 2 MB of L2 cache (8MB total), which is, according to several reports in this forum, the single most important factor. I would say go with 4GB of ram, although if you're using the biggest chips, you might need more. Keep in mind that Windows 32-bit will only be able to use 3GB max of this 4 GB, and each application will only be able to access 2GB max. So you might consider Windows 64 bits or Linux 64 bits if necessary. PatrickArticle: 122442
Hello, What does GSR pin do, when should I use it? How do I use it? Is it required in every design? Thanks in advance for any response.Article: 122443
I read this thread with great interest and have a very closely related question. As of May 07 Altera recommend putting their pll gnd pins in a split plane. The arguments in this thread make a lot of sense for seperate analog circuits being on the same plane because one can physically seperate them, but how about pll gnds which are 3mm (3 balls) away from a standard GND pin. Any advice appreciated as this will end an argument in our office. ColinArticle: 122444
Jon Beniston <jon@beniston.com> writes: >> > Static Timing Analysis (TimeQuest) is mostly double-precision floating- >> > point? >> >> I seriously doubt it. I don't see a need for floating point there >> when delays can use scaled integers. > > Dynamic range? Not a likely problem. Even a 32bit int would be big enough for holding up to a ridiculous 4.3 seconds, assuming 1psec resolution. As far as I know, everything in the simulate, synth, P&R, and STA chain can be performed with adequate resolution using integers. Crosstalk and inductive effects might require floating point help, but I would be surprised if even that can be approximated well with fixed-point arithmetic. Kai -- Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk>Article: 122445
sharp@cadence.com writes: > 64-bit Linux can make use of more than 4GB of RAM. But don't use 64- > bit executables unless your design is too big for 32-bit tools, > because they will run slower on the same machine. Although that might be true for some specific cases, in general on Linux native 64-bit executables tend to run faster than 32-bit executables. But I haven't benchmarked 32-bit vs. 64-bit FPGA tools.Article: 122446
On Jul 19, 3:35 pm, "RCIngham" <robert.ing...@gmail.com> wrote: > >i've synthesized or1200 and it consumed 3920 slices and 7258 LUT's > >which are beyond what is available with my xilinx device with 400K > >gates. (I followed instructions ghiven in "openrisc-HW-tutorial- > >Xilinx.pdf".) Why does this take this much of resources? is it > >possible to reduce this to an acceptable level? (by removing some > >stuff). > > From reading the output listings of the Xilinx tools, has it used the > devices on-chip RAM blocks, or has it inferred flip-flop-based registers? > If the latter, then you need to do the tutorial again, and correctly this > time... > > What part are you targetting? im targeting spartan 400K gate version. i followed the tutorial correctly. it synthesis output contains thousands of HDL adviser comments. i've disabled the cache and instructed the synthesizer to infer block rams.Article: 122447
Thanks everyone, this is real interesting, but please don't stop posting if you have more insights to share! FWIW, my runtimes in Quartus are dominated by P&R (quartus_fit); on Linux, they run about 20% faster on my 2005-era 64-bit Opteron than on my 2004-era 32-bit Xeon (both with a 32-bit build of Quartus). Another test run of a double-precision DSP simulation (compiled C) ran substantially slower on the Opteron, which I thought was supposed to have better floating-point performance than Xeons of that era. Maybe it was just a case of the gcc -O5 optimization switches being totally tuned to Intel instead of AMD, or maybe my Quartus P&R step is primarily dominated by integer calculations. I originally suspected P&R might have a lot of floating-point calculations (even prior to signal-integrity considerations) if they were doing any kind of physical synthesis (e.g., delay calculation based on distance and fanout); ditto for STA, because that's usually an integral part of the P&R loops. I also suspected that if floating- point operations (at least multiplies, add/subtract, and MACs) could be done in a single cycle, there would be no advantage to using integer arithmetic instead (especially if manual, or somewhat explicit integer scaling is required). On the other hand, in something like a router, you can get more exact location info wrt stuff like grid coordinates than you can with floating-point. As far as dynamic range is concerned, I seem to recall that SystemC standardized on 64-bit time to run longer simulations, but SystemC is a different animal in that regard anyway. Nonetheless, I also seem to recall that its implementation of time was 64-bit integers (scaled), because the average FPU operations are really only linear over the 53-bit mantissa part. Assuming they want linear representation of time ticks, I can see the appeal of using 64-bit integers in simulation. As far as event-driven simulations are concerned, I totally understand how hard it is to make good use of multithreading or multiprocessing, because everything is so tightly coupled in that evaluate/update/ reschedule loop. If you were working at a much higher level (behavioral/transaction), where the number of low-level events is lower and the computation behind "complex" events took up a much larger portion of the evaluate/update/reschedule loop, then multicore/ multiprocessing solutions might be more effective for simulation. (Agree/disagree?) It seems that as you get more coarse-grained with the simulation, that even distributed processing (multiple machines on a network) becomes more feasible. Obviously the scheduler has one "core" and has to reside in one CPU/memory space, but if it has less work to do, then it can handle less frequent communication with the event-processing CPUs in another space. Back to Quartus in particular and Windows in general... Quartus supports the new "number_of_cpus" or some similar variable, but only seems to use it in small sections of quartus_fit (I think Altera is just making their baby steps in this area). That appears to be related to the number of processors inside one box. If a single CPU is just hyperthreaded, the processor takes care of instruction distribution unrelated to a variable like number_of_cpus, right? And if there are two single-core processors in a box, obviously it will utilize "number_of_cpus=2" as expected. Does anyone know how that works with dual-core CPUs? i.e, if I have two quad-core CPUs in one box, will setting "number_of_cpus=7" make optimal use of 7 cores while leaving me one to work in a shell or window? Does anyone know if Quartus makes better use of multiple processors in a partitioned bottom-up flow compared to a single top-down compile flow? In 32-bit Windows, is that 3GB limit for everything running at one time? i.e., is 4GB a waste on a Windows machine? Can it run multiple 2GB processes and go beyond 3 or 4GB? Or is 3GB an absolute O/S limit, and 2GB an absolute process limit in Windows? In 32-bit Linux, can it run 4GB per process and as many simultaneous processes of that size as the virtual memory will support? In going to 64-bit apps and O/S versions, should the tools run equally fast as long as the processor is truly 64-bit? Thanks again for all the insights and interesting discussion. jjArticle: 122448
On 27 Jul, 17:17, Kai Harrekilde-Petersen <k...@harrekilde.dk> wrote: > Jon Beniston <j...@beniston.com> writes: > >> > Static Timing Analysis (TimeQuest) is mostly double-precision floating- > >> > point? > > >> I seriously doubt it. I don't see a need for floating point there > >> when delays can use scaled integers. > > > Dynamic range? > > Not a likely problem. Even a 32bit int would be big enough for holding > up to a ridiculous 4.3 seconds, assuming 1psec resolution. I think you're a factor of 1000 out. For an ASIC STA, gate delays must be specified at a much finer resolution than 1ps. Cheers, JonArticle: 122449
When you say "or1200", do you mean the OR function of 1200 parallel inputs? The most obvious implementation uses 300 + 75 + 19 + 5 + 1 = exactly 400 LUTs. I do not understand your problem. Peter Alfke ============ On Jul 6, 10:37 am, e2po...@yahoo.com wrote: > i've synthesized or1200 and it consumed 3920 slices and 7258 LUT's > which are beyond what is available with my xilinx device with 400K > gates. (I followed instructions ghiven in "openrisc-HW-tutorial- > Xilinx.pdf".) Why does this take this much of resources? is it > possible to reduce this to an acceptable level? (by removing some > stuff).
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