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>> When vias swap your signal between signal layers, your EMI will be >> affected by the distance to the closest capacitors, through the cap to >> the ground plane, and back to your signal. The closer the caps are, >> the better. > > I may then add a decoupling cap in the middle of my cluster of vias > where the bus changes layers, to reduce the loops. Heh. I noticed the ethernet chip has at least 20 no-connect pins (since I use its internal PHY I don't need the external PHY pins), deleted the pads in the footprint, which left enough room to route the entire bus from this chip to the FPGA with zero vias, then simplified the layout, removed the vias on the clock lines, etc. This certainly is a hack ;) but it'll work. I like that ;) Now if only DigiKey hadn't one month of lead time on the FPGA !! Argh.Article: 122176
I am working with a dual port RAM FIFO module that has a 32-bit write port and an 8-bit read port using asynchronous clocks. The full and empty flags use static thresholds...meaning I didn't choose the programmable option...it uses the default setup in COREGen. There are 2048 32-bit elements in the FIFO. I am seeing the FULL flag go high after the 2046th 32-bit write. The 2047th 32-bit write is accepted by the FIFO, but the last 32-bit write causes an overflow and the data is not written into the FIFO. So I went in the COREGen and tried to use the one-time programmable full threshold for the FULL logic and the maximum number it allowed was 2046. Does this mean that an 'X-element' FIFO is really full when X-1 elements have been written? If I need a FIFO to hold 2048 elements do I have to create one with 2049 elements? I looked in the FIFO user guide and haven't seen an exact explanation. Thanks.Article: 122177
On Jul 22, 6:33 pm, motty <mottobla...@yahoo.com> wrote: > I am working with a dual port RAM FIFO module that has a 32-bit write > port and an 8-bit read port using asynchronous clocks. The full and > empty flags use static thresholds...meaning I didn't choose the > programmable option...it uses the default setup in COREGen. There are Is it really important to have a capacity of 2048 entries? Detecting FULL in an asynchronous FIFO is a tricky procedure. It is much easier when the last position is not being used. A FIFO should really never go FULL. That is an indication of insufficient depth... Peter Alfke > 2048 32-bit elements in the FIFO. I am seeing the FULL flag go high > after the 2046th 32-bit write. The 2047th 32-bit write is accepted by > the FIFO, but the last 32-bit write causes an overflow and the data is > not written into the FIFO. > > So I went in the COREGen and tried to use the one-time programmable > full threshold for the FULL logic and the maximum number it allowed > was 2046. Does this mean that an 'X-element' FIFO is really full when > X-1 elements have been written? If I need a FIFO to hold 2048 > elements do I have to create one with 2049 elements? I looked in the > FIFO user guide and haven't seen an exact explanation. > > Thanks.Article: 122178
Thank you John; Thank you Symon. >Thinking as if single ended signals are actually differential signals, >one side of which just happens to be ground helps make this clearer. Its helpful! Leon,Article: 122179
"David M. Palmer" <dmpalmer@email.com> wrote in message news:210720071157266083%dmpalmer@email.com... > In article <f7ik0f$ft$1@aioe.org>, Symon <symon_brewer@hotmail.com> > wrote: > >> http://www.amazon.com/Aveda-Hand-Relief-4-2-oz/dp/B000FAMUIU >> I went into an Aveda store somewhere in silicon valley once and demanded >> this product. I half expected to be arrested, but apparently the UK >> meaning >> hasn't travelled the Atlantic yet. My mates back in the UK were delighted >> to >> have gifts of 'Hand Relief' for xmas! > > I'm glad your story had a happy ending. > > -- > David M. Palmer dmpalmer@email.com (formerly @clark.net, @ematic.com) Thank you, Mr 'Palmer'! :-)Article: 122180
Hi I'm studying Embedded system using XUPVP2PRO and use the tools ISE 8.1, EDK 8.1 and ModelSim 6.0 SE. I want to verify my custom IP. so I found the manual (http:// www.xilinx.com/bvdocs/desfiles/ug436.pdf). But it was based on ISE 8.2 and EDK 8.2. So Could you explain the procedure about system simulation?Article: 122181
On Jul 20, 6:16 pm, "Eddie H" <> wrote: > Mikhail, > > On powerup, I would like to transmit the 400 Mbps data using > GTPs conifigured to run at 3.2 Gbps. This is because after the > training I need to run the data at 3.2 Gbps. Basically I am > curious if GTP has oversampling capability on the transmit side > so that I can transmit 3.2 Gbps configured GTP at 400Mbps. Howdy Eddie, Could you explain the reason that you must run a training pattern? Is it for backwards compatibility with an existing 400 Mbps device? How is the far-end going to know when to switch from 400 to 3200 Mbps? If you really do need the "speed shift", I think that you could make it functional. If you're using 8b/10b and need to be backwards compatible with a 400 Mbps device, you may need to do the encoding in the fabric rather than letting the GTP do it (so that you can manually "inflate" each bit into 8 bits). MarcArticle: 122182
I'm using the v5.1 coregen fir, decimate by 2, two channel operation to process my I/Q. My system clock is 56 Mhz and the I/Q data rate is 500 ksps so I'm sure the latency is okay for the single dsp48 mac engine. Anyway, the output I get is misaligned, that is if I input a complex sinusoid and then plot the output on an x-y plot I get an ellipse instead of a circle. To figure out the misalignment I changed to input the same I sample on both channels expecting that I should get the same output on both channels. The outputs don't match. AND its not that they are shifted in time, they just do not match. I get the same result with modelsim and in my system. Does anyone have a working two channel fir example with testbench that I can use as a reference? Any ideas on why the channels would be misaligned? Thanks, ClarkArticle: 122183
Thanks Peter. I was basically just questioning if I was seeing things correctly. It makes sense that an async FIFO would behave this way. This is a temporary FIFO that I am using and I don't even need 2048 elements but I was filling the FIFO anyways. I can just back off an element and it should be fine.Article: 122184
Hello, I am using MicroBlaze in my FPGA tutorial. Read more here : http://www.fpgafromscratch.com SvenArticle: 122185
I have to use this ide vhdl driver that's supposed to link an IDE
channel to the expansion bus of an IXP425 Intel processor.
I asked why they didn't just connect the IDE signals to the GPIO, but
they said they needed to adapt to IDE/ATA cycles
Unfortunately, Linux can't recognize newer drives and I see bad
behavior in general.
I'm still wondering why they didn't use the opencore PCI driver, since
our FPGA is connected also to the PCI bus...
Can anyone help me find any problems?
Thank you,
M
Here's the code:
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
ENTITY ide IS
PORT(
-----------------------------------------------------------------------
-- GP Ports
-----------------------------------------------------------------------
P_CLK : IN std_logic; -- 1/2 MPC
CLKOUT -> 25 MHz
P_RESET_N : IN std_logic;
-----------------------------------------------------------------------
-- XScale Bus Port
-----------------------------------------------------------------------
P_DB_OUT : OUT std_logic_vector(15 DOWNTO
0);
P_DB_IN : IN std_logic_vector(15 DOWNTO
0);
P_CS_N : IN std_logic;
P_EXPB_RD_N : IN std_logic;
P_EXPB_WR_N : IN std_logic;
P_EXPB_IOWAIT_N : OUT std_logic;
P_EXPB_ADDRESS : IN std_logic_vector(10 DOWNTO
0);
P_EXPB_IRQ : OUT std_logic;
-----------------------------------------------------------------------
-- IDE Bus Ports
-----------------------------------------------------------------------
P_IDE_DB_OUT : OUT std_logic_vector(15 DOWNTO
0);
P_IDE_DB_IN : IN std_logic_vector(15 DOWNTO
0);
P_IDE_DIOR_N : OUT std_logic;
P_IDE_DIOW_N : OUT std_logic;
P_IDE_CS1_N : OUT std_logic;
P_IDE_CS3_N : OUT std_logic;
P_IDE_DA : OUT std_logic_vector(2 DOWNTO
0);
P_IDE_RESET : OUT std_logic;
P_IDE_DMACK_N : OUT std_logic;
P_IDE_INTRQ : IN std_logic;
P_IDE_IORDY : IN std_logic;
P_IDE_OE_N : OUT std_logic;
P_DBG : OUT std_logic_vector(7 DOWNTO
0)
);
END ide;
ARCHITECTURE rtl OF IDE IS
-----------------------------------------------------------------------
-- Custom Type Definitions
-----------------------------------------------------------------------
TYPE t_nowdskrd IS (IDLE, S0, S1, S2, S3);
TYPE t_nowdskwr IS (IDLE, S0, S1, S2, S3);
TYPE t_nowcnt IS (IDLE, S0, S1);
-----------------------------------------------------------------------
-- Signal Type Definitions
-----------------------------------------------------------------------
SIGNAL s_nowdskrd : t_nowdskrd;
SIGNAL s_nowdskwr : t_nowdskwr;
SIGNAL s_nowcnt : t_nowcnt;
-----------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------
-----------------------------------------------------------------------
-- DIORn/DIOWn Pulse Width: (C_IDEDELAY + 3) * ClockTick(nS) nS
-----------------------------------------------------------------------
--CONSTANT C_IDEDELAY : std_logic_vector(7 DOWNTO 0) :=
"00001111";
CONSTANT C_IDEDELAY : std_logic_vector(7 DOWNTO 0) := "00000001";
-----------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------
SIGNAL s_clk : std_logic;
SIGNAL s_reset_n : std_logic;
SIGNAL s_cs_n : std_logic;
SIGNAL s_cs1_n : std_logic;
SIGNAL s_cs3_n : std_logic;
SIGNAL s_da : std_logic_vector(2 DOWNTO 0);
SIGNAL s_cntend : std_logic;
SIGNAL s_cntstart : std_logic;
SIGNAL s_cntrdstart : std_logic;
SIGNAL s_cntwrstart : std_logic;
SIGNAL s_expb_iowait_n : std_logic;
SIGNAL s_cntdly : std_logic_vector(7 DOWNTO 0);
SIGNAL s_ide_dior_n : std_logic;
SIGNAL s_ide_diow_n : std_logic;
SIGNAL s_idedb_out : std_logic_vector(15 DOWNTO 0);
SIGNAL s_idedb_in : std_logic_vector(15 DOWNTO 0);
SIGNAL s_db_out : std_logic_vector(15 DOWNTO 0);
SIGNAL s_db_in : std_logic_vector(15 DOWNTO 0);
SIGNAL s_expb_wr_n : std_logic;
SIGNAL s_expb_rd_n : std_logic;
SIGNAL s_expb_addr : std_logic_vector(10 DOWNTO 0);
SIGNAL s_idereg : std_logic_vector(7 DOWNTO 0);
SIGNAL s_ide_irq : std_logic;
SIGNAL s_decadd : std_logic_vector(1 DOWNTO 0);
SIGNAL s_cs_reg_n : std_logic;
SIGNAL s_ide_iordy_n : std_logic;
SIGNAL s_ideout_latch : std_logic_vector(15 DOWNTO 0);
SIGNAL s_ide_oe_n : std_logic;
BEGIN
-----------------------------------------------------------------------
-- Input Port Assign
-----------------------------------------------------------------------
s_clk <= P_CLK;
s_reset_n <= P_RESET_N;
s_cs_n <= P_CS_N;
s_expb_wr_n <= P_EXPB_WR_N;
s_expb_rd_n <= P_EXPB_RD_N;
s_expb_addr <= P_EXPB_ADDRESS;
s_db_in <= P_DB_IN;
s_idedb_in <= P_IDE_DB_IN;
s_ide_irq <= P_IDE_INTRQ;
s_ide_iordy_n <= P_IDE_IORDY;
-----------------------------------------------------------------------
-- Output Port Assign
-----------------------------------------------------------------------
P_IDE_CS1_N <= s_cs1_n;
P_IDE_CS3_N <= s_cs3_n;
P_IDE_DA <= s_da;
P_IDE_DIOR_N <= s_ide_dior_n;
P_IDE_DIOW_N <= s_ide_diow_n;
P_EXPB_IOWAIT_N <= s_expb_iowait_n;
P_IDE_DB_OUT <= s_idedb_out;
P_DB_OUT <= s_ideout_latch;
P_IDE_RESET <= s_idereg(0);
P_IDE_DMACK_N <= '1'; -- MANDATORY !!!!!!
P_EXPB_IRQ <= s_ide_irq;
P_IDE_OE_N <= s_ide_oe_n;
-----------------------------------------------------------------------
-- Debug Output Port
-----------------------------------------------------------------------
-----------------------------------------------------------------------
-- Misc Signals
-----------------------------------------------------------------------
s_decadd <= s_expb_addr(10 DOWNTO 9);
s_da <= s_expb_addr(3 DOWNTO 1);
s_cntstart <= s_cntrdstart OR s_cntwrstart;
-----------------------------------------------------------------------
-- Decoder
-----------------------------------------------------------------------
CSDEC:PROCESS(s_decadd, s_cs_n)
BEGIN
s_cs1_n <= '1';
s_cs3_n <= '1';
s_cs_reg_n <= '1';
IF(s_cs_n = '0') THEN
CASE s_decadd IS
WHEN "10" =>
s_cs_reg_n <= '0';
WHEN "01" =>
s_cs1_n <= '0';
WHEN "11" =>
s_cs3_n <= '0';
WHEN OTHERS =>
s_cs3_n <= '1';
s_cs1_n <= '1';
s_cs_reg_n <= '1';
END CASE;
END IF;
END PROCESS;
-----------------------------------------------------------------------
-- Disk Read Delay Counter
-----------------------------------------------------------------------
RDCOUNT:PROCESS(s_clk, s_reset_n)
BEGIN
IF(s_reset_n = '0') THEN
s_cntdly <= (OTHERS => '0');
s_cntend <= '0';
ELSIF(s_clk 'EVENT AND s_clk = '1') THEN
CASE s_nowcnt IS
WHEN IDLE =>
s_cntdly <= (OTHERS => '0');
s_cntend <= '0';
IF(s_cntstart = '1') THEN
s_nowcnt <= S0;
END IF;
WHEN S0 =>
IF(s_ide_iordy_n = '1') THEN
s_cntdly <= s_cntdly + 1;
IF(s_cntdly = C_IDEDELAY) THEN
s_cntend <= '1';
s_nowcnt <= S1;
END IF;
END IF;
WHEN S1 =>
IF(s_cntstart = '0') THEN
s_nowcnt <= IDLE;
END IF;
WHEN OTHERS =>
s_nowcnt <= IDLE;
END CASE;
END IF;
END PROCESS;
-----------------------------------------------------------------------
-- Disk Read FSM
-----------------------------------------------------------------------
DSKRD:PROCESS(s_clk, s_reset_n)
BEGIN
IF(s_reset_n = '0') THEN
s_nowdskrd <= IDLE;
s_expb_iowait_n <= '1';
s_ide_dior_n <= '1';
s_ideout_latch <= (OTHERS => '0');
ELSIF(s_clk 'EVENT AND s_clk = '1') THEN
CASE s_nowdskrd IS
WHEN IDLE =>
s_expb_iowait_n <= '1';
s_ide_dior_n <= '1';
IF(s_cs_n = '0') THEN
IF(s_expb_rd_n = '0') THEN
s_nowdskrd <= S0;
s_expb_iowait_n <= '0';
END IF;
END IF;
WHEN S0 =>
s_ide_dior_n <= '0';
s_nowdskrd <= S1;
s_cntrdstart <= '1';
WHEN S1 =>
s_ideout_latch <= s_idedb_in;
IF(s_cntend = '1') THEN
s_cntrdstart <= '0';
s_ide_dior_n <= '1';
s_nowdskrd <= S2;
END IF;
WHEN S2 =>
s_nowdskrd <= S3;
WHEN S3 =>
s_expb_iowait_n <= '1';
IF(s_cs_n = '1') THEN
s_nowdskrd <= IDLE;
END IF;
WHEN OTHERS =>
s_nowdskrd <= IDLE;
END CASE;
END IF;
END PROCESS;
-----------------------------------------------------------------------
-- Disk Write Delay Counter
-----------------------------------------------------------------------
DSKWR:PROCESS(s_clk, s_reset_n)
BEGIN
IF(s_reset_n = '0') THEN
s_nowdskwr <= IDLE;
s_ide_diow_n <= '1';
s_idedb_out <= (OTHERS => '0');
s_ide_oe_n <= '0';
ELSIF(s_clk 'EVENT AND s_clk = '1') THEN
CASE s_nowdskwr IS
WHEN IDLE =>
s_ide_oe_n <= '0';
s_ide_diow_n <= '1';
IF(s_cs_n = '0') THEN
IF(s_expb_wr_n = '0') THEN
IF(s_da = "000") THEN
s_idedb_out <= s_db_in(7 DOWNTO 0) &
s_db_in(15 DOWNTO 8);
ELSE
s_idedb_out <= s_db_in;
END IF;
s_ide_oe_n <= '1';
s_nowdskwr <= S0;
END IF;
END IF;
WHEN S0 =>
IF(s_ide_irq='0') THEN
s_ide_diow_n <= '0';
s_nowdskwr <= S1;
s_cntwrstart <= '1';
END IF;
WHEN S1 =>
IF(s_cntend = '1') THEN
s_cntwrstart <= '0';
s_ide_diow_n <= '1';
s_nowdskwr <= S2;
END IF;
WHEN S2 =>
s_ide_oe_n <= '0';
IF(s_cs_n = '1') THEN
s_nowdskwr <= S3;
END IF;
WHEN S3 =>
s_nowdskwr <= IDLE;
WHEN OTHERS =>
s_nowdskwr <= IDLE;
END CASE;
END IF;
END PROCESS;
-----------------------------------------------------------------------
-- Disk Write FSM
-----------------------------------------------------------------------
REGWR:PROCESS(s_clk, s_reset_n)
BEGIN
IF(s_reset_n = '0') THEN
s_idereg <= (OTHERS => '0');
ELSIF(s_clk 'EVENT AND s_clk = '1') THEN
IF(s_cs_reg_n = '0') THEN
IF(s_expb_wr_n='0') THEN
s_idereg <= s_db_in(7 DOWNTO 0);
END IF;
END IF;
END IF;
END PROCESS;
END rtl;
Article: 122186As for the I2C Master, assuming no clock stretching is issued by the Slave, here is a common situation and its concerning counterparts. Usual scenario: 1) Start - b1 - b2 - Stop And relative CONCERNING scenarios: 2) Start - b1 - DELAY - b2 - Stop 3) Start - b1 - b2 - DELAY - Stop (and why not) Start - DELAY - b1 - b2 - Stop Where: b1 is a completely transferred and acked byte b2 as above DELAY is at least, more than a single SCL period. The difference between 1 and 2, 3 is the DELAY. Is such a delay allowed? If it is, which is the polarity of SCL when the master is (let's say) "stretching"? Low? (i'm not considering a multi-master bus)Article: 122187
"devices" <me@home> wrote in message news:46a4bbc3$0$37203$4fafbaef@reader3.news.tin.it... > As for the I2C Master, assuming no clock stretching > is issued by the Slave, here is a common situation and > its concerning counterparts. > > Usual scenario: > > 1) Start - b1 - b2 - Stop > > And relative CONCERNING scenarios: > > 2) Start - b1 - DELAY - b2 - Stop > 3) Start - b1 - b2 - DELAY - Stop > > (and why not) Start - DELAY - b1 - b2 - Stop > > Where: > > b1 is a completely transferred and acked byte > b2 as above > DELAY is at least, more than a single SCL period. > > The difference between 1 and 2, 3 is the DELAY. > Is such a delay allowed? If it is, which is the > polarity of SCL when the master is (let's say) > "stretching"? Low? (i'm not considering a multi-master > bus) > > > > SCL is usually an open collector style of signal. As such it can only be driven low (floated high). So that means, if the slave is inserting the DELAY it will drive SCL low for the duration of the DELAY. I believe a DELAY could occur for any of the scenerios that you mentioned. If the master is inserting the DELAY (you have a single master system) ... it doesn't matter what the state of SCL is as long as it doesn't toggle and provide a rising edge. MikeArticle: 122188
"devices" <me@home> wrote in message news:46a4bbc3$0$37203$4fafbaef@reader3.news.tin.it... > As for the I2C Master, assuming no clock stretching > is issued by the Slave, This is a bad assumption. The common situations that include delays must have the SCL clock stretching from the slave. Without that clock stretching, there's no idea when b1 or b2 start. The SCL holdoff is explicitly to allow for slave latency. <end> > here is a common situation and > its concerning counterparts. > > Usual scenario: > > 1) Start - b1 - b2 - Stop > > And relative CONCERNING scenarios: > > 2) Start - b1 - DELAY - b2 - Stop > 3) Start - b1 - b2 - DELAY - Stop > > (and why not) Start - DELAY - b1 - b2 - Stop > > Where: > > b1 is a completely transferred and acked byte > b2 as above > DELAY is at least, more than a single SCL period. > > The difference between 1 and 2, 3 is the DELAY. > Is such a delay allowed? If it is, which is the > polarity of SCL when the master is (let's say) > "stretching"? Low? (i'm not considering a multi-master > bus)Article: 122189
I am using the Xilinx ML403 board. It is not cheap but it has everything on board. I am writing a tutorial on how to use this board to implement my own design. Read more here: http://www.fpgafromscratch.com SvenArticle: 122190
Hello, I am using the Micron model in my simulations. See my blog: http://www.fpgafromscratch.com (part 20). SvenArticle: 122191
I am using the ML403 board from Xilinx. It came with ISE 8.1 and EDK 8.1 but I could upgrade to ISE 9.1 and EDK 9.1 for free. Read more in my blog: http://www.fpgafromscratch.com SvenArticle: 122192
Hello, I have been using Xilinx ISE and EDK tools successfully. I also implemented the new USB cable drivers. See my blog: http://www.fpgafromscratch.com (Part 25). SvenArticle: 122193
Hey everyone, I just recently upgraded from ISE 8.2i to 9.2i (service pack 1) and now i'm getting an error in my UCF file. Error appears while running map. ERROR:Pack:946 - The I/O component "o_ddr_clk" has an illegal IOSTANDARD value. Components of type IOB do not support IOSTANDARD LVDS_25. Please correct the IOSTANDARD property value. Here's the part of the UCF file it's referring to: NET "o_ddr_clk" IOSTANDARD = LVDS_25; As far as i knew (or could check online today) LVDS_25 is still a valid IOSTANDARD value for Virtex II Pro (which is what im using). Anyone else get a similar error after an upgrade to 9.2.01i or heard of anything like this? Cheers, Rob.Article: 122194
"cpope" <cepope@nc.rr.com> wrote in message news:46a4a3e7$0$31280$4c368faf@roadrunner.com... > > Does anyone have a working two channel fir example with testbench that I > can > use as a reference? Any ideas on why the channels would be misaligned? I don't have an answer for you, but I did a 2-channel interpolating FIR using the FIR Compiler and it worked fine. At the moment I am implementing both 8-channel decimation and 8-channel interpolation filter, but again using the compiler. I believe the compiler has less bugs than the MAC FIR... /MikhailArticle: 122195
"John_H" <newsgroup@johnhandwork.com> wrote in message news:13a9hnjl693afc@corp.supernews.com... >>>>>>>> As for the I2C Master, assuming no clock stretching >>>>>>>> is issued by the Slave, > This is a bad assumption. The common situations that include delays must > have the SCL clock stretching from the slave. Without that clock > stretching, there's no idea when b1 or b2 start. The SCL holdoff is > explicitly to allow for slave latency. For the sake of generality, the clock stretching not only applies to a byte level, it also applies to a bit level. Fortunately common situations are not general situations or it would mean that every i2c slave device would be always slower with respect to its specifications. So i can always take into account the latency as a preliminary step. But what i was investigating on was the possibility of the master to introduce a delay.Article: 122196
"Mike Lewis" <someone@micrsoft.com> wrote in message news:c2ac4$46a4c534$401a86c3$18437@PRIMUS.CA... > > > "devices" <me@home> wrote in message > news:46a4bbc3$0$37203$4fafbaef@reader3.news.tin.it... > > As for the I2C Master, assuming no clock stretching > > is issued by the Slave, here is a common situation and > > its concerning counterparts. > > > > Usual scenario: > > > > 1) Start - b1 - b2 - Stop > > > > And relative CONCERNING scenarios: > > > > 2) Start - b1 - DELAY - b2 - Stop > > 3) Start - b1 - b2 - DELAY - Stop > > > > (and why not) Start - DELAY - b1 - b2 - Stop > > > > Where: > > > > b1 is a completely transferred and acked byte > > b2 as above > > DELAY is at least, more than a single SCL period. > > > > The difference between 1 and 2, 3 is the DELAY. > > Is such a delay allowed? If it is, which is the > > polarity of SCL when the master is (let's say) > > "stretching"? Low? (i'm not considering a multi-master > > bus) > > > > > > > > > > SCL is usually an open collector style of signal. As such it can only be > driven low (floated high). So that means, if the slave is inserting the > DELAY it will drive > SCL low for the duration of the DELAY. > > I believe a DELAY could occur for any of the scenerios that you mentioned. > > If the master is inserting the DELAY (you have a single master system) ... > it doesn't matter what the state of SCL is as long as it doesn't toggle and > provide a rising edge. > > Mike > Mike, thanks.Article: 122197
On Jul 23, 1:12 pm, "devices" <me@home> wrote: > "John_H" <newsgr...@johnhandwork.com> wrote in message > > news:13a9hnjl693afc@corp.supernews.com... > > >>>>>>>> As for the I2C Master, assuming no clock stretching > >>>>>>>> is issued by the Slave, > > This is a bad assumption. The common situations that include delays must > > have the SCL clock stretching from the slave. Without that clock > > stretching, there's no idea when b1 or b2 start. The SCL holdoff is > > explicitly to allow for slave latency. > > For the sake of generality, the clock stretching not only applies > to a byte level, it also applies to a bit level. Fortunately common > situations are not general situations or it would mean that every > i2c slave device would be always slower with respect to its > specifications. So i can always take into account the latency as > a preliminary step. But what i was investigating on was the possibility > of the master to introduce a delay. In a single-master system you have complete control over the delay between SCL pulses. AFAIK there is no maximum delay spec for any of the standard (100K and 400KHz) timings, however it's not considered good practice to start a transfer you're not ready to complete (as a master). Also IIRC the SMbus allows for timeouts to prevent bus hang, so in that case there are maximum times. SCL is never presumed to be a continuous clock running at the nominal frequency. Delays from one bit to the next or from start condition to the first bit, etc. are specified as minimums. In a typical master, it wouldn't make sense to introduce a delay except between data bytes. For most I2C access you can accomplish multiple byte access to a slave either by continuous data bursting or by starting a new access. This is certainly true when accessing EEPROM. In such cases it doesn't make sense for the master to introduce delays in excess of the time it would take to stop and start a new transfer. Just out of curiosity, whay would you want to add delays from the master?Article: 122198
<bart.deboeck@gmail.com> wrote > > I'd like to learn programming FPGAs for HPC applications. I am, > however, a newbie in this field. I do have a software engineering > background. Newbie in FPGA, HPC or both? :) > Does anyone want to be so kind to suggest a development platform to > start with? > > What do you think of solutions like: > - http://www.drccomputer.com/drc/products.html Xilinx LX200 > - http://www.xtremedatainc.com/ Altera Stratix-II S180 > - http://www.mitrionics.com/ This one is not a platform, it's software for the 2 previous ones (and others). HPC is a huge domain. So if you don't tell what kind of computation you want to do, it's somewhat difficult to suggest anything. bio-computing is rather different from financial computing for instance. MarcArticle: 122199
Hello - I am trying to use the Xilinx MIG version 1.72 to generate a working interface for the DDR2 memory on the Xilinx ML501 eval board. I am having a bit of trouble. I am able to simulate the controller and testbench just fine using ModelSim, but seem to be having issues getting it to work in hardware. At the moment, I am simply checking the output of the phy_init_done signal, which does not go high at any point, which indicates a problem to me. I have not yet been able to delve much deeper into where things are getting stuck. I plan to use ChipScope to try to see what is going on, but I wonder before I get too far, if anybody else has tried a similar configuration? What experiences (good/bad) have people had with the MIG and Virtex-5 DDR2 designs? It would make me feel better if somebody out there had gotten it to work - it sounds like - from reading this group at least, that there are no shortage of issues with this stuff. Thanks, Ben
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