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Why don't your own code that samples the lines of interest for the first few moments that you care about. The data can be stored in BRAM and then read out any way and at any time you please. It basically is what Chipscope does, just one shot and immediately on. ---Matthew Hicks > Hi, > > I have to record some events immediately atfer configuration of my > FPGA (Spartan-3 1500). Chipscope's ILA and ICON are included and work > well. Unfortunately, I'm not fast enough to hit F5 in time and arming > the ILA in this way:-(. How can it be armed earlier, but that would > mean during core generation. > The FPGA is configured by a micro controller via JTAG. After finishing > the configuration this micro access the FPGA and I've to record these > cycles. Of course, I *have'nt* access to the micro's code. > Thanks > > Tom >Article: 122226
Hi, I have to design with 3 input adder, i.e. D = A + B + C, in Spartan 3E. The addition has to be finished in one 153.6MHz clock. When I do PAR, I met timing violations. Can anybody give me some advices on how to implement this design? (I can't upgrade to other device because of cost). Thanks very much. best regards skyworldArticle: 122227
If your micro controller has a JTAG connection you may connect it to Scanseer software www.scanseer.com (this is a program for boundary scan similar to ChipScope but it works with all JTAG enabled devices). Then you can observe micro controller's pins and view their waveforms.Article: 122228
devices wrote: > "Jim Granville" <no.spam@designtools.maps.co.nz> wrote in message > news:46a51c8d$1@clear.net.nz... > >> Serial EE proms, have chosen a polling system for their 'wait' >> requirements. >> >> >> -jg > > Yeah, i notice the Ack polling in Microchip's seeproms. > > By the way, are royalties still due to Philips? Or have the copyrights > expired. Just curious, i read something about it time ago. > > bye, Jim If you limit yourself to 400 kHz and 10 bit addressing, no royalties. Our company contacted the Philips legal folks a couple years ago to clear it up for ourselves.Article: 122229
You are probably way off timing depending on the bit-width of your words. You could use a pipelined adder, if you can stand the extra latency. If you need the add completed in a single stage, for let's say 16-bit words, your not going to hit 150 MHz on that device, but you could go faster by using a 3-2 compressor and then adding the final two terms using a carry look-ahead adder. ---Matthew Hicks > Hi, > > I have to design with 3 input adder, i.e. D = A + B + C, in Spartan > 3E. The addition has to be finished in one 153.6MHz clock. When I do > PAR, I met timing violations. Can anybody give me some advices on how > to implement this design? (I can't upgrade to other device because of > cost). Thanks very much. > > best regards > > skyworld >Article: 122230
skyworld wrote: > Hi, > > I have to design with 3 input adder, i.e. D = A + B + C, in Spartan > 3E. The addition has to be finished in one 153.6MHz clock. When I do > PAR, I met timing violations. Can anybody give me some advices on how > to implement this design? (I can't upgrade to other device because of > cost). Thanks very much. > > > best regards > > skyworld How large are the vectors you're adding? Have you looked at the timing analysis of your path to sanity-check the timing violations? If you have long routing delays, that can be accommodated with relative placements to keep the register-to-adder and adder-to-adder routing delays down. Getting on and off the carry chain may limit you at this speed. You may have to ask yourself if your requirement is *really* three adds in one cycle. What do you do with the data after the clock? Comparing to a constant, for instance, would allow you to take the difference of the constant with A in the first cycle and compare to a B+C result rather than a direct comparison to A+B+C. If the logic generating any two vectors is simple enough, the values could be generated and the difference taken before the first register. I do know that a divider that needed to completely daisy-chain four 14-bit add/subtract stages per cycle was only happy at 66 MHz with some RLOC constraints. Your situation is a little better since you're not MSB carry-out to LSB, but not much. The time to get on and off that carry chain may swamp your results. - John_HArticle: 122231
On 7 24 , 9 48 , John_H <newsgr...@johnhandwork.com> wrote: > skyworld wrote: > > Hi, > > > I have to design with 3 input adder, i.e. D = A + B + C, in Spartan > > 3E. The addition has to be finished in one 153.6MHz clock. When I do > > PAR, I met timing violations. Can anybody give me some advices on how > > to implement this design? (I can't upgrade to other device because of > > cost). Thanks very much. > > > best regards > > > skyworld > > How large are the vectors you're adding? > > Have you looked at the timing analysis of your path to sanity-check the > timing violations? If you have long routing delays, that can be > accommodated with relative placements to keep the register-to-adder and > adder-to-adder routing delays down. Getting on and off the carry chain > may limit you at this speed. > > You may have to ask yourself if your requirement is *really* three adds > in one cycle. What do you do with the data after the clock? Comparing > to a constant, for instance, would allow you to take the difference of > the constant with A in the first cycle and compare to a B+C result > rather than a direct comparison to A+B+C. If the logic generating any > two vectors is simple enough, the values could be generated and the > difference taken before the first register. > > I do know that a divider that needed to completely daisy-chain four > 14-bit add/subtract stages per cycle was only happy at 66 MHz with some > RLOC constraints. Your situation is a little better since you're not > MSB carry-out to LSB, but not much. The time to get on and off that > carry chain may swamp your results. > > - John_H Hi John, in fact this design is for sigme-delta transmission modulator. I need a filter to transform 10 bit parallel input data (15.36MHz) to one bit output stream (153.6MHz). The filter are composed by 3 stage adders. Each adder has three inputs, i.e., what I have mentioned D = A + B + C. Every adder has to finish A + B + C within one 153.6MHz clock so that 153.6Mbps data stream works well. I have tried to use pipeline adder, but for this structure failed. So I am searching a way for "fast adder algorithm", or "fast three input adder algorithm", which could be implemented in Spartan 3E and runs fast enough. Thanks very much. skyworldArticle: 122232
On 24 Jul., 15:34, Matthew Hicks <mdhic...@uiuc.edu> wrote: > Why don't your own code that samples the lines of interest for the first > few moments that you care about. The data can be stored in BRAM and then > read out any way and at any time you please. It basically is what Chipscope > does, just one shot and immediately on. Yes you are right, but this is a lot of work more than using Chipscope. If any where the protocol description for communication between ILA and ICON, than I could do my own ILA and using Chipscope's Analyzer. TomArticle: 122233
Hi there,
I have a Xilinx university program Virtex-II board and I'm trying to
get my head round the serial port on it. I am using EDK and
implementing a C program on a MicroBlaze, and using EDK's uartlite ip
core connected to the OPB bus.
I'm using XPS 9.1.02i.
I have written a simple C program which reads one character at a time
from stdin and writes its hex value to stdout. For example, if it sees
an "A" character (value 0x41) it prints "<41>" to stdout. stdin and
stdout are both connected to the serial port. The program is listed
here:
#include <stdio.h>
#include "xgpio.h"
#include "xstatus.h"
#include "xparameters.h"
int main(void) {
xil_printf("\n---entering main()---\n\n");
for(;;) {
unsigned char c;
volatile long delay=0;
while(fread(&c,1,1,stdin)) {
if (c=='A')
xil_printf("<CR>\r\n");
else
xil_printf("<%x>",c);
}
xil_printf("fread returned 0\r\n");
}
return 0;
}
When I use a terminal program to talk to the board, the board echoes
back the hex values, but after every character it also echos a zero
value. For example, if I type "beef" I get the result:
<62><0><65><0><65><0><66><0>
This happens for all characters except for carriage return (0x0A) and
line feed (0x0D), which do not get trailing NULs. All other control
characters and all printable characters that I've tried have a
trailing zero. (This is why I translate 'A' into a newline sequence
rather than \r or \n; to make sure my program wasn't treating them any
differently.)
Using Portmon I've determined that my terminal program is only sending
the characters that I'd expect, it's not sending NULs that I don't
want it to.
Does anyone know what the cause of these NULs is? They aren't there
when they leave my computer, but they appear when they arrive at the C
program on the MicroBlaze. In between is the Windows XP device driver,
the link, and the opb_uartlite. I suspect the uartlite is at fault,
but I'm new to EDK and I'm not sure how to go about poking at its
guts.
Phil
Article: 122234Would it be possible to build enough 3-input adders to produce enough data to meet the 153.6Mb/s requirement and operate them in a multiplexed fashion. ---Matthew Hicks > On 7 24 , 9 48 , John_H <newsgr...@johnhandwork.com> wrote: > >> skyworld wrote: >> >>> Hi, >>> >>> I have to design with 3 input adder, i.e. D = A + B + C, in Spartan >>> 3E. The addition has to be finished in one 153.6MHz clock. When I do >>> PAR, I met timing violations. Can anybody give me some advices on >>> how to implement this design? (I can't upgrade to other device >>> because of cost). Thanks very much. >>> >>> best regards >>> >>> skyworld >>> >> How large are the vectors you're adding? >> >> Have you looked at the timing analysis of your path to sanity-check >> the timing violations? If you have long routing delays, that can be >> accommodated with relative placements to keep the register-to-adder >> and adder-to-adder routing delays down. Getting on and off the carry >> chain may limit you at this speed. >> >> You may have to ask yourself if your requirement is *really* three >> adds in one cycle. What do you do with the data after the clock? >> Comparing to a constant, for instance, would allow you to take the >> difference of the constant with A in the first cycle and compare to a >> B+C result rather than a direct comparison to A+B+C. If the logic >> generating any two vectors is simple enough, the values could be >> generated and the difference taken before the first register. >> >> I do know that a divider that needed to completely daisy-chain four >> 14-bit add/subtract stages per cycle was only happy at 66 MHz with >> some RLOC constraints. Your situation is a little better since >> you're not MSB carry-out to LSB, but not much. The time to get on >> and off that carry chain may swamp your results. >> >> - John_H >> > Hi John, > > in fact this design is for sigme-delta transmission modulator. I need > a filter to transform 10 bit parallel input data (15.36MHz) to one bit > output stream (153.6MHz). The filter are composed by 3 stage adders. > Each adder has three inputs, i.e., what I have mentioned D = A + B + > C. Every adder has to finish A + B + C within one 153.6MHz clock so > that 153.6Mbps data stream works well. I have tried to use pipeline > adder, but for this structure failed. So I am searching a way for > "fast adder algorithm", or "fast three input adder algorithm", which > could be implemented in Spartan 3E and runs fast enough. Thanks very > much. > > skyworld >Article: 122235
I currently use Altera Quartus along with ModelSim for FPGA designs using Verilog. In ModelSim I use the "$random" term to create a random driver. My company is considering updating its tools so that we can get code coverage capabilities and possibly automatically generate block diagrams from the Verilog code. I've looked into Aldec ActiveHDL and it seems like most of this software provided redundant functionality to that of Altera Quartus. So strictly from a simulation and code coverage standpoint which tool is better, considering that I would like to use Verilog/SystemVerilog for a random driven, self-checking simulation environment? Does Aldec support random stimuli in their tool outside of using SystemC?Article: 122236
Peter, Asking weird questions about FPGAs means you never have to say you are "sorry." Goes with the territory. Austin Peter C. Wallace wrote: > On Mon, 23 Jul 2007 17:01:49 -0700, austin wrote: > >> Peter, >> >> Have you checked that this pin is not a dual use pin (also used for >> configuration)? >> >> Austin > > No, its just a regular pin (which is why we were so confused that it > mattered), BUT Looks like its a problem with our USB configurator, We > hacked our configurator CPLD so we could configure via a parallel port and > that works fine. Must be we are corrupting the last few bytes of > configuration data somehow. Sorry for the trouble. > > Peter Wallace > > >Article: 122237
On Jul 23, 9:56 pm, bgelb.mit....@gmail.com wrote: > Hello - > > I am trying to use the Xilinx MIG version 1.72 to generate a working > interface for the DDR2 memory on the Xilinx ML501 eval board. I am > having a bit of trouble. > > I am able to simulate the controller and testbench just fine using > ModelSim, but seem to be having issues getting it to work in hardware. > At the moment, I am simply checking the output of the phy_init_done > signal, which does not go high at any point, which indicates a problem > to me. I have not yet been able to delve much deeper into where things > are getting stuck. > > I plan to use ChipScope to try to see what is going on, but I wonder > before I get too far, if anybody else has tried a similar > configuration? What experiences (good/bad) have people had with the > MIG and Virtex-5 DDR2 designs? It would make me feel better if > somebody out there had gotten it to work - it sounds like - from > reading this group at least, that there are no shortage of issues with > this stuff. > > Thanks, > Ben Did you do a behavioral simulation? Do a post-PAR simulation and check if the initialization still completes. Also did you change the controller to work with the ML501? The ML501 has a SODIMM device on it. Check the following link on information on how to change the controller to work with a SODIMM memory: http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=25040 JacoArticle: 122238
Paul, Bonjour, Il est meilleur si vous ouvrez un 'web case': http://www.xilinx.com/support/clearexpress/websupport.htm Vous recevrez une réponse beaucoup plus rapidement... Austin Paul wrote: > Hi everybody, I've a problem with the mdio_0 signal of the hard temac available in the virtex4. Writting to the PHY is good but reading gives erroneous results. With an oscilloscope I can see that the voltage does not excess 1V (3.3V expected) during the read phase, during write phase I have 3.3V. A conflict with the FPGA is possible because the PHY is alone on the management bus. Is it possible that the tristate into the FPGA does not work ? Any ideas ? Thank you.Article: 122239
"skyworld" <chenyong20000@gmail.com> wrote in message news:1185286696.499801.126190@i13g2000prf.googlegroups.com... > On 7 24 , 9 48 , John_H <newsgr...@johnhandwork.com> wrote: >> skyworld wrote: >> > Hi, >> >> > I have to design with 3 input adder, i.e. D = A + B + C, in Spartan >> > 3E. The addition has to be finished in one 153.6MHz clock. When I do >> > PAR, I met timing violations. Can anybody give me some advices on how >> > to implement this design? (I can't upgrade to other device because of >> > cost). Thanks very much. >> >> > best regards >> >> > skyworld >> >> How large are the vectors you're adding? >> >> Have you looked at the timing analysis of your path to sanity-check the >> timing violations? If you have long routing delays, that can be >> accommodated with relative placements to keep the register-to-adder and >> adder-to-adder routing delays down. Getting on and off the carry chain >> may limit you at this speed. >> >> You may have to ask yourself if your requirement is *really* three adds >> in one cycle. What do you do with the data after the clock? Comparing >> to a constant, for instance, would allow you to take the difference of >> the constant with A in the first cycle and compare to a B+C result >> rather than a direct comparison to A+B+C. If the logic generating any >> two vectors is simple enough, the values could be generated and the >> difference taken before the first register. >> >> I do know that a divider that needed to completely daisy-chain four >> 14-bit add/subtract stages per cycle was only happy at 66 MHz with some >> RLOC constraints. Your situation is a little better since you're not >> MSB carry-out to LSB, but not much. The time to get on and off that >> carry chain may swamp your results. >> >> - John_H > > Hi John, > > in fact this design is for sigme-delta transmission modulator. I need > a filter to transform 10 bit parallel input data (15.36MHz) to one bit > output stream (153.6MHz). The filter are composed by 3 stage adders. > Each adder has three inputs, i.e., what I have mentioned D = A + B + > C. Every adder has to finish A + B + C within one 153.6MHz clock so > that 153.6Mbps data stream works well. I have tried to use pipeline > adder, but for this structure failed. So I am searching a way for > "fast adder algorithm", or "fast three input adder algorithm", which > could be implemented in Spartan 3E and runs fast enough. Thanks very > much. > > > skyworld Still no answer to my questions: What is the size of the vectors? Have you sanity-checked the timing report for long routing? Is there somethings you can do before or after this "I have to have it now" cycle? It's not obvious to me you can't simply move some things around. Where do the three values come from? Are the each results of previous 3-value adders? So terribly often, the problem can be repartitioned without compromising the system requirements. If you isolate your problem to a 3-value adder, you won't achieve your goals. If you expand your problem to the stages before and after or to the system level, you can make this work. You just probably can't make a 3-value adder work. And if you do answer my questions or provide more details, you might also include the speedgrade device you're targeting. - John_HArticle: 122240
"John_H" <newsgroup@johnhandwork.com> wrote in message news:minpi.2790$b04.1328@trndny06... > devices wrote: > > "Jim Granville" <no.spam@designtools.maps.co.nz> wrote in message > > news:46a51c8d$1@clear.net.nz... > > > >> Serial EE proms, have chosen a polling system for their 'wait' > >> requirements. > >> > >> > >> -jg > > > > Yeah, i notice the Ack polling in Microchip's seeproms. > > > > By the way, are royalties still due to Philips? Or have the copyrights > > expired. Just curious, i read something about it time ago. > > > > bye, Jim > > If you limit yourself to 400 kHz and 10 bit addressing, no royalties. > Our company contacted the Philips legal folks a couple years ago to > clear it up for ourselves. ThanksArticle: 122241
"skyworld" <chenyong20000@gmail.com> wrote in message news:1185286696.499801.126190@i13g2000prf.googlegroups.com... > > in fact this design is for sigme-delta transmission modulator. I need > a filter to transform 10 bit parallel input data (15.36MHz) to one bit > output stream (153.6MHz). The filter are composed by 3 stage adders. > Each adder has three inputs, i.e., what I have mentioned D = A + B + > C. Every adder has to finish A + B + C within one 153.6MHz clock so > that 153.6Mbps data stream works well. I have tried to use pipeline > adder, but for this structure failed. So I am searching a way for > "fast adder algorithm", or "fast three input adder algorithm", which > could be implemented in Spartan 3E and runs fast enough. Thanks very > much. > > > skyworld > As mentioned, if you're not feeding back your outputs into your filter, then you probably can pipeline this. Can you let us know why this doesn't work? if rising_edge(clock) then A_plus_B <= A + B; C_delay <= C; A_plus_B_plus_C <= A_plus_B + C_delay; end if; HTH., Syms.Article: 122242
> You can connect one port of BRAM with one lmb_bram controller which in > turn is attached to one of the LMB buses of your MicroBlaze. If you > choose the DLMB the MicroBlaze will see additional data memory. Do not > forget to assign an appropriate address range to the BRAM. > > The other port of the BRAM can be connected to your custon IP. Yes, I also did exactly this, and it works very well. The CPU can read/write data in the BRAM block via one port, and your custom core can do the same via the other port. It's very useful. In another case, I needed DMA accesses via OPB and opb_central_dma to my BRAM block ; I also needed the CPU to access it, and a custom core needed access to it too. So I used opb_bram controller on the OPB bus connected to BRAM port A ; custom core to BRAM port B ; DMA and CPU access BRAM via OPB. Have a nice day, PierreArticle: 122243
"Paul" <paul.peronnard@imag.fr> wrote in message news:eea82cc.-1@webx.sUN8CHnE... > Hi everybody, I've a problem with the mdio_0 signal of the hard temac > available in the virtex4. Writting to the PHY is good but reading gives > erroneous results. With an oscilloscope I can see that the voltage does > not excess 1V (3.3V expected) during the read phase, during write phase I > have 3.3V. A conflict with the FPGA is possible because the PHY is alone > on the management bus. Is it possible that the tristate into the FPGA does > not work ? Any ideas ? Thank you. Your PHY is expecting a pullup resistor on the bus. /MikhailArticle: 122244
Skyworld, you still have not told us the width of the three vectors that you want to add at 153.6 MHz. If the width is one bit, i.e. you want to add three serial bitstreams, this is very simple and takes only 4 LUTs olus two flip-flops, with a combinatorial delay through only two LUTs. That should easily run at your 153.6 MHz. Peter Alfke ============= On Jul 24, 8:47 am, "Symon" <symon_bre...@hotmail.com> wrote: > "skyworld" <chenyong20...@gmail.com> wrote in message > > news:1185286696.499801.126190@i13g2000prf.googlegroups.com... > > > in fact this design is for sigme-delta transmission modulator. I need > > a filter to transform 10 bit parallel input data (15.36MHz) to one bit > > output stream (153.6MHz). The filter are composed by 3 stage adders. > > Each adder has three inputs, i.e., what I have mentioned D = A + B + > > C. Every adder has to finish A + B + C within one 153.6MHz clock so > > that 153.6Mbps data stream works well. I have tried to use pipeline > > adder, but for this structure failed. So I am searching a way for > > "fast adder algorithm", or "fast three input adder algorithm", which > > could be implemented in Spartan 3E and runs fast enough. Thanks very > > much. > > > skyworld > > As mentioned, if you're not feeding back your outputs into your filter, then > you probably can pipeline this. Can you let us know why this doesn't work? > > if rising_edge(clock) then > A_plus_B <= A + B; > C_delay <= C; > A_plus_B_plus_C <= A_plus_B + C_delay; > end if; > > HTH., Syms.Article: 122245
We still do not know the width of the adder. If it's a bit-serial 3-input adder, that takes only 4 LUTs plus two flip-flops, and the combinatorial chain is only through two LUTs, so it should easily meet the speed requirements. Peter Alfke, Xilinx Applications On Jul 24, 7:18 am, skyworld <chenyong20...@gmail.com> wrote: > On 7 24 , 9 48 , John_H <newsgr...@johnhandwork.com> wrote: > > > > > skyworld wrote: > > > Hi, > > > > I have to design with 3 input adder, i.e. D = A + B + C, in Spartan > > > 3E. The addition has to be finished in one 153.6MHz clock. When I do > > > PAR, I met timing violations. Can anybody give me some advices on how > > > to implement this design? (I can't upgrade to other device because of > > > cost). Thanks very much. > > > > best regards > > > > skyworld > > > How large are the vectors you're adding? > > > Have you looked at the timing analysis of your path to sanity-check the > > timing violations? If you have long routing delays, that can be > > accommodated with relative placements to keep the register-to-adder and > > adder-to-adder routing delays down. Getting on and off the carry chain > > may limit you at this speed. > > > You may have to ask yourself if your requirement is *really* three adds > > in one cycle. What do you do with the data after the clock? Comparing > > to a constant, for instance, would allow you to take the difference of > > the constant with A in the first cycle and compare to a B+C result > > rather than a direct comparison to A+B+C. If the logic generating any > > two vectors is simple enough, the values could be generated and the > > difference taken before the first register. > > > I do know that a divider that needed to completely daisy-chain four > > 14-bit add/subtract stages per cycle was only happy at 66 MHz with some > > RLOC constraints. Your situation is a little better since you're not > > MSB carry-out to LSB, but not much. The time to get on and off that > > carry chain may swamp your results. > > > - John_H > > Hi John, > > in fact this design is for sigme-delta transmission modulator. I need > a filter to transform 10 bit parallel input data (15.36MHz) to one bit > output stream (153.6MHz). The filter are composed by 3 stage adders. > Each adder has three inputs, i.e., what I have mentioned D = A + B + > C. Every adder has to finish A + B + C within one 153.6MHz clock so > that 153.6Mbps data stream works well. I have tried to use pipeline > adder, but for this structure failed. So I am searching a way for > "fast adder algorithm", or "fast three input adder algorithm", which > could be implemented in Spartan 3E and runs fast enough. Thanks very > much. > > skyworldArticle: 122246
there is a pullup on the bus. I made another test: decreasing the drive strength of the FPGA from 12mA to 2mA allow MDIO to reach 3.3V ...Article: 122247
Does anyone sell a very tiny board with a Spartan 3 (or 3E, 3A, 3AN) and regulators to run from a 3.3V supply? I only need a handful of 3.3V CMOS I/O pins, but the whole module needs to be really tiny, so I can cram it into an existing device that has little room to spare. At most, it could be about 50 mm square, and should be very low profile. If nothing like that is available, I'll design one using an XC3S400-4TQ144 (or perhaps XC3S250E-4TQ144), but I'd like to avoid spending time on that if possible. Thanks! EricArticle: 122248
"Eric Smith" <eric@brouhaha.com> wrote in message news:m3ps2haad5.fsf@donnybrook.brouhaha.com... > Does anyone sell a very tiny board with a Spartan 3 (or 3E, 3A, 3AN) > and regulators to run from a 3.3V supply? I only need a handful of > 3.3V CMOS I/O pins, but the whole module needs to be really tiny, so I can > cram it into an existing device that has little room to spare. At most, > it could be about 50 mm square, and should be very low profile. > > If nothing like that is available, I'll design one using an XC3S400-4TQ144 > (or perhaps XC3S250E-4TQ144), but I'd like to avoid spending time on that > if > possible. > > Thanks! > Eric Hi Eric, There's a bloke (John Adair) that posts on here whose company sells stuff like that. http://www.enterpoint.co.uk/component_replacements/craignell.html A little longer than 50mm, but less area than 50x50. They may be a little damp when you get them. Cheers, Syms.Article: 122249
skyworld <chenyong20000@gmail.com> wrote: > Hi, > I have to design with 3 input adder, i.e. D = A + B + C, in Spartan > 3E. The addition has to be finished in one 153.6MHz clock. When I do > PAR, I met timing violations. Can anybody give me some advices on how > to implement this design? (I can't upgrade to other device because of > cost). Thanks very much. Why can't you pipeline like always @(posedge clk) begin AB<= A+B; D <= AB + C; end ? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
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