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On 17 Aug., 13:22, lembke.ste...@googlemail.com wrote: > hey, > > in FPGA-Editor i can choose a slice and type in an equation for this > block. > i need information, where i can find this equation (truth table) in > the generated bitstream and how > they are arranged. > > thanks for help not available fully, need write your RE tools to gain this info you can try generate LL file, but that file doesnt have all the needed some need still heavy RE :( AnttiArticle: 123151
i found the location in the bitstream, where 'result-column' can be found. when i use all 4 variables in the function, i can find exact these column of the truth table in the bitstream. (A3*A1)+(A2*A4) 05 37 00 00 => 0000 0101 0011 0111 0000 0000 0000 0000 (is the same, as in the truth table) but when i use less than 4 variables, the bits are not in the right order (but the number of 1's is correct) (A1+A2)*A4 00 77 00 00 => 0000 0000 0111 0111 0000 0000 0000 0000 (in other order) or A1*A3: 05 05 00 00 => 0000 0101 0000 0101 0000 0000 0000 0000Article: 123152
<lembke.stefan@googlemail.com> wrote in message news:1187349760.044999.83000@19g2000hsx.googlegroups.com... > hey, > > in FPGA-Editor i can choose a slice and type in an equation for this > block. > i need information, where i can find this equation (truth table) in > the generated bitstream and how > they are arranged. > > thanks for help > Hey backatyou, I first did this 20 years ago with Xilinx parts. I guess the method hasn't changed. 1) Make a design. 2) Generate bitstream. 3) Edit function generator in XACT, sorry, FPGA editor. 4) Generate bitstream. 5) See what's changed from 2). Not exactly rocket science, but effective nonetheless. You'll find the CLBs/Slices distributed regularly throughout the bitstream, I bet. HTH., Syms.Article: 123153
yes, that's the way i go. but don't understand, why the order changes, when i use less than 4 variables ....Article: 123154
On 17 Aug., 14:28, lembke.ste...@googlemail.com wrote: > i found the location in the bitstream, where 'result-column' can be > found. when i use all 4 variables in the function, i can find exact > these column of the truth table in the bitstream. > > (A3*A1)+(A2*A4) > 05 37 00 00 => 0000 0101 0011 0111 0000 0000 0000 0000 (is the > same, as in the truth table) > > but when i use less than 4 variables, the bits are not in the right > order (but the number of 1's is correct) > > (A1+A2)*A4 > 00 77 00 00 => 0000 0000 0111 0111 0000 0000 0000 0000 (in other > order) > > or > > A1*A3: > 05 05 00 00 => 0000 0101 0000 0101 0000 0000 0000 0000 the LUT inputs are swapped randomly duting PR so that explains why the appear in different places think there are some settings to free LUT inputs but that may not always work AnttiArticle: 123155
<lembke.stefan@googlemail.com> wrote in message news:1187353683.189676.87220@k79g2000hse.googlegroups.com... >i found the location in the bitstream, where 'result-column' can be > found. when i use all 4 variables in the function, i can find exact > these column of the truth table in the bitstream. > > (A3*A1)+(A2*A4) > 05 37 00 00 => 0000 0101 0011 0111 0000 0000 0000 0000 (is the > same, as in the truth table) > > but when i use less than 4 variables, the bits are not in the right > order (but the number of 1's is correct) > > (A1+A2)*A4 > 00 77 00 00 => 0000 0000 0111 0111 0000 0000 0000 0000 (in other > order) > > or > > A1*A3: > 05 05 00 00 => 0000 0101 0000 0101 0000 0000 0000 0000 > So, firstly, there only 16 bits in the LUT, right. You've written 16. So, let's look at just the first 16 bits of your truth table. In the second example, the A3 bit is 'don't care' so the equation implemented is :- ((A1+A2)*A4 * A3) + ((A1+A2)*A4 * ~A3) HTH., Syms.Article: 123156
"Symon" <symon_brewer@hotmail.com> wrote in message news:fa44vo$dfg$1@aioe.org... >> > So, firstly, there only 16 bits in the LUT, right? You've written 32. So, Whoops, correction above!Article: 123157
yes, 16 bits, i know. but the tip with the don't cares is great. thanksArticle: 123158
Thanks! As for the button, ChipHit lets you add it's search engine to Firefox's search engine pulldown as well as IE 7's search engine pulldown. That way, if you need a quick answer you can pulldown your list of search engines, select ChipHit, and search away! To add it, simply goto www.chiphit.com and select the link that says "Add ChipHit to Your Browser Add ChipHit to Your Browser's Search Bar". For Firefox users, the search bar pulldown should automatically highlight itself, whereby you can pull it down and add ChipHit. See http://www.chiphit.com/blog/files/df04e631b42554630d908f3686b1be7f-4.html for more information on this topic. On Aug 16, 6:33 am, "Symon" <symon_bre...@hotmail.com> wrote: > "ted" <ted.boyds...@gmail.com> wrote in message > > news:1187187861.573794.9990@e9g2000prf.googlegroups.com...> Hi, > > > So, the next time you are searching for an ASIC, FPGA, or EDA topic, > > why not check outhttp://www.chiphit.com. > > > Thanks, > > Ted > > Hi Ted, > That's pretty cool, looks like you put a fair bit of effort into it, it > seems to work well! > > BTW., if the requirement is just to search a single site, e.g. xilinx.com , > Google toolbar lets you create a custom search button. You install the > toolbar, navigate to xilinx.com, right click in the search box on that page, > and choose 'Generate custom search...' . A button now appears on the > toolbar. (I think I posted this before, but I was quite pleased to find it!) > > HTH., Syms.Article: 123159
hmm, but that doesn't explain why the bits have a different position. or i don't understand.Article: 123160
On 17 Aug., 15:14, lembke.ste...@googlemail.com wrote: > hmm, but that doesn't explain why the bits have a different position. > or i don't understand. the mapper can swap LUT input at will, as long as the logic function remains the same AnttiArticle: 123161
<lembke.stefan@googlemail.com> wrote in message news:1187356497.175275.112930@a39g2000hsc.googlegroups.com... > hmm, but that doesn't explain why the bits have a different position. > or i don't understand. > I believe they're in the right position. From left to right the bits represent ( ~A1 * ~A2 * ~A3 * ~A4 ) + ( A1 * ~A2 * ~A3 * ~A4 ) + ( ~A1 * A2 * ~A3 * ~A4 ) + ( A1 * A2 * ~A3 * ~A4 ) + ( ~A1 * ~A2 * A3 * ~A4 ) + ( A1 * ~A2 * A3 * ~A4 ) + ( ~A1 * A2 * A3 * ~A4 ) + ( A1 * A2 * A3 * ~A4 ) + ( ~A1 * ~A2 * ~A3 * A4 ) + ( A1 * ~A2 * ~A3 * A4 ) + ( ~A1 * A2 * ~A3 * A4 ) + ( A1 * A2 * ~A3 * A4 ) + ( ~A1 * ~A2 * A3 * A4 ) + ( A1 * ~A2 * A3 * A4 ) + ( ~A1 * A2 * A3 * A4 ) + ( A1 * A2 * A3 * A4 ) So, your equation is (A1+A2)*A4, which we re-write as ((A1+A2)*A4 * A3) + ((A1+A2)*A4 * ~A3) to include A3, can be re-written as ( A1 * ~A2 * ~A3 * A4 ) + ( ~A1 * A2 * ~A3 * A4 ) + ( A1 * A2 * ~A3 * A4 ) + ( A1 * ~A2 * A3 * A4 ) + ( ~A1 * A2 * A3 * A4 ) + ( A1 * A2 * A3 * A4 ) 0000 0000 0111 0111 TaaDaa! HTH., Syms.Article: 123162
cool thanks, let me think about it :)Article: 123163
On Aug 17, 2:42 pm, Niv <kev.pars...@mbda.co.uk> wrote: > It seems we're having trouble doing this. Is it possible to force/ > drive a particular pin to 'Z' via JTAG? You can use boundary-scan software for this purpose. I would recommend Scanseer http://www.scanseer.com. Put chip in EXTEST state and force any pin to any value you want.Article: 123164
On Aug 16, 8:28 pm, Chao <ss...@yahoo.com> wrote: > I am currently using FIFO16 with xilinx Virtex-4. I found out in my > design, the "almostempty" "almostfull" "empty" "full" flags are all stay > high. That means some errors happen. The FIFO16s are configured as: > > width 36 > depth 512 > almostempty offset 12'd128 > almostfull offset 12'd256 > first word fall through (FWFT) Mode "True" > read_clk 162Mhz > write_clk 200Mhz > > Is there any issues here? It's been reseted before use, (reset assertion > time is more than 3 clock cycles for both read and write clock). > > Anyone have similar experience or something wrong I doing. The clock > speed should be OK based on performance table. > > Thanks, > Chao I belive FIFO 16 in V4 has problems, I can't remember exactly what they are, but I do remember seeing some app notes with work-arounds. Check the Xilinx site FAQ and you should be able to find the info you're looking for.Article: 123165
On Aug 16, 2:39 am, ankur <ankurrawat0...@gmail.com> wrote: > hi > i am designing ahb arbiter . > In which i am using hmaster_lock as output signal . > when i am doing synthesis on xilinx 6.3 it is giving warning > > WARNING: FlipFlop hmaster_lock has been replicated 1 time(s) to handle > iob=true > attribute. > > pls help me why this warning is comming > > thanks > ankur It is generally safe to ignore these warnings. All this says that there are now two flip-flops in the part where there was only one in the design. The second (replicated) flip-flop is in the IOB (input output block) to meet the constraint "iob=true". Possibly the state of "hmaster_lock" is used internally to the FPGA as well as at the pin. In this case the flip-flop internal to the FPGA (in a slice) is used for internal feedback, while the flip-flop in the IOB only feeds the pin. If the D input to the flip-flop that creates the "hmaster_lock" signal uses only sources synchronous to its clock, there is no problem replicating the flip-flop. If for some reason you have an asynchronous signal feeding the D of the flip-flop, you can have a problem where the two flip-flops don't agree after their input changes within the setup/hold window. This is why the warning is issued. If "hmaster_lock" is not a signal that you generated yourself, i.e. it's part of a module you included, you probably don't need to worry about the warning. If you generate this signal check that the logic that creates it is synchronous. Other than replicating the signal yourself, which would make the source less readable and easier to break if you change it, there is no way to avoid the warning message. If you upgrade to a new version of ISE (which I normally would not recommend if you have a working project) you can filter the warnings so you don't need to re-visit them each time you re-build. HTH, Gabor PS - Warnings are not "errors", although they often help you to find mistakes in your design. If you work with FPGA's you should get used to the fact that it is not reasonable to expect a design to compile entirely without warnings.Article: 123166
Yes, there are known problems. The work-around is described in Answer Record 22462. You can also go to the Xilinx website and search for Virtex-4 FIFO AR. Peter AlfkeArticle: 123167
Hello, How feasible is it to shut down (or place in low power mode) an fpga (eg. XC3S1000 from Xilinx or similar) and power it up when it is needed (eg. after some interrupt to a microcontroller) ? If so, what hardware is used to provide it with power and still be controlled by a microcontroller ?Article: 123168
On 17 Aug., 20:06, amerdsp <amer...@hotmail.com> wrote: > Hello, > How feasible is it to shut down (or place in low power mode) an > fpga (eg. XC3S1000 from Xilinx or similar) and power it up when it is > needed (eg. after some interrupt to a microcontroller) ? If so, what > hardware is used to provide it with power and still be controlled by a > microcontroller ? you can do this with xilinx parts by shutting down supplies, but you need time afer wakeup for the FPGA to recongure itself, if that is not acceptable then you would need to use actel IGLOO AnttiArticle: 123169
"amerdsp" <amerdsp@hotmail.com> wrote in message news:1187373981.766730.134950@50g2000hsm.googlegroups.com... > Hello, > How feasible is it to shut down (or place in low power mode) an > fpga (eg. XC3S1000 from Xilinx or similar) and power it up when it is > needed (eg. after some interrupt to a microcontroller) ? If so, what > hardware is used to provide it with power and still be controlled by a > microcontroller ? Check the Spartan-3 Generation FPGA User Guide (http://www.xilinx.com/bvdocs/userguides/ug331.pdf). In Section III the "Powering Spartan-3 Generation FPGAs" subsection has an entry for "Saving Power" which will give you all the details on what you can do and what the impacts are on the power-savings mode you select.Article: 123170
"Antti" <Antti.Lukats@googlemail.com> wrote in message news:1187374487.103341.159090@50g2000hsm.googlegroups.com... > On 17 Aug., 20:06, amerdsp <amer...@hotmail.com> wrote: > > Hello, > > How feasible is it to shut down (or place in low power mode) an > > fpga (eg. XC3S1000 from Xilinx or similar) and power it up when it is > > needed (eg. after some interrupt to a microcontroller) ? If so, what > > hardware is used to provide it with power and still be controlled by a > > microcontroller ? > > you can do this with xilinx parts by shutting down supplies, but you > need time afer wakeup for the FPGA to recongure itself, if that is not > acceptable then you would need to use actel IGLOO > > Antti > Xilinx also now has a nonvolatile version of spartan-3. -ClarkArticle: 123171
"cpope" <cepope@nc.rr.com> wrote in message news:46c5fb80$0$16474$4c368faf@roadrunner.com... > > Xilinx also now has a nonvolatile version of spartan-3. -Clark > The Spartan-3AN is not instant-on, however. The Spartan-3 Family User Guide mentions what can be done with the 3AN as well as other devices to save power or work from shutdown.Article: 123172
Hello group, We are modelling our ASIC in an FPGA (Spartan) for system testing and as a demonstrator. For power reasons, we have globally (centrally) gated clocks of frequency f, f/2, f/4 etc (named clk_div2, clk_div4) Both the clocks and the gating signals (clk_en) are distributed to the endpoints so that in the FPGA we only have one clock of frequency f (named clk) For the FPGA, I add a BUFG at the root of clock f, use a generic to disable all clock gates, and apply a constraint for the frequency. The question is : How do I constrain the frequency f/2, f/4 etc. The synthesis tool optimizes nets clk_div2, clk_div4 so that only one net exists (clk), so I have no where to put the constraints (or do select all endpoints). (I currently add constraints via the UCF). Any suggestions or pointers grreatly appreciated. Thanks, StevenArticle: 123173
Please check these points... 1. Signal routing distance between Board2 Cyclone II FPGA & Borad3 Max II CPLD. 2. TDI pins of Microcontroller(Port pin) & MAX II CPLD should have have pull up resistors. 3. Microcontroller TDI should be MAX II CPLD TDO and Microcontroller TDO should be MAX II CPLD TDI. I think Andrew point is correct. Because TDO of Microcontroller should drive TDI of MAX II CPLD. Regards, JKArticle: 123174
On Aug 18, 6:24 am, moo...@yahoo.co.uk wrote: > Hello group, > > We are modelling our ASIC in an FPGA (Spartan) for system testing and > as a demonstrator. > > For power reasons, we have globally (centrally) gated clocks of > frequency f, f/2, f/4 etc (named clk_div2, clk_div4) Both the clocks > and the gating signals (clk_en) are distributed to the endpoints so > that in the FPGA we only have one clock of frequency f (named clk) > > For the FPGA, I add a BUFG at the root of clock f, use a generic to > disable all clock gates, and apply a constraint for the frequency. > > The question is : How do I constrain the frequency f/2, f/4 etc. The > synthesis tool optimizes nets clk_div2, clk_div4 so that only one net > exists (clk), so I have no where to put the constraints (or do select > all endpoints). > > (I currently add constraints via the UCF). > > Any suggestions or pointers grreatly appreciated. > > Thanks, > > Steven Hi Steven, If possible, stick with the single clock constraint on the main clock with a frequency of f. This will cause the delay between flip flops in the logic intended to be clocked by clk_div2 and clk_div4 to be 2* and 4* faster than really necessary, but will keep things simple, and easy. Everything should work just the same. Unfortunately, you may find that the clk_div2 and clk_div4 regions are nowhere near meeting timing with this constraint. In that case, you will need to relax timing in those areas using "multi-cycle paths". I suggest that you read up on this subject, and look in the Help for your tools as to how to apply them. I always try to avoid multi-cycle paths, as verification that they are done correctly requires a timing simulation after place and route. (e.g. A functional (non-timing) simulation will not find a problem where your logic samples the value out of the multi-cycle path earlier than it is available). My simulator crashes due to lack of memory under Win 32 whenever I have tried a post place and route timing simulation. I guess that you will have to run such simulations for the ASIC, so this might not be a problem for you. Good Luck, Ken Morrow, Morrow Electronics Limited www.morro.co.uk (currently down, but back soon) Email address is invalid. Remove the letter after my first name for the valid address.
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