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>>> I recently removed the series and parallel terminations from a Cyclone >>> 3 dev board and ran the ddr interface at 133MHz. The interface worked >>> overnight without a problem. See this Samsung App Note: http://tinyurl.com/2rrsoa TimArticle: 123201
fpgabuilder wrote: > On Aug 19, 11:15 am, PeteS <axk...@dsl.pipex.com> wrote: >> Nico Coesel wrote: >>> pgw <"SwietyMikolaj["@]poczta.onet.pl> wrote: >>>> Hello >>>> I decided to make my own DDR controller. I want to do this on CycloneII or >>>> Spartan-3 I'm not decided yet. That's way I want to ask the quastion: >>>> Which of this device familly has better features to design a DDR controller >>>> core. >>>> That what I know now: >>>> Altera Cyclone2: >>>> - PLL >>>> - Clock Delay Control Circuitry for DQS signal - it's look interesting >>>> - altdq and altdqs megafunctions to implement output and input logic >>>> - Series On-Chip Termination >>>> Xilinx Spartan3: >>>> - DCM >>> A normal and 90 degrees phase shifted clock are all that is required >>> to clock a DDR controller. >> For the perfect (or close to it) case. A practical DDR controller >> running at 200/400 or greater benefits greatly from having the ability >> to add/subtract a small delay around the 90 degrees. Whether the delay >> is useful depends on the application. >> >> >> >> >> >>>> - Programmable Delay on each input pin. - How it's work? How to use it? >>> Not necessary for DDR (should be left disabled) >> See above. >> >>>> - IFDDRxxx and OFDDRxxx components implement output and input logic >>> Yes, These are very necessary. Clock the signals as close to the IO >>> pin as possible. The setup and hold times will vary more as the amount >>> of logic increases which is something you don't want. >>>> - Digitally Controlled Impedance (DCI) - but require some pins: VREN, >>>> VREP >>> Useless. It will make the chip run very hot especially with many lines >>> connected. Use series resistors on the board. >> Agreed, but DDR should have a known impedance at the driver and >> receiver, which I believe the SSTL (II) IO standard provides. >> >> > > I recently removed the series and parallel terminations from a Cyclone > 3 dev board and ran the ddr interface at 133MHz. The interface worked > overnight without a problem. > > I think the trace length on the ddr signals is about 2-3 inches. They > are point-to-point signals. The data bus is 16bits wide and is > implemented using Altera's ALTMEMPHY megafunction. Further, I > momentarily cooled down the memory and altera chips to -40degC and > then heated them up to 125degC without any errors. > > I see that without the series terminations there is a problem on the > overshoot and undershoot. But it does not violate the specs of the > fpga. On the memory side, the problem goes away when I use onchip > series termination. > > The decision as to whether to parallel terminate is based on a number of things, as is the decision to simply series terminate. It depends on the application. Generally, if the data lines are point to point (2 connections only) you can get away with series termination (but it's not that simple - some thought needs to be given to the termination value) - if you have more than one endpoint, series termination is not possible for guaranteed operation, which is why series termination of address/control is generally not possible for guaranteed operation. Cheers PeteSArticle: 123202
John Retta wrote:
> I suspect your "simple" example might be more illustrative
> of a common problem
It is certainly a common problem in this newsgroup.
A multi-cycle constraint is a last resort in my book.
It is a fussy monkey on the back of the design that
must be tinkered with any time the circuit
is modified, branched or retargeted.
It would take me much more time to
repeatedly verify, that I had this
vendor-specific constraint
described correctly than it would
to fix the design to meet single-cycle
timing in the first place.
And like you said, this is a very simple example.
-- Mike Treseler
Article: 123203On 18 Aug, 14:52, "Symon" <symon_bre...@hotmail.com> wrote: > <moo...@yahoo.co.uk> wrote in message > > news:1187414658.093964.216970@k79g2000hse.googlegroups.com...> Hello group, > > > The question is : How do I constrain the frequency f/2, f/4 etc. The > > synthesis tool optimizes nets clk_div2, clk_div4 so that only one net > > exists (clk), so I have no where to put the constraints (or do select > > all endpoints). > > > (I currently add constraints via the UCF). > > > Any suggestions or pointers grreatly appreciated. > > > Thanks, > > > Steven > > Hi Steven, > OK, your system sounds like you have one clock, witth clock enables for the > slower bits. That's a good thing. > > So, you constraints should be something like this. > > NET "clock_div_2_enable*" TNM="slow_ffs"; > TIMESPEC TS1 = FROM : slow_ffs : TO : slow_ffs : 20ns; > > I added a wildcard at the end of the clock enable signal because often the > synthesis tool will duplicate nets that go to a lot of desitinations. This > will hopefully catch that situation. Also, be careful not to generate the > enable signal by feeding it back to itself, or the tool will include the FF > used to make the enable in the timegroup. You don't want that as the enable > has to get to every destination in the time determined by the clock period, > not the relaxed multi-path delay. For example, have a counter and use it to > generate the enables. > > HTH., Syms. Good idea, I hadn't thought of using the enable to define the timing groups - I was looking at the clock only. > > p.s. Here's a freebie puzzle I remembered while typing this. > What's the only word that's an anagram of itself? Stifle :-) ? Thanks, StevenArticle: 123204
Yes i enabled "Mark to initialize BRAM". I have two lmb bram controller connected to dlmb bus.One port of each controller is external.This external ports is connected to brams in ISE project.(bram controllers in XPS, brams in ISE.)I have some other RTL designs connected to these brams.I will write data to bram in ISE then i read the data with microblaze then make some floating point operations in microblaze and write the data to other bram. Fatih >Have you enabled "Mark to initialize BRAM" on multiple software applications >in XPS? >Can you share some more information on your system and your settings? > >Göran >Article: 123205
Yes i enabled "Mark to initialize BRAM". I have two lmb bram controller connected to dlmb bus.One port of each controller is external.This external ports is connected to brams in ISE project.(bram controllers in XPS, brams in ISE.)I have some other RTL designs connected to these brams.I will write data to bram in ISE then i read the data with microblaze then make some floating point operations in microblaze and write the data to other bram. Fatih >Have you enabled "Mark to initialize BRAM" on multiple software applications >in XPS? >Can you share some more information on your system and your settings? > >Göran >Article: 123206
I think that you shouldn't have the BRAMs in the ISE. Place them in XPS and then do the other bram ports as external ports. Doubt that this is the issue since the linker complains that your memory is full. Have you checked how the linker scripts look like? Göran "mfgunes" <mfgunes@yahoo.com> wrote in message news:5oudnb-d6aukoVTbRVn_vw@giganews.com... > Yes i enabled "Mark to initialize BRAM". > I have two lmb bram controller connected to dlmb bus.One port of each > controller is external.This external ports is connected to brams in ISE > project.(bram controllers in XPS, brams in ISE.)I have some other RTL > designs connected to these brams.I will write data to bram in ISE then i > read the data with microblaze then make some floating point operations in > microblaze and write the data to other bram. > > Fatih > > > > > > > >>Have you enabled "Mark to initialize BRAM" on multiple software > applications >>in XPS? >>Can you share some more information on your system and your settings? >> >>Göran >> >Article: 123207
This system is working for integers etc...I controlled the values with debugger and leds on my board. I have problems on floating point operations. I think i can beat this problem with using fix point library instead of doing operations with floats...Is there any fix point library in EDK? >I think that you shouldn't have the BRAMs in the ISE. >Place them in XPS and then do the other bram ports as external ports. >Doubt that this is the issue since the linker complains that your memory is >full. >Have you checked how the linker scripts look like? > >Göran >Article: 123208
<moogyd@yahoo.co.uk> wrote in message news:1187591749.726865.229200@o80g2000hse.googlegroups.com... > On 18 Aug, 14:52, "Symon" <symon_bre...@hotmail.com> wrote: > > Good idea, I hadn't thought of using the enable to define the timing > groups - I was looking at the clock only. > My pleasure. >> >> p.s. Here's a freebie puzzle I remembered while typing this. >> What's the only word that's an anagram of itself? > > Stifle :-) ? > > Thanks, > > Steven > Very good! :-) Cheers, Syms.Article: 123209
Hello I have just the MCS file and I want to configure directly my FPGa with a bitstream. So I had to convert the MCS in BIT. What I have done: 1)MCS->HEX with promgen: promgen -r <promfile> -p hex 2)HEX->BIT with Hex2bits : hex2bits -k <hexfile> <bitfile> But iMPACT doen't work with the generated bitstream. Do you have any idea ? Thanks !Article: 123210
On 20 Aug., 14:45, LilacSkin <lpaul...@iseb.fr> wrote: > Hello > > I have just the MCS file and I want to configure directly my FPGa with > a bitstream. > So I had to convert the MCS in BIT. > > What I have done: > 1)MCS->HEX with promgen: promgen -r <promfile> -p hex > 2)HEX->BIT with Hex2bits : hex2bits -k <hexfile> <bitfile> > > But iMPACT doen't work with the generated bitstream. > Do you have any idea ? > > Thanks ! where did you get "hex2bits" its not bundled with ISE (9.2) ?? if you know the option when the MCS was made you can write own scripts/ tools that can recover BIT file(s) but this is not always trivial AnttiArticle: 123211
On 20 ao=FBt, 15:00, Antti <Antti.Luk...@googlemail.com> wrote: > On 20 Aug., 14:45, LilacSkin <lpaul...@iseb.fr> wrote: > > > Hello > > > I have just the MCS file and I want to configure directly my FPGa with > > a bitstream. > > So I had to convert the MCS in BIT. > > > What I have done: > > 1)MCS->HEX with promgen: promgen -r <promfile> -p hex > > 2)HEX->BIT with Hex2bits : hex2bits -k <hexfile> <bitfile> > > > But iMPACT doen't work with the generated bitstream. > > Do you have any idea ? > > > Thanks ! > > where did you get "hex2bits" its not bundled with ISE (9.2) ?? > > if you know the option when the MCS was made you can write own scripts/ > tools that can recover BIT file(s) > but this is not always trivial > > Antti Hex2bits is a separatly downloadable tool made by Xilinx: http://www.xilinx.com/support/troubleshoot/htm_index/utils_prom.htmArticle: 123212
On 20 ao=FBt, 15:05, LilacSkin <lpaul...@iseb.fr> wrote: > On 20 ao=FBt, 15:00, Antti <Antti.Luk...@googlemail.com> wrote: > > > > > > > On 20 Aug., 14:45, LilacSkin <lpaul...@iseb.fr> wrote: > > > > Hello > > > > I have just the MCS file and I want to configure directly my FPGa with > > > a bitstream. > > > So I had to convert the MCS in BIT. > > > > What I have done: > > > 1)MCS->HEX with promgen: promgen -r <promfile> -p hex > > > 2)HEX->BIT with Hex2bits : hex2bits -k <hexfile> <bitfile> > > > > But iMPACT doen't work with the generated bitstream. > > > Do you have any idea ? > > > > Thanks ! > > > where did you get "hex2bits" its not bundled with ISE (9.2) ?? > > > if you know the option when the MCS was made you can write own scripts/ > > tools that can recover BIT file(s) > > but this is not always trivial > > > Antti > > Hex2bits is a separatly downloadable tool made by Xilinx:http://www.xilin= x=2Ecom/support/troubleshoot/htm_index/utils_prom.htm- Masquer le texte des= messages pr=E9c=E9dents - > > - Afficher le texte des messages pr=E9c=E9dents - Have you ever did it ? The MCS is generated with a Xilinx PROM xcf32p not compressed with 2 revisionsArticle: 123213
Has any one measured the cycles needed for a single I/O function using a GPIO peripheral with the PowerPC processor (Virtex-II Pro device). I have measured using a counter and i takes 115 cycles. I think these are a lot o cycles. Is there anything I can do to reduce the cycles?Article: 123214
Hi Eli, Synplify has an attribute called 'direct_enable'. Use it on your enable net to make sure you don't get the problem you describe. HTH., Syms.Article: 123215
I need to do the voltage translation from V5 3.3V push-pull output to one of the traget device input. The input accepts 0.8V on the positive rail and -2.5V on the negative rail. I am looking at a pair of NPN and PNP transistors but would like to know if there is off the shelf device that can can do this. EddieArticle: 123216
I think you can still use the CLKFX_MULTIPLY and CLKFX_DIVIDE attribute to implment. For example, if you need divide-by-2 clock, set M=2 and D=4;if divide-by-3, set M=2, D=6 and so on. Here the minimum M is 2 so you need a bigger D . On Aug 19, 12:36 pm, "Symon" <symon_bre...@hotmail.com> wrote: > "davide" <dav...@xilinx.com> wrote in message > > news:fa2j1c$g1r2@cnn.xilinx.com...> Symon, > > > I believe that DRP can only change the attributes for phase shift, M and D > > values of the DCM. Not CLKDV values. > > > -David > > Hi David, > Yeah, looks like you're right. I might try some addresses when I get chance, > if I find anythign I'll report back... > Cheers, Syms.Article: 123217
On Aug 20, 9:43 am, "Eddie H" <> wrote: > I need to do the voltage translation from V5 3.3V push-pull output to one of the traget device input. The input accepts 0.8V on the positive rail and -2.5V on the negative rail. I am looking at a pair of NPN and PNP transistors but would like to know if there is off the shelf device that can can do this. > > Eddie Are you saying the supply rails of the device are +0.8 and -2.5V or that the logic level requirements are to swing from +0.8 (Vih_min) to -2.5V (Vil_max)? How fast does the logic run? What sort of latency can you live with? Is there guaranteed AC content in the signal? Some possibilities include capacitive level shifting, current-limited RS-232 drivers with diode clamps, low-voltage zener with a resistive pulldown... If a couple of transistors can do the job, why not just use those? How many signals do you need to shift? Can you use arrays of transistors? HTH, GaborArticle: 123218
Hi all,
I am currently work on multiple Microblazes too. I met this error
message when instantiion.
------------------------------------------------------------------------------------------------------------------------------------
Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
ERROR:MDT - xget_handle 43974304 44798020 parent : a null handle was
provided
ERROR:MDT - microblaze_3 (microblaze) - expected integer but got
"43974304
44798020"
while executing
"xget_handle $inhandle "parent""
(procedure "xget_hw_parent_handle" line 2)
invoked from within
"xget_hw_parent_handle $master_addrstrobe_sink"
(procedure "::hw_microblaze_v5_00_c::check_syslevel_settings"
line 20)
invoked from within
"::hw_microblaze_v5_00_c::check_syslevel_settings 34520024"
------------------------------------------------------------------------------------------------------------------------------------
The EDK version is 8.2. And I have connected each processor with an
opb bus and a lmb bus.
Thanks.
Young Zhang
Article: 123219Theere are some signals that are just static signals and do not need to run at high speed. There are other signals that act like SPI bus and may run at 25MHz. I do not that that can AC couple it as it is not a free running clock. EddieArticle: 123220
On 20 Aug., 15:16, Vangelis <> wrote: > Has any one measured the cycles needed for a single I/O function using a GPIO peripheral with the PowerPC processor (Virtex-II Pro device). I have measured using a counter and i takes 115 cycles. I think these are a lot o cycles. Is there anything I can do to reduce the cycles? advice 1, dont use xilinx drivers ;) AnttiArticle: 123221
Thamx for the reply, but where can I find others drivers?Article: 123222
There is no ISE 9.3. Maybe they meant ISE 9.2.03i (service pack 3) which is scheduled to release September 14. Steve "Andreas Schwarz" <usenet@andreas-s.net> wrote in message news:1187203614.592844.20690@d55g2000hsg.googlegroups.com... > On 14 Aug., 03:52, David Bishop <dbis...@vhdl.org> wrote: >> Xilinx said that they were going to fix this in 9.3. I have not had a >> chance to check it out yet, but I would try that first. > > Thanks for the info. 9.3 isn't released yet, do you have any idea when > it will be? > > Andreas >Article: 123223
"LilacSkin" <lpaulo07@iseb.fr> wrote in message news:1187615555.726752.286330@g4g2000hsf.googlegroups.com... On 20 aoűt, 15:05, LilacSkin <lpaul...@iseb.fr> wrote: > On 20 aoűt, 15:00, Antti <Antti.Luk...@googlemail.com> wrote: > > > > > > > On 20 Aug., 14:45, LilacSkin <lpaul...@iseb.fr> wrote: > > > > Hello > > > > I have just the MCS file and I want to configure directly my FPGa with > > > a bitstream. > > > So I had to convert the MCS in BIT. > > > > What I have done: > > > 1)MCS->HEX with promgen: promgen -r <promfile> -p hex > > > 2)HEX->BIT with Hex2bits : hex2bits -k <hexfile> <bitfile> > > > > But iMPACT doen't work with the generated bitstream. > > > Do you have any idea ? > > > > Thanks ! > > > where did you get "hex2bits" its not bundled with ISE (9.2) ?? > > > if you know the option when the MCS was made you can write own scripts/ > > tools that can recover BIT file(s) > > but this is not always trivial > > > Antti > > Hex2bits is a separatly downloadable tool made by > Xilinx:http://www.xilinx.com/support/troubleshoot/htm_index/utils_prom.htm- > Masquer le texte des messages précédents - > > - Afficher le texte des messages précédents - Have you ever did it ? The MCS is generated with a Xilinx PROM xcf32p not compressed with 2 revisions Why can't you revert back to the original BIT files used to generate the MCS? There are only two possible inputs to generate an MCS. One is a BIT file, the other an RBT (an additional .elf is required for uP designs). Can one guess that these are not available? What about the NCD files? Do you use encryption or does the design flow use .bmm/.elf files? I have not played around with Hex2bits, so I can't add much here. But how did iMPACT fail? This might gives some clues as to where to start debugging. -DavidArticle: 123224
Hi all, Can anyone suggest me how to run an exe file in modelsim...I have tried using sccom -g basedes.cpp baseDesc.cpp -Wno-deprecated.Compilation and linking was successful but i dont know the command to run an exe file Thanks in advance, fazal
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